CN110165026B

CN110165026B - LED chip, preparation method thereof, display module and intelligent terminal

Info

Publication number: CN110165026B
Application number: CN201910273288.2A
Authority: CN
Inventors: 曲爽; 代郁峰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-04-04
Filing date: 2019-04-04
Publication date: 2020-11-10
Anticipated expiration: 2039-04-04
Also published as: CN110165026A

Abstract

The embodiment of the application provides an LED chip and a preparation method thereof, a display module and an intelligent terminal, relates to the technical field of semiconductors, and is used for solving the problem that PL detection cannot be carried out on a large number of micro LEDs. The LED chip includes at least a portion of the main device and the antenna structure. The main device includes a main epitaxial layer, a first electrode, and a second electrode. The main epitaxial layer comprises a first semiconductor layer and a first functional layer covering partial area of the upper surface of the first semiconductor layer. The first functional layer includes a second semiconductor layer and a first light emitting layer. The first light emitting layer is located between the first semiconductor layer and the second semiconductor layer. The first electrode is disposed on an upper surface of the first semiconductor layer and coupled to the first semiconductor layer. The second electrode is disposed on the upper surface of the second semiconductor layer and coupled to the second semiconductor layer. An antenna structure is coupled to the first electrode and the second electrode. The antenna structure is for receiving a radio frequency signal and generating a potential difference between the first electrode and the second electrode.

Description

LED chip, preparation method thereof, display module and intelligent terminal

Technical Field

The application relates to the technical field of semiconductors, in particular to an LED chip and a preparation method thereof, a display module and an intelligent terminal.

Background

With the development of display technology, micro organic Light Emitting Diodes (LEDs) are used as a current type light emitting device for Liquid Crystal Displays (LCDs), and are increasingly applied to the high performance display field due to their self-luminescence, high luminous efficiency, color saturation, brightness, reliability, and the like.

In the micro LED display screen, each micro LED can be used as a sub-pixel (sub-pixel). In order to reduce the probability of dead pixels (sub-pixels incapable of emitting light) in the display process of the micro LED display screen, Photo Luminescence (PL) detection needs to be performed on the micro LEDs in the manufacturing process. However, since the size of a single micro LED is small (in micron level), and the number of micro LEDs in the display screen is large, the micro LEDs in the display screen cannot be detected one by one.

Disclosure of Invention

The embodiment of the application provides an LED chip, a preparation method thereof, a display module and an intelligent terminal, and is used for solving the problem that PL detection cannot be performed on a large number of micro LED chips.

In order to achieve the above purpose, the following technical solutions are adopted in this embodiment:

in a first aspect of the embodiments of the present application, an LED chip is provided. The LED chip includes a main device and an antenna structure. The main device includes a main epitaxial layer, a first electrode, and a second electrode. The main epitaxial layer comprises a first semiconductor layer and a first functional layer covering partial area of the upper surface of the first semiconductor layer. The first functional layer includes a second semiconductor layer and a first light emitting layer. The first light-emitting layer is located between the first semiconductor layer and the second semiconductor layer. In addition, the first electrode is disposed on the upper surface of the first semiconductor layer and coupled to the first semiconductor layer. The second electrode is disposed on the upper surface of the second semiconductor layer and coupled to the second semiconductor layer. An antenna structure is coupled to the first electrode and the second electrode. The antenna structure is for receiving a radio frequency signal and generating a potential difference between the first electrode and the second electrode. In this case, before the chip wafer is cut to obtain the LED chips, the rf signals may be transmitted to the antenna structures in the chip wafer. When the antenna structure receives a radio frequency signal, a potential difference is generated between the first electrode and the second electrode which are coupled with the antenna structure. The electromotive force may cause a potential difference between the first electrode and the second electrode, and thus an electric field is formed between the first electrode and the second electrode. The electric field enables electrons in the first semiconductor layer (i.e., N-type semiconductor) to recombine with holes in the second semiconductor layer (i.e., P-type semiconductor) in the first light emitting layer and emit energy in the form of photons to drive the respective main devices to emit light. So that it can be judged whether each master device has failed. Each main device belonging to the same chip wafer can be detected in one-time luminescence detection, so that the problem that a large number of LED chips cannot be detected can be solved. After the light emitting detection is finished, the chip wafer can be cut to obtain a plurality of LED chips. In this case, after the LED chips are flip-chip mounted on the substrate to form the display module, the first electrode and the second electrode of each LED chip receive the dc signal and emit light during the display process of the display module. Therefore, the direct current signal can not cause the antenna structure to induce electromotive force in the display process of the display module, so that the display of the display module can not be influenced.

Optionally, the antenna structure comprises a conductive coil located outside the main epitaxial layer. The first end of the conductive coil forms a capacitor with the first electrode, and the second end of the conductive coil is in contact with the second electrode. Or the first end of the conductive coil and the first electrode form a capacitor, and the second end of the conductive coil and the second electrode form a capacitor. The capacitor has the function of connecting alternating current and blocking direct current, so that the first end of the conductive coil can be coupled with the first electrode after the conductive coil receives a radio frequency signal. Similarly, under the condition that the second end of the conductive coil and the second electrode form a capacitor, the second end of the conductive coil and the second electrode can be coupled through the effect of alternating current and direct current blocking of the capacitor after the conductive coil receives the radio-frequency signal.

Optionally, when a capacitance is formed between the first end of the conductive coil and the first electrode, a gap is formed between the first end of the conductive coil and the first electrode, and an orthographic projection of the conductive coil on the main epitaxial layer has no overlapping region with an orthographic projection of the first electrode on the main epitaxial layer. The technical effects of the capacitor are the same as those described above, and are not described herein again.

Optionally, in a case that a capacitance is formed between the first end of the conductive coil and the first electrode, a groove is formed on a side of the first electrode close to the conductive coil. The first end of the conductive coil extends into the groove, and a gap is formed between the first end of the conductive coil and the inner wall of the groove so as to form a capacitor between the first end of the conductive coil and the inner wall of the groove. The technical effects of the capacitor are the same as those described above, and are not described herein again.

Optionally, the conducting direction of the main device is directed from the second electrode to the first electrode. The above-mentioned antenna structure includes: the sub-devices, the conductive wire outside the main epitaxial layer, and the conductive coil. The sub-device comprises a sub-epitaxial layer, and a first auxiliary electrode and a second auxiliary electrode which are arranged on the sub-epitaxial layer. The sub-epitaxial layer is insulated from the main epitaxial layer. In addition, the conduction direction of the sub-device is directed from the second auxiliary electrode to the first auxiliary electrode. In this case, one end of the conductive coil is in contact with the first electrode, and the other end is in contact with the second auxiliary electrode. One end of the wire is in contact with the first auxiliary electrode, and the other end is in contact with the second electrode. In this case, the first electrode is an N-electrode, and the second electrode is a P-electrode. When the conductive coil in the antenna structure receives the radio-frequency signal, the conductive coil in the antenna structure is directed to the first electrode from the second electrode, so that when positive voltage in the signal is applied to the first electrode, the main device is not conducted, and potential difference cannot be generated between the first electrode and the second electrode. Further, when a positive voltage in the radio frequency signal as the alternating current signal is applied to the second auxiliary electrode in the sub device, the voltage on the first electrode of the main device may be a negative voltage. The conducting direction of the sub-device is from the second auxiliary electrode to the first auxiliary electrode, so that the sub-device is conducted, and the voltage received by the first auxiliary electrode on the sub-device is still positive after a certain voltage drop. Since the first auxiliary electrode of the sub-device is electrically connected with the second electrode of the main device through a wire, the voltage on the second electrode is positive and the voltage of the first auxiliary electrode of the sub-device is the same. In this case, a potential difference is generated between the first electrode and the second electrode of the main device, so that the main device can be driven to emit light, and light emission detection is realized. After the chip wafer subjected to luminescence detection is separated to obtain a plurality of LED chips, and the LED chips are arranged in an LED display screen, when the LED chips are required to be luminous, positive voltage is applied to the second electrodes in the LED chips, and negative voltage is applied to the first electrodes. In this case, the LED chip will operate normally. And because the conduction direction of the LED chip sub-device is that the second auxiliary electrode points to the first auxiliary electrode, and the second auxiliary electrode can not obtain positive pressure, the LED chip sub-device can not be conducted, thereby avoiding the influence of the sub-device on the luminous brightness of the LED chip in the display process. In addition, the above-mentioned conductive coil is arranged in the same manner as above, and there may be no overlapping at any place, or there are at least two parts that are crossed and arranged in an insulating manner in the conductive coil, which is not described herein again. The first electrode or the second electrode may be disposed within the conductive coil. Alternatively, the conductive coil may be disposed between the first electrode and the second electrode, which is not described herein.

Optionally, the sub-epitaxial layer includes a third semiconductor layer and a second functional layer covering a partial region of an upper surface of the third semiconductor layer. The second functional layer includes a fourth semiconductor layer and a second light emitting layer. The second light emitting layer is located between the third semiconductor layer and the fourth semiconductor layer. The first auxiliary electrode is disposed on the upper surface of the third semiconductor layer and coupled to the third semiconductor layer. The second auxiliary electrode is disposed on the upper surface of the fourth semiconductor layer and coupled to the fourth semiconductor layer. In this case, the third semiconductor layer, the second functional layer, and the third semiconductor layer in the sub-epitaxial layer of the sub-device may be the same as the materials of the first semiconductor layer, the second light emitting layer, and the second semiconductor layer, respectively, in the main epitaxial layer of the main device. In addition, in the sub-epitaxial layer of the sub-device, in addition to the third semiconductor layer, the second functional layer, and the third semiconductor layer, the other film layers may be provided in the same manner as the structure and position of the corresponding thin film layer in the main epitaxial layer of the main device. In this way, the main epitaxial layer and the sub-epitaxial layer can be prepared simultaneously, then the main epitaxial layer and the sub-epitaxial layer are separated through an etching process, and a passivation layer with insulating property is arranged between the main epitaxial layer and the sub-epitaxial layer.

Optionally, the first auxiliary electrode and the second auxiliary electrode are both located on the upper surface of the fifth semiconductor layer and are coupled to the fifth semiconductor layer. The fifth semiconductor layer may be an N-type semiconductor layer. In this case, in the sub-device, the first auxiliary electrode (N-electrode) and the fifth semiconductor layer in the sub-epitaxial layer, and the second auxiliary electrode (P-electrode) and the fifth semiconductor layer in the sub-epitaxial layer form a schottky junction. At the moment, the number of the film layers in the sub epitaxial layer of the sub device is small, and the structure is simpler.

Optionally, any two turns of the coil in the conductive coil do not intersect. The orthographic projection of each part of the conductive coil on the main epitaxial layer has no overlapping area. Therefore, the conductive coil and the main epitaxial layer can be insulated by a passivation layer, and the structure of the LED chip can be simplified.

In a second aspect of the embodiments of the present application, an LED chip is provided. The LED chip includes the remainder of the main device and the antenna structure. The main device includes a main epitaxial layer, a first electrode, and a second electrode. The main epitaxial layer comprises a first semiconductor layer and a first functional layer covering partial area of the upper surface of the first semiconductor layer. The first functional layer includes a second semiconductor layer and a first light emitting layer. The first light-emitting layer is located between the first semiconductor layer and the second semiconductor layer. In addition, the first electrode is disposed on the upper surface of the first semiconductor layer and coupled to the first semiconductor layer. The second electrode is disposed on the upper surface of the second semiconductor layer and coupled to the second semiconductor layer. The residual part of the antenna structure comprises a first metal wire, a second metal wire and at least one third metal wire, wherein the first metal wire, the second metal wire and the at least one third metal wire are positioned outside the main epitaxial layer and insulated from the main epitaxial layer. The first metal wire, the second metal wire and the third metal wire are insulated from each other. In addition, one end of the first metal wire is in contact with the first electrode, and the other end of the first metal wire is flush with one edge of the LED chip. One end of the second metal wire is in contact with the second electrode, and the other end of the second metal wire is flush with one edge of the LED chip. A portion of the third metal line is located between the first metal line and the second metal line. Two ends of the third metal wire are flush with the same edge of the LED chip; or two ends of the third metal wire are respectively flush with two different edges of the LED chip. The first metal wire, the second metal wire and the third metal wire are structures which are used for cutting off the part of a complete conductive coil in a cutting channel when a chip wafer is cut, and the part of the complete conductive coil is remained on an LED chip after the LED chip is formed. Wherein the first end of each conductive coil is contacted with the first electrode of one main device, and the second end is contacted with the second electrode of the main device. Therefore, before the chip wafer is cut, a radio frequency signal can be sent to the conductive coil, and a potential difference is generated between the first electrode and the second electrode on the main device through the conductive coil, so that the light emitting test of each main device on the chip wafer is completed. And after the test is finished, cutting the chip wafer, cutting off the part of the conductive coil, which is positioned on the cutting channel, wherein the uncut residual parts are the first metal wire, the second metal wire and the third metal wire. In this case, one end of the first metal line is a first end of the conductive coil and is in contact with the first electrode. One end of the second metal wire is the second end of the conductive coil and is in contact with the second electrode. The third metal wire is disconnected with the first metal wire and the second metal wire. At this time, after the LED chips are inversely mounted on the substrate to form the display module, in the display process of the display module, when each LED chip normally works to receive a direct current signal, the electrical connection between the first electrode and the second electrode in the LED chip is interrupted. And then when the LED chip normally works, the residual part of the antenna structure on the LED chip can not influence the normal light emission of the LED chip.

Optionally, orthographic projections of the first metal line, the second metal line and the third metal line on the main epitaxial layer have no overlapping area. In addition, the first electrode is positioned in an area enclosed by the third metal wire and the edge of the LED chip with two ends of the third metal wire being flush. As can be seen from the above, the first metal line, the second metal line and the third metal line are the residual parts of the conductive coil. When orthographic projections of the first metal wire, the second metal wire and the third metal wire on the main epitaxial layer do not have an overlapping region, one part of the conductive coil is located in a cutting path between two adjacent main devices, and any two turns of the conductive coil do not intersect, namely, the orthographic projections of all parts of the conductive coil on the main epitaxial layer do not have the overlapping region. At this time, the first electrode or the second electrode in the master device may be located within the conductive coil. Therefore, the whole conductive coil and the main epitaxial layer can be insulated by a passivation layer, so that the structure of the LED chip can be simplified.

Optionally, the LED chip includes a plurality of third metal lines, and a gap is formed between two adjacent third metal lines. As described above, after the chip wafer is cut to obtain the LED chip, the orthographic projections of the metal lines remaining in the conductive coil on the main epitaxial layer have no overlapping area. In this way, a first passivation layer can be arranged between the whole conductive coil and the main epitaxial layer to insulate the conductive coil from the main epitaxial layer, so that the structure of the LED chip can be simplified.

Optionally, the first metal line is insulated from the third metal line. The orthographic projection of the first metal wire and the orthographic projection of the at least one third metal wire on the main epitaxial layer have an overlapping area. As can be seen from the above, the first metal line, the second metal line and the third metal line are the residual parts of the conductive coil. When orthographic projections of the first metal wire, the second metal wire and the third metal wire on the main epitaxial layer have an overlapping area, the conductive coil comprises a first sub-portion and a second sub-portion which are connected. The orthographic projection of the first sub-portion on the main epitaxial layer has an overlapping area with the orthographic projection of the second sub-portion on the main epitaxial layer. In this case, the portion of the first metal line overlapping the third metal line may be a second sub-portion of the conductive coil. And the third metal line and the second metal line may be part of the first sub-portion of the conductive coil. An insulating second passivation layer is disposed between the first and second sub-portions of the conductive coil. It is possible to insulate a portion of the first metal line that overlaps the third metal line. Therefore, the conductive coil is arranged between the first electrode and the second electrode of the main device, and the space of the conductive coil occupying the surface of the main epitaxial layer of the main device can be saved.

In a third aspect of the embodiments of the present application, a method for manufacturing an LED chip is provided. The preparation method comprises the following steps: a master device is fabricated in each build region on a substrate, which includes a plurality of build regions defined by streets crossing in a row and a column direction. The main epitaxial layer comprises a first semiconductor layer and a first functional layer covering partial area of the upper surface of the first semiconductor layer. The first functional layer includes a second semiconductor layer and a first light emitting layer. The first light emitting layer is located between the first semiconductor layer and the second semiconductor layer. The first electrode is arranged on the upper surface of the first semiconductor layer and is coupled with the first semiconductor layer; the second electrode is disposed on the upper surface of the second semiconductor layer and coupled to the second semiconductor layer. In addition, a plurality of antenna structures are manufactured, the antenna structures correspond to the assembly areas one by one, and each antenna structure is coupled with the first electrode and the second electrode in the corresponding assembly area to form the chip wafer. The antenna structure is used for receiving radio frequency signals and generating potential difference between the first electrode and the second electrode in the same building area. In addition, radio frequency signals are sent to the antenna structures, the light emitting brightness of each main device in the chip wafer is collected, and whether each main device can work normally or not is tested according to the light emitting brightness of each main device. In addition, the chip wafer is separated along the cutting channels, and a plurality of LED chips are obtained. The preparation method of the LED chip has the same technical effects as the LED chip provided in the foregoing embodiment, and details are not repeated here.

Optionally, the manufacturing of the antenna structure includes manufacturing a plurality of conductive coils outside the main epitaxial layer. The two ends of each conductive coil are respectively contacted with the first electrode and the second electrode which are positioned in the same building area, and at least one part of each conductive coil is positioned in a cutting channel between two adjacent building areas. After the chip wafer is cut to form the independent LED chips, the part of the conductive coil, which is positioned in the cutting channel, is removed, so that a metal wire which cannot be electrically connected, namely the residual part of the conductive coil, remains on the LED chips. Thus, when the LED chip is normally operated to receive a dc signal, the electrical connection between the first electrode and the second electrode in the LED chip is interrupted. And then when the LED chip normally works, the residual part of the antenna structure (namely the conductive coil) on the LED chip can not influence the normal light emission of the LED chip.

Optionally, the manufacturing of the antenna structure includes: and manufacturing a plurality of conductive coils outside the main epitaxial layer, wherein each conductive coil is positioned in one building area. A capacitor is formed between the first end of each conductive coil and the first electrode, and the second end of each conductive coil is in contact with the second electrode. Or a capacitor is formed between the first end of each conductive coil and the first electrode, and a capacitor is formed between the second end of each conductive coil and the second electrode. The capacitor has the function of connecting alternating current and blocking direct current, so that the first end of the conductive coil can be coupled with the first electrode after the conductive coil receives a radio frequency signal. Similarly, under the condition that the second end of the conductive coil and the second electrode form a capacitor, the second end of the conductive coil and the second electrode can be coupled through the effect of alternating current and direct current blocking of the capacitor after the conductive coil receives the radio-frequency signal.

Optionally, the manufacturing the first electrode includes: and manufacturing a first electrode on the upper surface of the first semiconductor layer, and forming a groove on the side surface of the first electrode. In addition, the step of manufacturing the conductive coil comprises that the first end of the conductive coil extends into the groove, and a gap is formed between the first end of the conductive coil and the inner wall of the groove so as to form a capacitor between the first end of the conductive coil and the inner wall of the groove. The technical effects of the capacitor are the same as those described above, and are not described herein again.

Optionally, the manufacturing of the antenna structure includes: and forming a sub-device in the building region, wherein the sub-device comprises a sub-epitaxial layer insulated from the main epitaxial layer, and a first auxiliary electrode and a second auxiliary electrode which are positioned on the sub-epitaxial layer. The conducting direction of the sub-device is directed from the second auxiliary electrode to the first auxiliary electrode. In addition, making the antenna structure further includes: and manufacturing a plurality of conductive coils and a plurality of leads outside the main epitaxial layer, wherein each building area is provided with one conductive coil and one lead. One end of the conductive coil in each building area is contacted with the first electrode, and the other end is contacted with the second auxiliary electrode. One end of one of the conductive wires in each of the build areas is in contact with the first auxiliary electrode, and the other end is in contact with the second electrode. The conduction direction of the main device is directed from the second electrode to the first electrode. The technical effects of the antenna structure formed by the sub-devices, the conducting wire positioned outside the main epitaxial layer and the conducting coil are the same as those described above, and are not described herein again.

In a fourth aspect of the embodiments of the present application, a display module is provided, which includes a substrate, and any one of the LED chips described above arranged on the substrate in an array. Each LED chip is a sub-pixel. The display module has the same technical effects as the LED chip provided in the foregoing embodiments, and details are not repeated herein.

In a fourth aspect of the embodiments of the present application, an intelligent terminal is provided, which includes a processor and a display module as described above, where the processor is configured to control the display module to display an image. The intelligent terminal has the same technical effect as the display module provided by the embodiment, and the description is omitted here.

Drawings

Fig. 1a is a schematic structural diagram of an intelligent terminal according to some embodiments of the present application;

fig. 1b is a schematic structural diagram of a display module according to some embodiments of the present disclosure;

FIG. 2 is a schematic diagram of the structure of the LED chip of FIG. 1;

FIG. 3 is a schematic diagram of the LED chip of FIG. 2 flip-chip mounted on a substrate;

fig. 4 is a flowchart of a method for manufacturing an LED chip according to some embodiments of the present disclosure;

FIG. 5 is a schematic diagram of a substrate with scribe lines according to some embodiments of the present disclosure;

FIG. 6a is a schematic structural diagram of the main epitaxial layer of FIG. 2;

FIG. 6b is another schematic structural view of the main epitaxial layer of FIG. 2;

fig. 7 is a schematic structural view of a plurality of epitaxial wafers provided in accordance with some embodiments of the present application;

fig. 8a, 8b, 8c, 8d, and 8e are schematic diagrams illustrating a process of fabricating a first electrode and a second electrode according to some embodiments of the present disclosure;

fig. 8f is a schematic structural diagram of an LED chip according to some embodiments of the present application;

FIG. 8g is a schematic diagram of another LED chip according to some embodiments of the present application;

FIG. 8h is a schematic illustration of a structure of a wafer of chips having first and second electrodes fabricated thereon according to some embodiments of the present application;

fig. 9 is a top view of a chip wafer according to some embodiments of the present application;

FIG. 10 is a schematic diagram of a method for separating different LED chips from a plurality of chip wafers and forming a display module according to some embodiments of the present disclosure;

FIG. 11a is a top view of another chip wafer according to some embodiments of the present application;

FIG. 11b is a cross-sectional view taken along the dashed line O1-O1 in FIG. 11 a;

FIG. 11c is a schematic structural diagram of an LED chip obtained by separating the chip wafer shown in FIG. 11 a;

FIG. 11d is a schematic structural diagram of another LED chip obtained by separating the chip wafer shown in FIG. 11 a;

fig. 11e is a schematic structural diagram of another LED chip obtained by separating the chip wafer shown in fig. 11 a;

FIG. 12 is a schematic diagram of a test apparatus according to some embodiments of the present application;

FIG. 13 is a schematic illustration of test results obtained using the test apparatus shown in FIG. 12;

FIG. 14a is a cross-sectional view of an LED chip taken along the line D-D of FIG. 11 a;

FIG. 14b is a cross-sectional view of an alternative LED chip taken along the line D-D of FIG. 11 a;

FIG. 15a is a top view of another alternative chip wafer according to some embodiments of the present application;

FIG. 15b is a cross-sectional view of an LED chip taken along the dashed line Q1-Q1 in FIG. 15 a;

FIG. 15c is a schematic structural diagram of an LED chip obtained by separating the chip wafer shown in FIG. 15 a;

FIG. 16a is a top view of another alternative chip wafer according to some embodiments of the present application;

FIG. 16b is a schematic structural diagram of an LED chip obtained by separating the chip wafer shown in FIG. 16 a;

FIG. 16c is a cross-sectional view of an LED chip taken along the dashed line O2-O2 in FIG. 16 a;

FIG. 16d is a cross-sectional view of another LED chip taken along the dashed line O2-O2 in FIG. 16 a;

FIG. 16e is a cross-sectional view of another LED chip taken along the dashed line O2-O2 in FIG. 16 a;

FIG. 16f is a cross-sectional view of another LED chip taken along the dashed line O2-O2 in FIG. 16 a;

FIG. 17a is a top view of another LED chip provided in accordance with some embodiments of the present application;

FIG. 17b is a cross-sectional view of an LED chip taken along the dashed line O2-O2 in FIG. 17 a;

FIG. 18 is a schematic block diagram of another test apparatus provided in accordance with certain embodiments of the present application;

FIG. 19a is a top view of another alternative chip wafer according to some embodiments of the present application;

FIG. 19b is a schematic structural diagram of an LED chip obtained by separating the chip wafer shown in FIG. 19 a;

FIG. 19c is a cross-sectional view of an LED chip taken along the dashed line O3-O3 in FIG. 19 b;

FIG. 19d is a cross-sectional view of an LED chip taken along the line Q3-Q3 of FIG. 19 b;

FIG. 20a is a schematic cross-sectional view of the neutron device of FIG. 19 b;

fig. 20b is a schematic cross-sectional view of the neutron device of fig. 19 b.

Reference numerals:

01-a display module; 02-pixel; 03-an epitaxial wafer; 04-detection equipment; 05-an intelligent terminal; 06-a processor; 10-a substrate; 101-sub-pixels; 11-an LED chip; 100-a substrate; 110-main epitaxial layer; 111-a first semiconductor layer; 112-a second semiconductor layer; 113-a first light emitting layer; 114-a semiconductor nucleation layer; 115-undoped semiconductor layer; 116-a low doped semiconductor layer; 117-growing a superlattice layer; 118-an electron blocking layer; 119-an ohmic contact layer; 120-distributed bragg reflector layer; 121-a first electrode; 1210-grooves; 1211-first part; 1212-a second portion; 1213-third part; 122-a second electrode; 20-photoresist; 21-mask plate; 22-a metal layer; 201-a first functional layer; 202-a second functional layer; 30-building an area; 31-cutting a channel; 300-a chip wafer; 40-an antenna structure; 400-a conductive coil; 401 — first subsection; 402-a second subsection; 411-a base; 412-a radio frequency signal generator; 413-an optical detector; 420-sub-epitaxial layer; 421-a first auxiliary electrode; 422-a second auxiliary electrode; 432-a conductive line; 441-a first metal line; 442-a second metal line; 443-a third metal line; 50-a first passivation layer; 51-a second passivation layer; 60-a master device; 61-a sub-device; 611 — a third semiconductor layer; 612-a fourth semiconductor layer; 613-second luminescent layer; 614-fifth semiconductor layer.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.

In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

Further, in the present application, directional terms such as "upper" and "lower" are defined with respect to a schematically-disposed orientation of components in the drawings, and it is to be understood that these directional terms are relative concepts that are used for descriptive and clarity purposes and that will vary accordingly with respect to the orientation in which the components are disposed in the drawings.

Some embodiments in the present application provide a smart terminal. The intelligent terminal can be a mobile phone, a tablet computer, a notebook computer, a Personal Digital Assistant (PDA), a vehicle-mounted computer and the like. The embodiment of the present application does not specially limit the specific form of the intelligent terminal.

As shown in fig. 1a, the intelligent terminal 05 includes a processor 06 and a display module 01. The processor 06 is configured to control the display module 01 to display an image.

The display module 01 in the intelligent terminal 05, as shown in fig. 1b, includes a substrate 10 and a plurality of LED chips 11 arranged in a matrix on the substrate 10. Each LED chip 11 is a sub pixel 101.

Adjacent at least three sub-pixels 101 emitting light of different colors, for example, a sub-pixel 101 for emitting red (R) light, a sub-pixel 101 for emitting green (G) light, and a sub-pixel 101 for emitting blue (B) light, constitute a pixel (pixel)02 capable of emitting white light.

It should be noted that, in the embodiment of the present application, the LED chip 11 may be a micro LED chip.

As shown in fig. 2, the LED chip 11 includes a substrate 100 (e.g., sapphire), a master device 60 on the substrate 100. Master device 60 includes a master epitaxial layer 110, a first electrode 121, and a second electrode 122.

Further, as shown in fig. 2, the main epitaxial layer 110 includes a first semiconductor layer 111 and a first functional layer 201 covering a partial region of an upper surface of the first semiconductor layer 111. The first functional layer 201 includes a second semiconductor layer 112 and a first light emitting layer 113. The first light emitting layer 113 is located between the first semiconductor layer 111 and the second semiconductor layer 112.

In this case, the first semiconductor layer 111 may be an N-type semiconductor layer. Illustratively, the N-type semiconductor layer may be formed by doping a pentavalent element, such as phosphorus, in a pure semiconductor material, such as gallium nitride (GaN). In the N-type semiconductor layer, free electrons are majority electrons, and holes are minority electrons, and the conduction is mainly realized by the free electrons. The higher the concentration of majority electrons (free electrons), the stronger the conductivity of the N-type semiconductor layer.

The second semiconductor layer 112 may be a P-type semiconductor layer. Illustratively, the P-type semiconductor layer may be formed by doping a pure semiconductor material, such as gallium nitride (GaN), with a trivalent element, such as boron. In the P-type semiconductor layer, the holes are majority electrons, and the free electrons are minority electrons, and mainly conduct electricity by the holes. The higher the concentration of majority (holes), the stronger the conductivity of the P-type semiconductor layer.

Based on this, the first electrode 121 is disposed on the upper surface of the first semiconductor layer 111 and is located in an area of the upper surface of the first semiconductor layer 111 not covered by the first functional layer 201, where the area is used to enable the first electrode 121 to be coupled with the first semiconductor layer 111.

In the case where the first semiconductor layer 111 is an N-type semiconductor layer, the first electrode 121 coupled to the first semiconductor layer 111 is an N-electrode.

In addition, the second electrode 122 is disposed on the upper surface of the second semiconductor layer 112 and coupled to the second semiconductor layer 112.

In the case where the second semiconductor layer 112 is a P-type semiconductor layer, the second electrode 122 coupled to the second semiconductor layer 112 is a P-electrode.

It should be noted that "coupled" in this application means that two elements may be electrically connected directly or through intervening elements.

Accordingly, a PN junction is formed between the first semiconductor layer 111 and the second semiconductor layer 112. The first light emitting layer 113 is a multiple quantum well layer. Since the first light emitting layer 113 is disposed between the first semiconductor layer 111 and the second semiconductor layer 112, the first light emitting layer 113 is located in the active region of the PN junction.

In addition, the LED chip 11 may be flip-chip mounted on the substrate 10 by using a flip-chip (flip-chip) process, as shown in fig. 3. The substrate 10 may be a rigid Printed Circuit Board (PCB), a Flexible Printed Circuit Board (FPCB), or a silicon substrate. A driving circuit (not shown in the figure) for driving each LED chip 11 to emit light is provided on the substrate 10.

When the driving circuits on the substrate 10 in the display module 01 respectively provide voltages to the first electrode 121 and the second electrode 122 in each LED chip 11, under the action of the applied electric field, electrons in the first semiconductor layer 111 (i.e., N-type semiconductor) and holes in the second semiconductor layer 112 (i.e., P-type semiconductor) are recombined in the first light-emitting layer 113 and emit energy in the form of photons, so that the main device 60 in the LED chip 11 emits light, and the purpose of driving the display module 01 to display images is achieved.

The embodiment of the application provides a method for manufacturing an LED chip 11, as shown in fig. 4, the method includes S101 to S104.

S101, the above-mentioned master device 60 is fabricated in each of the build-up areas 30 on the substrate 100.

The substrate 100, as shown in fig. 5, includes a plurality of building areas 30 defined by crosswise streets 31.

The method of manufacturing the substrate 100 includes preparing sapphire (aluminum oxide (Al) using a crystal growth process₂O₃) ) a crystal column. The crystal pillar is then sliced and polished to obtain the substrate 100. Illustratively, the thickness of the substrate 100 may be about 2 Inch.

In addition, the main epitaxial layer 110 of the main device 60 includes, in addition to the first semiconductor layer 111, the second semiconductor layer 112 and the first light emitting layer 113, a semiconductor nucleation layer 114, an undoped semiconductor layer 115, a low-doped semiconductor layer 116, a superlattice layer 117, an electron blocking layer 118, an ohmic contact layer 119 and a Distributed Bragg Reflector (DBR) layer 120 as shown in fig. 6 a.

Based on this, the method for manufacturing the master device 60 includes: first, a semiconductor (e.g., GaN) nucleation layer 114 is grown on the upper surface of the substrate 100 as shown in fig. 6 a. The thickness of the semiconductor nucleation layer 114 may be about 25 nm. The semiconductor nucleation layer 114 acts as a buffer layer for adaptation between the substrate 100 and the film layers above the GaN nucleation layer 114.

Next, on the upper surface of the semiconductor nucleation layer 114, an undoped semiconductor (e.g., GaN) layer 115 is grown. The thickness of the undoped semiconductor layer 115 may be about 1 um. The undoped semiconductor layer 115 is used to increase the thickness of the entire main epitaxial layer 110 to a thickness that meets design requirements.

Next, the first semiconductor layer 111, i.e., an N-type semiconductor layer, is grown on the upper surface of the undoped semiconductor layer 115. The thickness of the first semiconductor layer 111 may be 2um, and the doping concentration may be 5E18/cm³. The first semiconductor layer 111 is used to supply electrons.

Next, on the upper surface of the first semiconductor layer 111, a low-doped semiconductor (e.g., GaN) layer 116 is grown. The thickness of the lowly doped semiconductor layer 116 may be 300nm with a doping concentration of 5E17/cm³. The low-doped semiconductor layer 116 serves to improve the withstand voltage capability of the LED chip 11.

Next, on the upper surface of the low-doped semiconductor layer 116, a superlattice layer 117 is grown. The superlattice layer 117 is most predominantly composed of periodic GaN and indium gallium nitride (InGaN), and may have a thickness of 2.5nm/5 nm. The superlattice layer 117 serves to improve the light emission efficiency of the first light-emitting layer 113.

Next, on the upper surface of the superlattice layer 117, a multiple quantum well layer of about 12 periods is grown as the first light emitting layer 113. The quantum well layer consists essentially of InGaN and GaN and may be 3nm to 7nm thick. Here, the proportion of the element In the first light-emitting layer 113 can be adjusted so that the first light-emitting layer 113 can emit light of different colors, for example, light with a wavelength of 450nm (i.e., blue light).

Next, on the upper surface of the first light emitting layer 113, an electron blocking layer 118 is grown. The electron blocking layer 118 may be formed of gallium aluminum nitride (AlGaN) and may have a thickness of 70 nm. The electron blocking layer 118 is used to block electrons that overflow, and improve the light emission efficiency of the first light-emitting layer 113.

Next, on the upper surface of the electron blocking layer 118, a second semiconductor layer 112, i.e., a P-type semiconductor layer, is grown. The second semiconductor layer 112 may have a thickness of 150nm and a doping concentration of 1E20/cm³. The second semiconductor layer 112 serves to provide holes.

Next, on the upper surface of the second semiconductor layer 112, an ohmic contact layer 119 is grown. The ohmic contact layer 119 may be N-doped InGaN with a doping concentration of 1E20/cm³The thickness may be 1.5 nm. The ohmic contact layer 119 serves to improve the contact property of the second electrode 122 with the second semiconductor layer 112.

In the case where the LED chip 11 is flip-chip mounted on the substrate 10 as shown in fig. 3, a dbr 120 is grown on the upper surface of the ohmic contact layer 119 as shown in fig. 6a in order to improve the light extraction efficiency of the LED chip 11. The distributed bragg reflector 120 is capable of reflecting light emitted from the first light emitting layer 113 so that more light is emitted from the substrate 100 side.

As can be seen from the above, the first electrode 121 needs to be coupled to the first semiconductor layer 111, and therefore, after the layers in the main epitaxial layer 110 are fabricated, a portion of the first functional layer 201 on the first semiconductor layer 111 is removed, as shown in fig. 6a, so that the upper surface of the first semiconductor layer 111 has an area not covered by the first functional layer 201, and the area is used for coupling with the first electrode 121.

When the structure of the main device 60 is as shown in fig. 6a, the first functional layer 201 further includes a low-doped semiconductor layer 116, a superlattice layer 117, an electron blocking layer 118, an ohmic contact layer 119, and a distributed bragg reflector layer 120.

In addition, when the main epitaxial layer 110 further includes the distributed bragg reflector layer 120 located above the ohmic contact layer 119, as shown in fig. 6b, a portion of the distributed bragg reflector layer 120 needs to be removed to expose a portion of the ohmic contact layer 119 for contacting the second electrode 122, so as to couple the second electrode 122 to the second semiconductor layer 112.

After the above steps are performed, the preparation of the epitaxial wafer can be completed. As can be seen from the above, when the proportion of the element In the first light-emitting layer 113 is adjusted, the first light-emitting layer 113 can emit light rays with different colors. The first light-emitting layer 113 of an epitaxial wafer is a continuous, integral layer that is laid on the substrate 100, so that an epitaxial wafer can generally emit light of only one color.

In this case, in order to prepare the LED chip 11 capable of emitting R light, G light, and B light, respectively, as shown in fig. 7, an epitaxial wafer 03_ a for emitting R light, an epitaxial wafer 03_ B for emitting G light, and an epitaxial wafer 03_ c for emitting B light can be prepared.

Next, the first electrode 121 and the second electrode 122 are fabricated in the respective build-up areas 30 on the epitaxial wafer.

Specifically, as shown in fig. 8a, a photoresist 20 is coated on the upper surface, i.e., the epitaxial surface, of the main epitaxial layer 110. The photoresist 20 is taken as a positive photoresist as an example.

Then, as shown in fig. 8b, a region other than the positions where the first electrode 121 and the second electrode 122 are arranged is irradiated with light on the epitaxial wafer using the mask 21, and is solidified. The first electrode 121 and the second electrode 122 are not irradiated by light and are not solidified (shaded portions of the photoresist 20 in the figure) under the shielding effect of the light shielding portions on the mask.

Next, as shown in fig. 8c, the uncured photoresist is washed away with a developing solution to expose a portion of the epitaxial surface of the main epitaxial layer 110.

For example, a partial region of the upper surface of the first semiconductor layer 111 in the main epitaxial layer 110 is exposed for coupling with the first electrode 121, and a partial region of the upper surface of the ohmic contact layer 119 in the main epitaxial layer 110 is exposed for coupling with the second electrode 122.

Next, a metal layer 22 is vapor-deposited on the epitaxial surface of the main epitaxial layer 110 using an electron beam as shown in fig. 8d, and may have a thickness of 1.5 μm, for example.

Next, the remaining photoresist 20 is removed using a photoresist removing liquid, so that the metal layer 22 above the photoresist is also removed. In this case, as shown in fig. 8e, the metal layer remaining at the position of the second electrode 122 is preset as the second electrode 122, and the metal layer remaining at the position of the first electrode 121 is preset as a part of the first electrode 121.

In addition, in order to make the upper surfaces of the first electrode 121 and the second electrode 122 substantially flush as shown in fig. 8f, the above steps of coating photoresist, masking the photoresist, exposing, developing, evaporating the metal layer, and removing the photoresist may be adopted again, and the thickness of the remaining metal layer is increased at the position where the first electrode 121 is preset to form the first electrode 121 as shown in fig. 8 f.

For example, in order to improve the contact performance of the first electrode 121 and the second electrode 122 with the main epitaxial layer 110, as shown in fig. 8g, when the first electrode 121 is an N electrode, the first electrode 121 includes two metal layers (B1 and C1).

Wherein, the material of the metal layer B1 in contact with the first semiconductor layer 111 in the main epitaxial layer 110 may be titanium (Ti); the metal layer C1 facing away from the first semiconductor layer 111 is gold (Au).

When the second electrode 122 is a P-electrode, the second electrode 122 may include two metal layers (B2 and C2).

Wherein the material of the metal layer B2 coupled to the second semiconductor layer 112 in the main epitaxial layer 110 is aluminum (Al); the metal layer C2 facing away from the second semiconductor layer 112 is gold (Au).

The above description is made by taking the photoresist 20 as a positive resist. When the negative resist is used as the resist 20, the portion not irradiated with light is solidified and is not dissolved in a developer. The portion irradiated with the light is not solidified and dissolved in the developing solution. The rest steps are the same as above, and are not described herein again.

After the above S101 is performed, a structure is formed in which a plurality of master devices 60 are arranged in a matrix form and the master epitaxial layers 110 of the respective master devices 60 are connected as shown in fig. 8 h.

S102, a plurality of antenna structures 40 as shown in fig. 9 are fabricated.

As shown in fig. 9, a plurality of antenna structures 40 are in one-to-one correspondence with a plurality of build areas 30. Each antenna structure 40 is coupled to its corresponding first electrode 121 and second electrode 122 in the build area 30 to form a chip wafer 300.

The antenna structure 40 is used to receive the RF signal and to generate a potential difference between the first electrode 121 and the second electrode 122 within the same build area 30 before the chip wafer 300 is diced to separate the LED chips 11.

When the antenna structure 40 receives a received Radio Frequency (RF) signal, the antenna structure 40 may induce an electromotive force between the first electrode 121 and the second electrode 122 coupled to the antenna structure 40 in the building region 30 corresponding to the antenna structure 40. The electromotive force may cause a potential difference between the first electrode 121 and the second electrode 122, and thus an electric field is formed between the first electrode 121 and the second electrode 122.

The electric field can cause electrons in the first semiconductor layer 111 (i.e., N-type semiconductor) and holes in the second semiconductor layer 112 (i.e., P-type semiconductor) in the building region 30 corresponding to the antenna structure 40 to recombine in the first light-emitting layer 113 and emit energy in the form of photons, thereby causing the main device 60 in the building region 30 to emit light.

S103, performing PL test on the chip wafer 300.

Sending RF signals to the plurality of antenna structures 40 shown in fig. 9, collecting the light emitting luminance of each master device 60 in the chip wafer 300, and testing whether each master device 60 can normally operate according to the light emitting luminance of each master device 60.

In this way, each master device 60 in the chip wafer 300 may be detected by the PL detection method provided in S103, and whether it fails (KGD) may be determined. Thus, the problem that a large number of LED chips 11 cannot be detected can be solved.

And S104, separating the chip wafer 300 along the cutting channels to obtain a plurality of LED chips 11.

In this case, as shown in fig. 10, a plurality of LED chips 11_ a for emitting R light can be obtained by separating the chip wafer 300_ a for emitting R light.

The chip wafer 300_ b for emitting G light is separated, and a plurality of LED chips 11_ b for emitting G light can be obtained.

By separating the chip wafer 300_ B for B light emission, a plurality of LED chips 11_ c for B light emission can be obtained.

Next, the LED chips 11_ a, 11_ b, and 11_ c are transferred in batch, and are inversely mounted on the substrate 10 in a certain pixel arrangement manner, thereby forming the display module 01 shown in fig. 10.

As can be seen from the above description, when receiving an RF signal, the antenna structure 40 can generate a potential difference between the first electrode 121 and the second electrode 122 coupled to the antenna structure 40, so as to drive the main device 60 in the building area 30 corresponding to the antenna structure 40 to emit light. Wherein, the RF signal is an AC signal.

In addition, after the display module 01 is formed by separating the LED chips 11 formed by the chip wafer 300 and inversely mounting the LED chips 11 on the substrate 10, the first electrode 121 and the second electrode 122 of each LED chip 11 receive a direct current signal and emit light in the display process of the display module 01. Therefore, the direct current signal does not cause the antenna structure 40 to induce an electromotive force in the display process of the display module 01, so that the display of the display module 01 is not affected.

The specific arrangement of the antenna structures 40 in the chip wafer 300 and the structure of the LED chips 11 obtained after the chip wafer 300 is cut will be described in detail below. For convenience of explanation, the following embodiments are all described by taking the length L (as shown in fig. 9) of the building region 30 as 300 μm and the width B as 100 μm as an example. In this case, the specification of any one of the LED chips 11 obtained by separating the chip wafer 300 is approximately 100 μm × 300 μm.

Example 1

In this example, the step S102 of fabricating the antenna structure 40 includes fabricating a plurality of conductive coils 400 insulated from the main epitaxial layer 110, as shown in fig. 11a, outside the main epitaxial layer 110.

Both ends of each conductive coil 400 are respectively in contact with the first electrode 121 and the second electrode 122 in the same building region 30, and at least one part of each conductive coil 400 is positioned in the cutting path 31 between two adjacent building regions 30.

In some embodiments of the present application, as shown in fig. 11a, the first electrode 121 (or the second electrode 122) may be located within the conductive coil 400. Furthermore, any two turns of conductive coil 400 do not intersect, i.e., there is no overlap area in the orthographic projection of the respective portions of conductive coil 400 onto primary epitaxial layer 110.

For example, in the case that the size of the LED chip 11 is 100 × 300 μm, when the conductive coil 400 is disposed as shown in fig. 11a, the number of turns of the conductive coil 400 may be 8.

As shown in fig. 11a, the length S11 of the outermost circle is 250 μm; the width S12 of the outermost circle is 120 μm; the length of the innermost circle S21 is 80 μm; the width S22 of the innermost circle is 70 μm.

The line width M of the conductive coil 400 is 2 μ M. As shown in fig. 11b (cross-sectional view taken along O1-O1 in fig. 11 a), conductive coil 400 has a thickness N of 1 μm.

It should be noted that the above is merely illustrative of the number of turns of the conductive coil 400 and the size of the innermost or outermost turn. The size of each circle in the conductive coil 400 is not limited in the present application, as long as it can be ensured that before the chip wafer 300 is cut to separate the LED chips 11, the conductive coil 400 can induce an electromotive force after receiving the RF signal, so that a potential difference is generated between the first electrode 121 and the second electrode 122 directly connected to two ends of the conductive coil 400, so as to drive the main device 60 in the building area 10 corresponding to the conductive coil 400 to emit light.

In addition, when the conductive coil 400 is disposed as shown in fig. 11a, in order to insulate the conductive coil 400 from the main epitaxial layer 110, the chip wafer 300 further includes a first passivation layer 50 as shown in fig. 11 b.

The upper surface of the first passivation layer 50 is in contact with the lower surface of the conductive coil 400, and the lower surface of the first passivation layer 50 is in contact with the upper surface of the main epitaxial layer 110. At this time, each portion of the conductive coil 400 is disposed on the upper surface of the first passivation layer 50. As such, the conductive coil 400 may be isolated from the main epitaxial layer 110 by the first passivation layer 50.

The material of the first passivation layer 50 may be a resin material having insulating properties.

In this example, after the wire coil 400 is fabricated in S102, a PL test of the chip wafer 300 may be performed in S103.

As shown in fig. 12, the inspection apparatus 04 for testing the chip wafer 300 includes a base 411, an rf signal generator 412, and an optical detector 413.

The base 411 is used for carrying the chip wafer 300 with the wire coil 400.

The rf signal generator 412 may be disposed on the base 411. For example, the distance between the chip wafer 300 and the pedestal 411 may be about 1 cm.

The RF signal generator 412 is used to send RF signals to the antenna structures 40 on the chip wafer 300, i.e., the wire coil 400. Illustratively, the RF signal may have a frequency of 20MHz and a transmit power of 10W. The receiving power of the chip wafer 300 may be 100 mW.

In this case, the wire coil 400 may serve as an inductance layer, and after receiving the RF signal, an electromotive force may be induced, so that a potential difference may be generated between the first electrode 121 and the second electrode 122, which are respectively in contact with both ends of the wire coil 400, in the building region 30 corresponding to the wire coil 400.

At this time, under the effect of the electric field generated by the first and

second electrodes

121 and 122, electrons in the first semiconductor layer 111 (i.e., N-type semiconductor) of the main device 60 and holes in the second semiconductor layer 112 (i.e., P-type semiconductor) are recombined in the first light emitting layer 113 and emit energy in the form of photons, so that the main device 60 emits light.

Based on this, the optical signal detector 413, such as an integrating sphere, may be disposed on a side of the chip wafer 300 away from the pedestal 411, i.e., an upper surface of the chip wafer 300. After each main device 60 in the chip wafer 300 emits light, the optical signal detector 413 can collect the light emitting brightness of each main device 60 building area 30 in the chip wafer 300, and judge whether the main device 60 emits light normally according to the light emitting brightness of the main device 60.

The collection result of the optical signal detector 413 can be shown in fig. 13. As can be seen from fig. 13, according to the acquisition result of the optical signal detector 413, the position of the master device 60 that does not normally emit light, that is, the position of the dead pixel (indicated by a black square in the drawing) can be acquired. In this way, after the chip wafer 300 is separated to obtain the LED chips 11, the LED chips 11 at the dead center positions can be skipped to avoid being flipped over on the substrate 10 in the process of transferring the plurality of LED chips 11 in batch. Alternatively, the positions of the dead points may be maintained.

In addition, when the chip wafer 300 finishes the PL test, S104 is executed to separate the chip wafer 300 to obtain a plurality of LED chips 11.

As can be seen from the above, the main epitaxial layers 110 in each main device 60 on the same chip wafer 300 are connected together. Therefore, before separating the chip wafer 300, as shown in fig. 14a (the cross-sectional view taken along D-D in fig. 11 a), the film layers, such as the first passivation layer 50 and the second passivation layer 51, and the main epitaxial layer 110, located in the scribe line 31 between two adjacent building regions 30 need to be removed.

For example, an Inductively Coupled Plasma (ICP) process may be used to etch the film layer in the scribe line 31, and the structure of the etched chip wafer 300 is shown in fig. 14 b. Fig. 14b shows that the film between two adjacent building regions 30 is broken.

Next, at the dicing streets 31, the substrate 100 is subjected to dicing separation, thereby obtaining a plurality of LED chips 11.

As can be seen from the above, in this example, a part of the conductive coil 400 is located in the scribe line 31 between two adjacent building regions 30, so that after the chip wafer 300 is separated, the part of the conductive coil 400 located in the scribe line 31 is removed, and the conductive coil 400 is disconnected at the position of the scribe line 31. The remainder of conductive coil 400 is located outside of main epitaxial layer 110 of main device 60.

Thus, after S104 is executed, any one of the separated independent LED chips 11 has the remaining portion of the antenna structure 40 (i.e., the conductive coil 400). The remaining portion of the antenna structure 40 is shown in fig. 11c, and includes a first metal 441, a second metal 442, and at least one third metal 443.

The first metal line 441, the second metal line 442, and the third metal line 443 are used as a structure of the conductive coil 400 remaining in the LED chip 11, and the first metal line 441, the second metal line 442, and the third metal line 443 are insulated from each other. So that the electrical connection between the first electrode 121 and the second electrode 122 in the LED chip 11 is interrupted when the LED chip 11 normally operates to receive a direct current signal. Further, when the LED chip 11 works normally, the antenna structure 40 will not affect the normal light emission of the LED chip 11.

One end of the first metal line 441 is in contact with the first electrode 121, and the other end is flush with one edge of the LED chip 11. One end of the second metal line 442 contacts the second electrode 122, and the other end is flush with one edge of the LED chip 11.

A portion of the third metal line 443 is located between the first metal line 441 and the second metal line 442. As shown in fig. 11c, both ends of the third metal line 443 are flush with two different edges of the LED chip 11, respectively. Alternatively, as shown in fig. 11d, both ends of the third metal line 443 are flush with the same edge of the LED chip 11.

Note that, the fact that one end of the first metal line 441, the second metal line 442, or the third metal line 443 is flush with the edge of the LED chip 11 means that after the chip wafer 300 shown in fig. 11a is diced, the side surface of the separated LED chip 11 and the end surface of one end of the first metal line 441, the second metal line 442, or the third metal line 443 are located in the same plane.

Since any two turns of each conductive coil 400 do not intersect in the chip wafer 300 shown in fig. 11a, that is, the orthographic projections of the parts of the conductive coils 400 on the main epitaxial layer 110 do not have an overlapping region, after the chip wafer 300 shown in fig. 11a is cut, the separated LED chip 11 is shown in fig. 11c, and the orthographic projections of the first metal line 441, the second metal line 442 and the third metal line 443 on the main epitaxial layer 110 do not have an overlapping region.

In addition, the first electrode 121 is located in an area enclosed by the third metal line 443 and the edge of the LED chip 11 where two ends of the third metal line 443 are flush.

On this basis, when the antenna structure 40 includes a plurality of third metal lines 443 as shown in fig. 11e, two adjacent third metal lines 443 are spaced apart from each other.

Alternatively, in other embodiments of the present application, as shown in fig. 15a, the conductive coil 400 fabricated when the above-described S102 is performed may be located between the first electrode 121 and the second electrode 122.

Conductive coil 400 includes a first subsection 401 and a second subsection 402 connected. The orthographic projection of the first sub-portion 401 on the main epitaxial layer 110 has an overlapping area with the orthographic projection of the second sub-portion 402 on the main epitaxial layer 110.

At this time, the first sub-section 401 and the second sub-section 402 of the wire coil 400 are arranged to intersect and be insulated.

In this case, in order to isolate the conductive coil 400 from the main epitaxial layer 110, as shown in fig. 15b (a cross-sectional view taken along Q1-Q1 in fig. 15 a), the chip wafer 300 further includes a first passivation layer 50 and a second passivation layer 51.

Wherein the first passivation layer 50 is located between the first sub-portion 401 of the conductive coil 400 and the main epitaxial layer 110. The second passivation layer 51 is located between the second sub-portion 402 of the conductive coil 400 and the first sub-portion 401 of the conductive coil 400.

The first passivation layer 50 and the second passivation layer 51 may be made of the same material, for example, the resin material having the insulating property.

As such, the first sub-portion 401 of the conductive coil 400 may be isolated from the main epitaxial layer 110 by the first passivation layer 50. The first subsection 401 and the second subsection 402, which are arranged crosswise, may be separated by the second passivation layer 51.

The PL testing method of the chip wafer 300 having the conductive coil 400 is the same as described above, and is not described herein again.

In this case, after the PL test is performed on the chip wafer 300, S104 is performed to separate the chip wafer 300 shown in fig. 15a along the scribe lines 31, the portion of the conductive coil 400 located on the scribe lines 31 is cut off, and the conductive coil 400 is disconnected at the positions of the scribe lines 31. In addition, the portion of conductive coil 400 that is in build area 30 remains.

Thus, after S104 is executed, the remaining portion of the antenna structure 40 in the separated independent LED chip 11 includes the first metal 441, the second metal line 442, and at least one third metal line 443 as shown in fig. 15 c.

As described above, one end of the first metal line 441 is in contact with the first electrode 121, and the other end is flush with one edge of the LED chip 11. One end of the second metal line 442 contacts the second electrode 122, and the other end is flush with one edge of the LED chip 11. A portion of the third metal line 443 is located between the first metal line 441 and the second metal line 442. Both ends of the third metal line 443 are flush with two different edges of the LED chip 11, respectively. Or both ends of the third metal line 443 are flush with the same edge of the LED chip 11.

In addition, the third metal line 443 is located between the first electrode 121 and the second electrode 122. The first metal line 441 and the at least one third metal line 443 have an overlapping area in an orthogonal projection on the main epitaxial layer 110.

The portion of the first metal line 441 overlapped with the third metal line 443 may be the second sub-portion 402 of the conductive coil 400 in fig. 15 a. And the third metal line 443 and the second metal line 442 may be part of the first sub-portion 401 of the conductive coil 400 in fig. 15 a. As can be seen in fig. 15b, an insulating second passivation layer 51 is disposed between the first sub-portion 401 and the second sub-portion 402 of the conductive coil 400. It is possible to insulate a portion of the first metal line 441 that overlaps the third metal line 443.

Example two

In this example, the fabrication of the antenna structure 40 in S102 includes fabricating a plurality of conductive coils 400 outside the main epitaxial layer 110, as shown in fig. 16a, each conductive coil 400 being located in one of the building regions 30.

In this example, the two ends of each conductive coil 400 are referred to as a first end and a second end. Wherein a first end of conductive coil 400 faces first electrode 121 and a second end of conductive coil 400 faces second electrode 122.

In this case, in order to couple the first end of the conductive coil 400 to the first electrode 121 and the second end to the second electrode 122, a capacitance is formed between the first end of each conductive coil 400 and the first electrode 121, and the second end is in contact with the second electrode 122.

Alternatively, a capacitance is formed between the first end of each conductive coil 400 and the first electrode 121, and a capacitance is formed between the second end of each conductive coil 400 and the second electrode 122.

In this case, when S104 is performed, the chip wafer 300 shown in fig. 16a is separated, and then the structure of any one of the LED chips 11 is obtained as shown in fig. 16 b. It can be seen that the LED chip 11 includes a complete conductive coil 400 as described above. In the LED chip 11, the manner of coupling the two ends of the conductive coil 400 with the first electrode 121 and the second electrode 122 in the LED chip 11 is the same as that described above, and details are not repeated here.

Based on this, in some embodiments of the present application, after the chip wafer 300 shown in fig. 16a is separated, the arrangement of the conductive coil 400 in the LED chip 11 is shown in fig. 16b, and the first electrode 121 (or the second electrode 122) may be located in the conductive coil 400. Furthermore, the orthographic projections of the various portions of conductive coil 400 on main epitaxial layer 110 have no overlap areas.

For example, in the case where the LED chip 11 has a size of 100 × 300 μm, when the conductive coil 400 is sized as shown in fig. 16b, the number of turns of the conductive coil 400 may be 6. The length of the outermost circle S11 ═ 250 μm; the width S12 of the outermost circle is 80 μm; the length of the innermost circle S21 is 80 μm; the width S22 of the innermost circle is 70 μm.

The line width M of the conductive coil 400 is 2 μ M. As shown in fig. 16c (cross-sectional view taken along O2-O2 in fig. 16 b), conductive coil 400 has a thickness N of 1 μm.

In the case that a capacitance is formed between the first end of each conductive coil 400 and the first electrode 121, and the second end of each conductive coil 400 is in contact with the second electrode 122, as shown in fig. 16c, a gap H exists between the first end of the conductive coil 400 facing the first electrode 121 and the first electrode 121, and an orthographic projection of the conductive coil 400 on the main epitaxial layer 110 has no overlapping area with an orthographic projection of the first electrode 121 on the main epitaxial layer 110.

As such, a second passivation layer 51 having an insulating property may be filled between the first end of the conductive coil 400 facing the first electrode 121 and the first electrode 121, so that a capacitance may be formed between the first end of the conductive coil 400 facing the first electrode 121 and the first electrode 121.

This capacitance has the effect of turning on the ac current and blocking the dc current so that coupling of the first end of conductive coil 400 to first electrode 121 is achieved after RF signal is received by conductive coil 400.

In addition, a second end of the conductive coil 400 is in contact with the second electrode 122. In this case, when the conductive coil 400 receives the RF signal, the conductive coil 400 may induce an electromotive force as an inductance layer, and generate a potential difference between the first electrode 121 and the second electrode 122 coupled to both ends thereof for driving the LED chip 11 having the conductive coil 400 to emit light.

Alternatively, in order to form a capacitance between the first end of the conductive coil 400 and the first electrode 121, in other embodiments of the present application, the fabricating the first electrode in performing S101 includes fabricating the first electrode 121 on the upper surface of the first semiconductor layer 111 of the main epitaxial layer 110, and forming a groove 1210 on a side of the first electrode 121 close to the conductive coil 400, as shown in fig. 16 d.

In this application, the method for manufacturing the first electrode 121 having the groove 1210 may be to respectively manufacture the first portion 1211, the second portion 1212, and the third portion 1213 of the first electrode 121, which are shown in fig. 16d, three times by using the processes of applying the adhesive, masking, exposing, developing, and evaporating the metal layer, so as to form the first electrode 121 having the groove 1210. The specific manufacturing method is the same as the manufacturing method of the electrode provided in S101, and is not described herein again.

Next, the antenna structure 40 manufactured in step S102, that is, the conductive coil 400 includes, as shown in fig. 16d, a first end of the conductive coil 400 extends into the groove 1210, and a gap H is formed between the first end of the conductive coil 400 and an inner wall of the groove 1210, so as to form a capacitance between the first end of the conductive coil 400 and the inner wall of the groove 1210. Such that a first end of the conductive coil 400 is coupled to the first electrode 121.

It should be noted that, the above description is made by taking an example that a capacitance is formed between the first end of the conductive coil 400 facing the first electrode 121 and the first electrode 121, and the second end is in contact with the second electrode 122. In other embodiments of the present application, as shown in fig. 16e, a first end of conductive coil 400 may be in contact with first electrode 121 and a second end forms a capacitance with second electrode 122. And the second end of the conductive coil 400 forms a capacitor with the second electrode 122 in the same manner as described above, and will not be described herein again.

Alternatively, in some embodiments of the present application, in order to form a capacitance between the first end of the conductive coil 400 and the first electrode 121 and a capacitance between the second end and the second electrode 122, as shown in fig. 16f, a groove may be formed on a side of the first electrode 121 facing the first end of the conductive coil 400 and a groove may be formed on a side of the second electrode 122 facing the second end of the conductive coil. Such that a first end of the conductive coil 400 extends into the recess of the first electrode 121 and a second end extends into the recess of the second electrode 122. The arrangement of the grooves is the same as that described above, and is not described herein again.

In this case, in order to make the conductive coil 400 be disposed to be insulated from the main epitaxial layer 110, the LED chip 11 further includes a first passivation layer 50 between the conductive coil 400 and the main epitaxial layer 110 as shown in fig. 16f, in the same manner as in the first example.

The above describes the arrangement of the conductive coil 400 in the LED chip 11 by taking the orthographic projection of each part of the conductive coil 400 on the main epitaxial layer 110 as an example.

In addition, in other embodiments of the present application, the conductive coil 400 is disposed as shown in fig. 17a, and the conductive coil 400 may be located between the first electrode 121 and the second electrode 122.

In addition, the conductive coil 400 includes a first sub-portion 401 and a second sub-portion 402 connected. The orthographic projection of the first sub-portion 401 on the main epitaxial layer 110 has an overlapping area with the orthographic projection of the second sub-portion 402 on the main epitaxial layer 110.

In this case, in order to insulate the conductive coil 400 from the main epitaxial layer 110, as shown in fig. 17b (a cross-sectional view taken along Q2-Q2 in fig. 17 a), the LED chip 11 further includes a first passivation layer 50 between the first sub-portion 401 and the epitaxial surface of the main epitaxial layer 110, and a second passivation layer 51 partially between the first sub-portion 401 and the second sub-portion 402, as well as the same example.

When the conductive coil 400 shown in fig. 17a is used, the manner of forming a capacitance between one end of the conductive coil 400 and the first electrode 121 or the second electrode 122 is the same as described above, and details thereof are omitted here.

As can be seen from the above, in this example, the LED chip 11 has the complete conductive coil 400, that is, each conductive coil 400 is fabricated to be located in one of the building regions 30 on the substrate 100 when S102 is performed. In this way, for the chip wafer 300 obtained after performing S102, the film layer at the position of the scribe line 31 may be removed first as shown in fig. 14b, so that the main epitaxial layers 110 in the respective building regions 30 are spaced apart. The manner of removing the film layer at the position of the scribe line 31 is the same as that described above, and is not described herein again.

Then, the chip wafer 300 is subjected to PL test. For example, as shown in fig. 18, the distance between the rf signal generator 412 and the chip wafer 300 may be about 0.5 cm. The RF signal generated by the RF signal generator 412 may have a frequency of 2GHz and a transmission power of 5W. The receiving power of the chip wafer 300 may be 300 mW.

Finally, S104 is performed to cut the substrate 100 of the chip wafer 300, and separate the LED chips 11 shown in fig. 16a or fig. 17 a.

In this way, by disposing the PL test link for the chip wafer 300 after the step of separating the main epitaxial layer 110, the sequence of the PL test link for the chip wafer 300 is further advanced in the entire manufacturing process of the LED chip 11. In this case, the PL test result is closer to the actual usage environment of the LED chip 11, i.e., the environment when the LED chip 11 is disposed in the display module 01 and normally operates. Therefore, the accuracy of the PL test can be improved, and the purpose of improving the product quality is achieved.

Example three

In this example, the fabrication of the antenna structure 40 in S102 described above includes forming sub-devices 61 in the build-up area 30, as shown in fig. 19 a. In addition, outside the main epitaxial layer 110, a plurality of conductive coils 400 and a plurality of conductive wires 432 are fabricated, one conductive coil 400 and one conductive wire 432 in each build region 30.

In this case, when S104 is performed, the chip wafer 300 shown in fig. 19a is separated, and then the structure of any one of the LED chips 11 is obtained as shown in fig. 19 b. The antenna structure 40 of the LED chip 11 comprises a sub-device 61 as shown in fig. 19b, a wire 432 outside the main epitaxial layer 110 and a conductive coil 400.

Like the second example, the conductive coil 400 in the LED chip 11 may not be overlapped at any position, or at least two parts of the conductive coil 400 are crossed and insulated, which is not described herein again.

As in example two, first electrode 121 or second electrode 122 may be disposed within conductive coil 400. Alternatively, the conductive coil 400 may be disposed between the first electrode 121 and the second electrode 122, which is not described in detail herein.

For example, in the case that the LED chip 11 has a size of 100 × 300 μm, when the conductive coil 400 is disposed as shown in fig. 19b, the number of turns of the conductive coil 400 may be 5. The length of the outermost circle S11 ═ 150 μm; the width S12 of the outermost circle is 80 μm; the length of the innermost circle S21 is 80 μm; the width S22 of the innermost circle is 50 μm.

The line width M of the conductive coil 400 is 2 μ M. As shown in fig. 19c (cross-sectional view taken along O3-O3 in fig. 19 b), conductive coil 400 has a thickness N of 1 μm.

Further, the sub-device 61 comprises, as shown in fig. 19c (a cross-sectional view cut along O3-O3 in fig. 19 b), a sub-epitaxial layer 420 and a first auxiliary electrode 421 and a second auxiliary electrode 422 provided on the sub-epitaxial layer 420.

The sub-epitaxial layer 420 is disposed insulated from the main epitaxial layer 110 of the main device 60. For example, an etching process may be used to separate the sub-epitaxial layer 420 from the main epitaxial layer 110, and fill the gap with a passivation layer having insulating properties.

The main device 60 is turned on with the second electrode 122 pointing to the first electrode 121. The conducting direction of the sub-device 61 is directed from the second auxiliary electrode 422 to the first auxiliary electrode 421.

In addition, one end of the conductive coil 400 is in contact with the first electrode 121, and the other end is in contact with the second auxiliary electrode 422.

As shown in fig. 19d (a cross-sectional view taken along line Q3-Q3 in fig. 19 b), one end of the wire 432 is in contact with the first auxiliary electrode 421, and the other end is in contact with the second electrode 122.

It should be noted that, in some embodiments of the present application, in order to simplify the manufacturing process, as shown in fig. 19d, the sub-epitaxial layer 420 of the sub-device 61 and the main epitaxial layer 110 of the main device 60 may be located on the same substrate 100. Alternatively, in other embodiments of the present application, the passivation layer for insulation may be formed after the main device 60 is formed, and then the sub-device 61 is formed.

In addition, in order to simplify the manufacturing process and facilitate the optimal arrangement of the layout space in the LED chip, when the cross sections (parallel to the carrying surface of the substrate 100) of the first electrode 121 and the second electrode 122 of the main device 60 and the first auxiliary electrode 421 and the second auxiliary electrode 422 of the sub-device 61 are rectangular, the long side or the short side of the cross section of the electrodes may be parallel to the edge of the LED chip 11. Alternatively, in other embodiments of the present application, the long side or the short side of the electrode may intersect with the edge of the LED chip 11.

In the same LED chip 11, the positional relationship between the sub-device 61 and the main device 60, and the first electrode 121, the second electrode 122, the first auxiliary electrode 421, and the second auxiliary electrode 422 is not limited, as long as the sub-epitaxial layer 420 of the sub-device 61 is insulated from the main epitaxial layer 110 of the main device 60.

The manner in which the sub-epitaxial layer 420 of the sub-device 61 is disposed is illustrated below.

In some embodiments of the present application, as shown in fig. 20a, the sub-epitaxial layer 420 of the sub-device 61 includes a third semiconductor layer 611 and a second functional layer 202 covering a partial region of the upper surface of the third semiconductor layer 611.

The second functional layer 202 includes a fourth semiconductor layer 612 and a second light emitting layer 613. The second light emitting layer 613 is positioned between the third semiconductor layer 611 and the fourth semiconductor layer 612.

In this case, the first auxiliary electrode 421 is disposed on the upper surface of the third semiconductor layer 611 and is coupled to the third semiconductor layer 611.

The second auxiliary electrode 422 is disposed on an upper surface of the fourth semiconductor layer 612 and is coupled to the fourth semiconductor layer 612.

In some embodiments of the present application, the third semiconductor layer 611, the second functional layer 202, and the third semiconductor layer 611 in the sub-epitaxial layer 420 of the sub-device 61 may be the same material as the first semiconductor layer 111, the second light emitting layer 113, and the second semiconductor layer 112 in the main epitaxial layer 110 of the main device 60, respectively.

In addition, in the sub-epitaxial layer 420 of the sub-device 61, in addition to the third semiconductor layer 611, the second functional layer 202, and the third semiconductor layer 611, the arrangement of other film layers may be the same as the structure and position of the corresponding thin film layer in the main epitaxial layer 110 of the main device.

In this case, when the third semiconductor layer 611 is an N-type semiconductor layer and the fourth semiconductor layer 612 is a P-type semiconductor layer in the sub-device 61, the PN junction is provided in the sub-device 6161.

In addition, a material constituting the first auxiliary electrode 421 may be the same as a material constituting the first electrode 121. The material constituting the second auxiliary electrode 422 may be the same as the material constituting the second electrode 122. And will not be described in detail herein.

Alternatively, in other embodiments of the present application, the sub-epitaxial layer 420 of the sub-device 61 is disposed in such a way that, as shown in fig. 20b, the first auxiliary electrode 421 and the second auxiliary electrode 422 are both located on the upper surface of the fifth semiconductor layer 614 and are coupled to the fifth semiconductor layer 614. The fifth semiconductor layer 614 may be an N-type semiconductor layer.

In this case, the first auxiliary electrode 421 is an N-electrode, and the first auxiliary electrode 421 may include two metal layers (B1 and C1). Wherein, the material of the metal layer B1 in contact with the fifth semiconductor layer 614 in the sub-epitaxial layer 420 may be titanium (Ti); the metal layer C1 facing away from the fifth semiconductor layer 614 is gold (Au).

The second auxiliary electrode 422 is a P-electrode, and the second auxiliary electrode 422 may include two metal layers (B2 and C2). Wherein, the material of the metal layer B2 in contact with the fifth semiconductor layer 614 in the sub-epitaxial layer 420 is nickel (Ni); the metal layer C2 facing away from the fifth semiconductor layer 614 is gold (Au).

In this case, in the sub-device 61, the first auxiliary electrode 421(N electrode) forms a schottky junction with the fifth semiconductor layer 614 in the sub-epitaxial layer 420, and the second auxiliary electrode 422(P electrode) forms a schottky junction with the fifth semiconductor layer 614 in the sub-epitaxial layer 420.

When the sub-device 61 adopts the schottky junction arrangement shown in fig. 20b, the number of film layers in the sub-epitaxial layer 420 of the sub-device 61 is small and the structure is simpler than that of the PN junction arrangement shown in fig. 20 a.

Since in this example, after the chip wafer 300 is diced, any one of the LED chips 11 obtained has the complete antenna structure 40 therein, including the above-mentioned sub-device 61, the wire 432 and the conductive coil 400. Therefore, as in the second example, the film layer at the position of the scribe line 31 may be removed from the chip wafer 300 obtained after performing S102, as shown in fig. 14b, so that the main epitaxial layers 110 in the respective build areas 30 are spaced apart. The manner of removing the film layer at the position of the scribe line 31 is the same as that described above, and is not described herein again.

Then, the chip wafer 300 is subjected to a PL test as shown in fig. 18. For example, the distance between the rf signal generator 412 and the chip wafer 300 may be about 2 cm. The RF signal generated by the RF signal generator 412 may have a frequency of 30GHz and a transmission power of 30W. The receiving power of the chip wafer 300 may be 50 mW.

In this case, the first electrode 121 is an N electrode, and the second electrode 122 is a P electrode. When the conductive coil 400 in the antenna structure 40 receives the RF signal, since the conductive direction of the main device 60 is directed from the second electrode 122 to the first electrode 121 as shown in fig. 19b, the main device 60 is not conductive when a positive voltage in the RF signal is applied to the first electrode 121, and thus no potential difference is generated between the first electrode 121 and the second electrode 122.

Further, when a positive voltage (e.g., 10V) in the RF signal as the alternating current signal is applied to the second auxiliary electrode 422 in the sub-device 61, the voltage on the first electrode 121 of the main device 60 may be 0V.

Since the conducting direction of the sub-device 61 is directed from the second auxiliary electrode 422 to the first auxiliary electrode 421, the sub-device 61 is turned on, and the voltage received by the first auxiliary electrode 421 on the sub-device 61 is still positive after a certain voltage drop, for example, 8V.

Since the first auxiliary electrode 421 of the sub-device 61 is electrically connected to the second electrode 122 of the main device through the wire 432, the voltage on the second electrode 122 is a positive voltage, i.e., the above-mentioned 8V, as the first auxiliary electrode 421. In this case, a potential difference is generated between the first electrode 121(0V) and the second electrode 122(8V) of the master device 60, so that the master device can be driven to emit light, enabling PL detection.

After the plurality of LED chips 11 are separated from the chip wafer 300 after PL detection and the LED chips 11 are disposed in the display module 01, when the LED chips 11 need to emit light, a positive voltage is applied to the second electrodes 122 of the LED chips 11 and a negative voltage is applied to the first electrodes 121.

In this case, the LED chip 11 will operate normally. The sub-device 61 in the LED chip 11 is not turned on because the conducting direction of the sub-device is that the second auxiliary electrode 422 points to the first auxiliary electrode 421, and the second auxiliary electrode 422 cannot obtain positive voltage, so that the influence of the sub-device 61 on the light emitting brightness of the LED chip 11 in the display process can be avoided.

In this example, the technical effects of the separation manner of the LED chip 11 and the PL testing method are the same as those provided in the previous example, and are not described herein again.

The above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An LED chip is characterized by comprising a main device and an antenna structure, wherein the main device comprises a main epitaxial layer, a first electrode and a second electrode;

the main epitaxial layer comprises a first semiconductor layer and a first functional layer covering partial area of the upper surface of the first semiconductor layer; the first functional layer includes a second semiconductor layer and a first light emitting layer; the first light emitting layer is located between the first semiconductor layer and the second semiconductor layer;

the first electrode is arranged on the upper surface of the first semiconductor layer and is coupled with the first semiconductor layer;

the second electrode is arranged on the upper surface of the second semiconductor layer and is coupled with the second semiconductor layer;

the antenna structure is coupled with the first electrode and the second electrode; the antenna structure is used for receiving radio frequency signals and generating a potential difference between the first electrode and the second electrode;

wherein the antenna structure comprises a conductive coil located outside the main epitaxial layer;

a first end of the conductive coil forms a capacitor with the first electrode, and a second end of the conductive coil is in contact with the second electrode;

or,

the first end of the conductive coil and the first electrode form a capacitor, and the second end of the conductive coil and the second electrode form a capacitor.

2. The LED chip of claim 1,

a groove is formed in one side, close to the conductive coil, of the first electrode, the first end of the conductive coil extends into the groove, and a gap is formed between the first end of the conductive coil and the inner wall of the groove, so that a capacitor is formed between the first end of the conductive coil and the inner wall of the groove.

3. An LED chip is characterized by comprising a main device and an antenna structure, wherein the main device comprises a main epitaxial layer, a first electrode and a second electrode;

wherein the conduction direction of the main device is directed from the second electrode to the first electrode;

the antenna structure includes: the sub-device, the conducting wire and the conducting coil are positioned on the outer side of the main epitaxial layer;

the sub-device comprises a sub-epitaxial layer, and a first auxiliary electrode and a second auxiliary electrode which are arranged on the sub-epitaxial layer; the sub epitaxial layer and the main epitaxial layer are arranged in an insulating mode;

the conduction direction of the sub-device is directed to the first auxiliary electrode from the second auxiliary electrode;

one end of the conductive coil is contacted with the first electrode, and the other end of the conductive coil is contacted with the second auxiliary electrode;

one end of the lead is in contact with the first auxiliary electrode, and the other end of the lead is in contact with the second electrode.

4. The LED chip of claim 3, wherein said sub-epitaxial layer comprises a third semiconductor layer and a second functional layer covering a portion of the upper surface of said third semiconductor layer; the second functional layer comprises a fourth semiconductor layer and a second light-emitting layer; the second light emitting layer is positioned between the third semiconductor layer and the fourth semiconductor layer;

the first auxiliary electrode is arranged on the upper surface of the third semiconductor layer and is coupled with the third semiconductor layer;

the second auxiliary electrode is disposed on an upper surface of the fourth semiconductor layer and coupled to the fourth semiconductor layer.

5. The LED chip of claim 3, wherein said sub-epitaxial layer comprises a fifth semiconductor layer;

the first auxiliary electrode and the second auxiliary electrode are both located on the upper surface of the fifth semiconductor layer and are coupled with the fifth semiconductor layer.

6. The LED chip of claim 1 or 3, wherein any two turns of coil within the conductive coil do not intersect.

7. An LED chip comprising a main device and a remainder of an antenna structure, the main device comprising a main epitaxial layer, a first electrode and a second electrode:

the residual part of the antenna structure comprises a first metal wire, a second metal wire and at least one third metal wire, wherein the first metal wire, the second metal wire and the at least one third metal wire are positioned outside the main epitaxial layer and insulated from the main epitaxial layer; the first metal line, the second metal line and the third metal line are insulated from each other;

one end of the first metal wire is in contact with the first electrode, and the other end of the first metal wire is flush with one edge of the LED chip;

one end of the second metal wire is in contact with the second electrode, and the other end of the second metal wire is flush with one edge of the LED chip;

a portion of the third metal line is located between the first metal line and the second metal line;

two ends of the third metal wire are flush with the same edge of the LED chip; or two ends of the third metal wire are respectively flush with two different edges of the LED chip.

8. A preparation method of an LED chip is characterized by comprising the following steps:

manufacturing a main device in each building area on a substrate, wherein the substrate comprises a plurality of building areas defined by cutting lines which are crossed transversely and longitudinally; the main device comprises a main epitaxial layer, a first electrode and a second electrode; the main epitaxial layer comprises a first semiconductor layer and a first functional layer covering partial area of the upper surface of the first semiconductor layer; the first functional layer includes a second semiconductor layer and a first light emitting layer; the first light emitting layer is located between the first semiconductor layer and the second semiconductor layer; the first electrode is arranged on the upper surface of the first semiconductor layer and is coupled with the first semiconductor layer; the second electrode is arranged on the upper surface of the second semiconductor layer and is coupled with the second semiconductor layer;

manufacturing a plurality of antenna structures, wherein the plurality of antenna structures correspond to the plurality of building areas one by one, and each antenna structure is coupled with the first electrode and the second electrode in the corresponding building area to form a chip wafer; the antenna structure is used for receiving radio frequency signals and generating a potential difference between the first electrode and the second electrode in the same building area;

sending radio frequency signals to the antenna structures, collecting the luminous brightness of each main device in the chip wafer, and testing whether each main device can normally work according to the luminous brightness of each main device;

and separating the chip wafer along the cutting channel to obtain a plurality of LED chips.

9. The method of manufacturing an LED chip according to claim 8,

making the antenna structure includes: manufacturing a plurality of conductive coils on the outer side of the main epitaxial layer;

two ends of each conductive coil are respectively contacted with the first electrode and the second electrode which are positioned in the same building area, and at least one part of each conductive coil is positioned in the cutting channel between two adjacent building areas.

10. The method of manufacturing an LED chip according to claim 8,

making the antenna structure includes: manufacturing a plurality of conductive coils outside the main epitaxial layer, wherein each conductive coil is positioned in one building region;

a first end of each conductive coil forms a capacitor with the first electrode, and a second end of each conductive coil is in contact with the second electrode;

or,

and a capacitor is formed between the first end of each conductive coil and the first electrode, and a capacitor is formed between the second end of each conductive coil and the second electrode.

11. The method of manufacturing an LED chip according to claim 10,

fabricating the first electrode includes: manufacturing the first electrode on the upper surface of the first semiconductor layer, and forming a groove on the side surface of the first electrode;

manufacturing the conductive coil comprises the following steps: the first end of the conductive coil extends into the groove, and a gap is formed between the first end of the conductive coil and the inner wall of the groove, so that a capacitor is formed between the first end of the conductive coil and the inner wall of the groove.

12. The method of manufacturing an LED chip according to claim 8,

making the antenna structure includes: forming a sub-device in the building region, wherein the sub-device comprises a sub-epitaxial layer insulated from the main epitaxial layer, and a first auxiliary electrode and a second auxiliary electrode which are positioned on the sub-epitaxial layer; the conduction direction of the sub-device is directed to the first auxiliary electrode from the second auxiliary electrode;

fabricating the antenna structure further comprises: manufacturing a plurality of conductive coils and a plurality of leads outside the main epitaxial layer, wherein each building area is provided with one conductive coil and one lead;

one end of the conductive coil in each building area is in contact with the first electrode, and the other end of the conductive coil is in contact with the second auxiliary electrode;

one end of one wire in each building area is in contact with the first auxiliary electrode, and the other end of the wire is in contact with the second electrode;

the conducting direction of the main device is directed to the first electrode from the second electrode.

13. A display module comprising a substrate, and the LED chip of any one of claims 1 to 7 arranged in an array on the substrate;

each LED chip is a sub-pixel.

14. An intelligent terminal, comprising a processor and the display module of claim 13, wherein the processor is configured to control the display module to display an image.