CN110098112A - A kind of implementation method of resistant to total dose SOI integrated circuit device structure - Google Patents
A kind of implementation method of resistant to total dose SOI integrated circuit device structure Download PDFInfo
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- CN110098112A CN110098112A CN201910411177.3A CN201910411177A CN110098112A CN 110098112 A CN110098112 A CN 110098112A CN 201910411177 A CN201910411177 A CN 201910411177A CN 110098112 A CN110098112 A CN 110098112A
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000002347 injection Methods 0.000 claims abstract description 10
- 239000007924 injection Substances 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 230000003071 parasitic effect Effects 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 21
- 239000002253 acid Substances 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 4
- 230000001678 irradiating effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 28
- 229910052681 coesite Inorganic materials 0.000 description 14
- 229910052906 cristobalite Inorganic materials 0.000 description 14
- 239000000377 silicon dioxide Substances 0.000 description 14
- 229910052682 stishovite Inorganic materials 0.000 description 14
- 229910052905 tridymite Inorganic materials 0.000 description 14
- 238000007254 oxidation reaction Methods 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 10
- 239000002245 particle Substances 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 230000005855 radiation Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000000191 radiation effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 230000001235 sensitizing effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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Abstract
The invention belongs to Flouride-resistani acid phesphatase device studying technological domains, it is related to a kind of implementation method of the SOI device structure of resistant to total dose performance that can be improved device, the implementation method of resistant to total dose SOI device structure of the invention is based on SOI Substrate, is aoxidized, is deposited, etched, photoetching, ion implanting, the series of process step such as short annealing and then obtaining resistant to total dose SOI device structure of the invention.The present invention not only can reduce the parasitic leakage current caused by irradiating and threshold voltage shift, but also the structure and traditional SOI technique are completely compatible, it is only necessary to increase an injection technology, not will increase chip area, big influence will not be caused to cost.
Description
Technical field
The present invention relates to integrated circuit and fields of space technology, more particularly to one kind to be based on leading semiconductor process conditions
, the implementation method of the SOI device structure that can be improved resistant to total dose performance.
Background technique
Integrated circuit and electronic component are under radiation parameter, it will it is a variety of to generate accumulated dose, single-particle, instantaneous radiation etc.
Radiation effect.If device used by artificial earth satellite, space probe and manned spacecraft etc. and circuit, do not pass through
Special radiation hardened measure, performance will soon degenerate so that fail, and huge security risk and cost is caused to waste.
Therefore, the method with the device and circuit of high radiation preventing energy is actively found, is had for the development of space technology important
Meaning.
The oxidation layer region of MOS device and its interface between silicon materials are the sensitizing ranges of ionising radiation total dose effect
Domain, the accumulation of the oxide trapped charge due to caused by total dose effect and the increase of interface trapped charge can make MOS device
Electric property degenerate, and then may cause the disabler of integrated circuit.The electricity of MOS device caused by total dose effect
Learn performance degradation to be mainly manifested in: threshold voltage negative sense drifts about, Leakage Current increases, channel current-carrying at silica-silicon interface
Transport factor reduction, the mutual conductance reduction of MOS device and degeneration of subthreshold swing etc..
Single particle effect refer to single high energy particle pass through microelectronic component sensitive volume when cause device state it is non-just
A kind of radiation effect often changed, including the breakdown of single-particle inversion, locking single particle, single event burnout, single-particle grid etc..Simple grain
Son overturning is that single high energy particle acts on semiconductor devices, and the logic state for causing device is abnormal variation.Single-particle turns over
Turn to be most common and most classic one kind in a variety of single particle effects caused by the radiation of space, occur mainly in data storage or refers to
It enables in related device.
SOI device has due to using Fully dielectric isolation, its many characteristics and body silicon device there are apparent difference
Higher integrated level, lower power consumption and more excellent short-channel properties, and fundamentally due to the presence of buries oxide layer
Latch-up is eliminated to make the reliability of device increase substantially.
The content of present invention is to a kind of patent " novel Flouride-resistani acid phesphatase device architecture[1]" further research, in former patent
There is no specific techniques to realize step for SOI Flouride-resistani acid phesphatase structure, and this patent proposes one kind for its structure and can produce
The specific process step realized on line, make its structure is implemented as possibility.
Bibliography:
[1] a kind of novel Flouride-resistani acid phesphatase device architecture [P] .CN201710017928.4.2017.01.10 of Li Ping, Liu Yang
Summary of the invention
A kind of implementation method of resistant to total dose SOI integrated circuit device structure, the present invention are existed by series of process step
P+ secondary doping region is formed in SOI device, is provided a kind of implementation method of new resistant to total dose SOI device structure, is passed through
P+ doped region is formed, parasitic metal-oxide-semiconductor will not be formed in backgate, leakage current and threshold voltage shift is effectively reduced, effectively mentions
The high resistant to total dose performance of SOI device.
Compared with prior art, the invention has the following advantages that
1. and traditional SOI technology is compatible, need to only increase primary ions injection, not will increase chip area.
2. the selection of the P+ doped region proposed in the present invention reduces leakage current and threshold voltage shift, Ke Yiyou
Effect improves SOI device resistant to total dose performance.
Detailed description of the invention
Fig. 1 is the schematic diagram of SOI Substrate.
Fig. 2 is the schematic diagram that gate oxide is formed.
Fig. 3 is the schematic diagram that polysilicon gate is formed.
Fig. 4 is the schematic diagram that grid protection layer is formed.
Fig. 5 is the schematic diagram of the formation in LDD region domain.
Fig. 6 is the schematic diagram that nitride side wall is formed.
Fig. 7 is the schematic diagram that N+ active area is formed.
Fig. 8 is the schematic diagram that bis- injection regions P+ are formed.
Specific embodiment
As shown in Figure 1 it is the basic structure of selected SOI Substrate, had both been that one layer of 2- is buried above 1-P type doped substrate
Oxide layer SiO2, then it is one layer of 3- thin-layer silicon above 2- buries oxide layer.
It is illustrated in figure 2 1-P type doped substrate, that above p-type doped substrate is 2- buries oxide layer SiO2, bury oxidation
Layer top is 3- thin-layer silicon, forms 4- gate oxide SiO by oxidation2。
It is illustrated in figure 3 1-P type doped substrate, that above p-type doped substrate is 2- buries oxide layer SiO2, bury oxidation
Layer top is 3- thin-layer silicon, 4- gate oxide SiO2, by deposit, gluing, photoetching, etching and etc. formed 5- polysilicon gate
Pole.
It is illustrated in figure 4 1-P type doped substrate, that above p-type doped substrate is 2- buries oxide layer SiO2, bury oxidation
Layer top is 3- thin-layer silicon, 4- gate oxide SiO2, 5- polysilicon gate, the 6- grid protection layer formed by oxidation.
It is illustrated in figure 5 1-P type doped substrate, that above p-type doped substrate is 2- buries oxide layer SiO2, bury oxidation
Layer top is 3- thin-layer silicon, 4- gate oxide SiO2, 5- polysilicon gate, 6- grid protection layer, pass through ion implanting formed
7-LDD structure (is lightly doped) using N-.
It is illustrated in figure 6 1-P type doped substrate, that above p-type doped substrate is 2- buries oxide layer SiO2, bury oxidation
Layer top is 3- thin-layer silicon, 4- gate oxide SiO2, 5- polysilicon gate, 6- grid protection layer, 7-LDD structure (using N- it is light
Doping), by deposit, gluing, photoetching, etching and etc. formed 8- silicon nitride spacer.
It is illustrated in figure 7 1-P type doped substrate, that above p-type doped substrate is 2- buries oxide layer SiO2, bury oxidation
Layer top is 3- thin-layer silicon, 4- gate oxide SiO2, 5- polysilicon gate, 6- grid protection layer, 7-LDD structure (using N- it is light
Doping), 8- silicon nitride spacer, the 9-N+ active area formed by ion implanting.
It is illustrated in figure 8 1-P type doped substrate, that above p-type doped substrate is 2- buries oxide layer SiO2, bury oxidation
Layer top is 3- thin-layer silicon, 4- gate oxide SiO2, 5- polysilicon gate, 6- grid protection layer, 7-LDD structure (using N- it is light
Doping), 8- silicon nitride spacer, 9-N+ active area forms 10-P+ doped region by secondary ion injection, short annealing.
Embodiment
The substrate of 1 SOI Substrate selected is p-type doping, and doping concentration is about 1e16 < cm-3>, buries oxide layer with a thickness of
150nm, top layer silicon and p-type doping above buries oxide layer, doping concentration is about 1e17 < cm-3>, as shown in Figure 1.
2 carry out later processing operation step for selected SOI Substrate, i.e., first at 850 DEG C, do in oxygen environment, oxidation
Time 6min forms thin gate oxide, as shown in Figure 2.
3 depositing polysilicons, anisotropic growth, and rate be 0.13um/min, time 1min, then by customized
Mask, progress photoetching, then the polysilicon extra by anisotropic etching, etch rate 0.15um/min, time 1min,
Fall extra gate oxide finally by anisotropic etching, etch rate 0.01um/min, time 1min form polycrystalline
Silicon gate, as shown in Figure 3.
4 at 900 DEG C, do in oxygen environment, oxidization time 3min, form grid protection layer, as shown in Figure 4.
5 form LDD structure by ion implanting, and injection element is arsenic, and implantation dosage is 4e11 < cm-2>, Implantation Energy
For 6<keV>, vertical injection, then under 1050 DEG C of environment, anneal 5s, and the LDD structure eventually formed is as shown in Figure 5.
6 by deposit formed nitride, isotropic growth, and rate be 0.05um/min, time 1min, then pass through
Anisotropic etching etches away extra nitride, etch rate 0.074um/min, time 1min, finally by it is each to
Anisotropic etch etches away extra oxide layer, etch rate 0.01um/min, time 1min, the nitride side eventually formed
Wall is as shown in Figure 6.
7 form N+ active area by ion implanting again, and injection element is arsenic, and implantation dosage is 3e13 < cm-2>, inject energy
Amount is 8<keV>, and incident angle is 7 °, and the active area doping of formation is as shown in Figure 7.
8 form P+ doped region by ion implanting again below source region, and injection element is boron, and implantation dosage for 2e13 <
cm-2>, Implantation Energy be 14<keV>, vertical incidence, then under 1050 DEG C of environment, short annealing 5s, the SOI device eventually formed
Part structure is as shown in Figure 8.
Claims (3)
1. a kind of process implementation method of resistant to total dose SOI integrated circuit device structure, which is characterized in that in traditional SOI device
On the basis of, the processing step by increasing additional primary ions injection, short annealing obtains the resistant to total dose SOI in the present invention
Device architecture.
2. increased additional ion implanting as described in claim 1 and rta technique step, which is characterized in that in source
Below the active area of pole, very thin doped region identical with channel region doping type is formed by ion implanting, passes through control
Energy, dosage and the angle of ion implanting and the temperature and time of short annealing, so that it may obtain the SOI device of resistant to total dose
Part structure, the formation in this region and traditional SOI process compatible, only need to increase primary injection, will not increase chip area.
3. increased additional ion implanting as described in claim 1 and rta technique step, which is characterized in that can be with
The parasitic metal-oxide-semiconductor for eliminating SOI top layer silicon bottom, can effectively reduce leakage current and threshold voltage shift, to effectively improve
The resistant to total dose performance of SOI device.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110676252A (en) * | 2019-09-12 | 2020-01-10 | 北京时代民芯科技有限公司 | Integrated circuit layout structure with reinforced instantaneous radiation resistance |
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| JP2009224721A (en) * | 2008-03-18 | 2009-10-01 | Shin Etsu Chem Co Ltd | Method of manufacturing soi substrate |
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| US8361829B1 (en) * | 2011-08-31 | 2013-01-29 | International Business Machines Corporation | On-chip radiation dosimeter |
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| CN106449760A (en) * | 2016-11-02 | 2017-02-22 | 西安电子科技大学 | SOI (silicon on insulator) substrate based ring-gate radiation-proof MOS (metal oxide semiconductor) field-effect transistor |
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2019
- 2019-05-17 CN CN201910411177.3A patent/CN110098112A/en active Pending
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| JP2009224721A (en) * | 2008-03-18 | 2009-10-01 | Shin Etsu Chem Co Ltd | Method of manufacturing soi substrate |
| CN102194827A (en) * | 2010-03-16 | 2011-09-21 | 北京大学 | High-dielectric-constant material-based irradiation-resistance SOI (Silicon on Insulator) device and manufacturing method thereof |
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| 李艳艳等: "一种基于总剂量效应的SOI 器件模型快速提取方法", 《电子与封装》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110676252A (en) * | 2019-09-12 | 2020-01-10 | 北京时代民芯科技有限公司 | Integrated circuit layout structure with reinforced instantaneous radiation resistance |
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