CN118824336A

CN118824336A - Memory, built-in self-test method and test system

Info

Publication number: CN118824336A
Application number: CN202310383355.2A
Authority: CN
Inventors: 张瑞
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-04-06
Filing date: 2023-04-06
Publication date: 2024-10-22

Abstract

The present disclosure provides a memory, a built-in self-test method and a test system, the memory includes a counter for counting error data bits obtained by data verification, 1 flag pulse signal is generated every 1 data error is detected in the process of performing the built-in self-test on the memory, and the flag pulse signal is counted by the counter.

Description

Memory, built-in self-test method and test system

Technical Field

The present disclosure relates to the field of semiconductors, and more particularly, to a memory, a built-in self-test method, and a test system.

Background

Memory Build-In-Self Test (MBIST) is a Design For Test (DFT) technique that places a Test structure of a device inside the device, automatically generates a Test vector For a target circuit, and compares output results to obtain a final Test result of a chip. Currently, in MBIST testing, only 2 error addresses are recorded due to the limitation of chip area, and then repaired by a Post-package repair (Memory Post PACKAGE REPAIR, MPPR) technique.

Disclosure of Invention

The present disclosure provides a memory, a built-in self-test method and a test system.

The technical scheme of the present disclosure is realized as follows:

In a first aspect, embodiments of the present disclosure provide a memory, where the memory includes a counter, and the counter is configured to count erroneous data bits obtained by data verification; the memory also comprises a built-in self-test module; the built-in self-test module is configured to perform self-test by using built-in self-test logic, and outputs 1 mark pulse signal when 1 data error is detected in the process of executing the self-test; the counter is connected with the built-in self-test module and is configured to receive the marking pulse signals and count the marking pulse signals in the self-test process.

In some embodiments, the counter comprises a first counter and a second counter; the counter is configured to add one to the count value of the first counter when the count value of the first counter does not reach the maximum value and each time 1 marking pulse signal is received; and after the count value of the first counter reaches the maximum value, when the next marking pulse signal is received, adding one to the count value of the second counter and the count value of the first counter respectively.

In some embodiments, the counter is further configured to receive a first type of pulse signal and a second type of pulse signal, count the first type of pulse signal with the first counter, and count the second type of pulse signal with the second counter; each first type pulse signal represents that data transmitted by an odd clock is found by data verification, each second type pulse signal represents that data transmitted by an even clock is found by data verification, and the phases of the system odd clock signal and the system even clock signal are opposite.

In some embodiments, the counter further comprises a first logic unit; the input end of the first logic unit is used for receiving the marking pulse signal and the first type pulse signal, and the output end of the first logic unit is connected with the first counter; the first logic unit is configured to output 1 first processing signal if 1 sign pulse signal or 1 first type pulse signal is received; the first counter is configured to count the first processing signal.

In some embodiments, the first counter is further configured to output a low-order carry signal of the first state if its own count value reaches a maximum value; if the count value of the carry signal does not reach the maximum value, outputting a carry signal in a second state; the counter also comprises a gating unit and a second logic unit, wherein the input end of the gating unit receives the marking pulse signal and the carry signal, and the output end of the gating unit is used for outputting an intermediate pulse signal; the input end of the second logic unit receives the intermediate pulse signal and the second type pulse signal; the gating unit is configured to output the marking pulse signal as an intermediate pulse signal when the carry signal is in a first state; or shielding the flag pulse signal when the carry signal is in the second state; the second logic unit is connected with the gate control unit and is configured to receive the intermediate pulse signal and output the intermediate pulse signal as a second processing signal; or receiving the second type pulse signal and outputting the second type pulse signal as the second processing signal; the second counter is configured to count the second processing signal.

In some embodiments, the first type of pulse signal includes a first result signal and a second result signal, three input ends of the first logic unit are respectively used for receiving the first result signal, the second result signal and the flag pulse signal, and an output end of the first logic unit is used for outputting the first processing signal; the first result signal characterizes that the low byte data transmitted by the odd clock is found by data verification, and the second result signal characterizes that the high byte data transmitted by the odd clock is found by data verification.

In some embodiments, the second type pulse signal includes a third result signal and a fourth result signal, three input ends of the second logic unit are respectively used for receiving the third result signal, the fourth result signal and the intermediate pulse signal, and an output end of the second logic unit is used for outputting the second processing signal; the third result signal represents that the low-byte data transmitted by the even clock is found to be wrong through data verification, and the fourth result signal represents that the high-byte data transmitted by the even clock is found to be wrong through data verification.

In some embodiments, the first counter is further configured to receive a first enable signal; wherein the first enable signal in an enable state is used to enable the first counter, the first enable signal being in an enable state during at least part of the self-test phase and at least part of the data verification phase; the second counter is further configured to receive a second enable signal; wherein the second enable signal in an enable state is used to enable the second counter, the second enable signal being in an enable state during at least part of the self-test phase and at least part of the data verification phase.

In some embodiments, the counter is further configured to, after the self-test is finished, combine the count value of the first counter and the count value of the second counter to output as a final error value to indicate the total number of errors detected in the self-test at this time.

In a second aspect, an embodiment of the present disclosure provides a test method applied to a memory including a counter, where the counter is configured to count erroneous data bits obtained by data verification; the method comprises the following steps:

in the built-in self-test mode, self-test is performed by using built-in self-test logic; and counting the detected data errors by using the counter in the self-test process.

In some embodiments, the counter comprises a first counter and a second counter; the counting of the detected data errors with a counter includes:

If the count value of the first counter does not reach the maximum value, adding one to the count value of the first counter every time 1 data error is detected; and if the count value of the first counter reaches the maximum value, adding one to the count value of the second counter and the count value of the first counter when the next data error is detected.

In some embodiments, the method further comprises:

Counting the first type of errors by using the first counter; counting the second type of errors by using the second counter; each first type pulse signal represents that data transmitted by an odd clock is found by data verification, each second type pulse signal represents that data transmitted by an even clock is found by data verification, and the phases of the system odd clock signal and the system even clock signal are opposite.

In some embodiments, the method further comprises:

and after the self-test is finished, combining and outputting the count value of the first counter and the count value of the second counter to be final error values so as to indicate the total number of errors detected in the self-test.

In a third aspect, embodiments of the present disclosure provide a test system, the test system including a memory controller and a memory, the memory controller and the memory being connected; the memory controller is configured to send a self-test instruction to the memory; the memory is configured to perform a self-test using built-in test logic after receiving the self-test instruction, and to count detected data errors using a counter during the self-test.

The embodiment of the disclosure provides a memory, a built-in self-test method and a test system, which can count data errors detected by the built-in self-test by using a counter in a data verification process, so that the built-in self-test can provide more test result information, the test efficiency is improved, the test functions are enriched, the influence on the circuit area of the memory is small, and the performance of the memory is not reduced.

Drawings

Fig. 1 is a schematic structural diagram of a memory according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of another memory according to an embodiment of the disclosure;

fig. 3 is a schematic partial structure of a first counter according to an embodiment of the disclosure;

FIG. 4 is a schematic diagram of a partial structure of a second counter according to an embodiment of the disclosure;

fig. 5 is a schematic diagram of a partial structure of a counter according to an embodiment of the disclosure;

fig. 6 is a schematic diagram of a partial structure of a counter according to an embodiment of the disclosure;

FIG. 7 is a flow chart of a built-in self-test method according to an embodiment of the disclosure;

Fig. 8 is a schematic structural diagram of a test system according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting of the application. It should be noted that, for convenience of description, only a portion related to the related application is shown in the drawings. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure. In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict. It should be noted that the term "first/second/third" in relation to the embodiments of the present disclosure is merely used to distinguish similar objects and does not represent a particular ordering for the objects, it being understood that the "first/second/third" may be interchanged with a particular order or sequencing, if allowed, to enable the embodiments of the present disclosure described herein to be implemented in an order other than illustrated or described.

As previously mentioned, the MBIST test can only record 2 erroneous addresses in a first-in-first-out manner. In this way, in the test process after the Chip is produced, whether the MBIST function is correct can only be verified by comparing whether the last 2 error addresses captured by the MBIST test are included in the error addresses captured in the wafer test (CP)/semiconductor process (FINAL TEST, FT) test, but whether other error address MBIST tests are detected cannot be judged, so that whether the MBIST function is correct cannot be well judged; in addition, during the system level Test, some Test modes (Test Mode) can make part of errors disappear through part of means (such as loosening timing), but MBIST Test can only record the last 2 error addresses, and cannot embody the effect brought by the improvement means, so that the improvement means of the Test modes cannot be used normally.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In one embodiment of the present disclosure, referring to FIG. 1, a schematic diagram of a memory 10 provided by an embodiment of the present disclosure is shown. The memory 10 supports an error checking and correction (Error Correcting Code, ECC) function that performs data checking on stored data through parity checking principles, improving data stability of the memory 10. As shown in fig. 1, the memory 10 includes a counter 11, and the counter 11 is used for counting error data bits obtained by data verification. That is, the counter 11 is used to count the error data bits detected in the ECC process, and may also be referred to as an ECC counter.

Memory 10 also includes a built-in self-test module 12; the built-in self-test module 12 is configured to perform self-test by using built-in self-test logic, and output 1 flag pulse signal when 1 data error is detected in the process of performing self-test;

the counter 11 is connected with the built-in self-test module 12 and is configured to receive the marking pulse signal and count the marking pulse signal in the self-test process.

It should be noted that the memory 10 may be various types of memories that support ECC functions, such as dynamic random access memory (Dynamic Random Access Memory, DRAM), synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM), double data rate memory (Double DATA RATE SDRAM, DDR), low Power DDR (LPDDR).

It should be appreciated that the built-in self-test and data verification (otherwise referred to as ECC operation) do not occur simultaneously, so the counter 11 in the ECC function may be multiplexed for error counting during the built-in self-test. That is, the counter 11 is used to count errors checked for data verification when the memory 10 performs an ECC operation; the counter 11 is used to count errors detected during the self-test when the memory 10 performs the built-in self-test.

Thus, on the one hand, the total number of errors detected by the built-in self-test is recorded, and the test result of the final test of the wafer is combined to accurately judge whether the built-in self-test module 12 works normally or not, and the specific influence of the improvement means on the data errors can be embodied during the system level test; on the other hand, since the error count of the built-in self-test is multiplexed with the counter in the ECC function, the area occupied by the built-in self-test module 12 is hardly increased additionally, avoiding increasing extra cost or degrading chip performance.

Since the ECC operation generates result signals indicating different types of data errors, the counter 11 needs to support the counts of these result signals, respectively, and thus the counter 11 includes at least 2 sub-counters capable of supporting independent counts; but the built-in self-test only generates a result signal (i.e. a flag pulse signal) indicating one kind of data error, different sub-counters in the counter 11 can be combined to achieve a larger count range.

Thus, in some embodiments, as shown in fig. 2, the counter 11 includes a first counter 111 and a second counter 112; a counter 11 configured to add one to the count value of the first counter 111 (i.e., the first count value in fig. 2) every time 1 flag pulse signal is received when the count value of the first counter 111 does not reach the maximum value; and, after the count value of the first counter 111 reaches the maximum value, when the next flag pulse signal is received, the count value of the second counter 112 (i.e., the second count value in fig. 2) and the count value of the first counter 111 are each subjected to one-up processing.

That is, the counter 11 is further configured to combine and output the count value of the first counter 111 and the count value of the second counter 112 as a final error value after the self-test is completed, to indicate the total number of errors detected in the present self-test.

It should be noted that the first counter 111 includes a plurality of cascaded asynchronous counters. As shown in fig. 3, the first counter 111 includes a cascade of a flip-flops, each having an input connected to its own inverting output, a 1 st flip-flop having a clock terminal forming the input of the entire counter 111, an i-th flip-flop having a clock terminal connected to its inverting output, and an output outputting a one-bit sub-signal of a first count value < a-1:0 >. The second counter 112 is similar in structure, as shown in FIG. 4, and the second counter 112 includes B cascaded flip-flops, which are connected in a similar manner as described above, and the output terminal of each flip-flop outputs a one-bit sub-signal of the second count value < B-1:0 >. The flip-flop may be a D-type flip-flop, with both a and B being positive integers.

Thus, when the first counter 111 and the second counter 112 count independently, the first counter 111 counts in the range of 0 to 2 ^A -1, and the second counter 112 counts in the range of 0 to 2 ^B -1. Since there is only one type of error in the built-in self test, the first counter 111 can be regarded as a low-order counter, the second counter 112 can be regarded as a high-order counter, i.e. the first counter 111 is fully charged and then carries the second counter 112, and the count values of the two can be combined to be represented as a final count value < a+b-1:0>, i.e. the second count value < a-1:0> is regarded as a final count value < a-1:0>, and the second count value < B-1 >: 0> is considered as the final count value < a+b-1: a > and the final count value is 0-2 ^A+B -1, the count range is expanded, and the counter 11 is fully utilized.

It should be understood that fig. 3 simply illustrates a circuit portion related to counting in the first counter 111, and does not limit the configuration of the first counter 111; fig. 4 simply shows a circuit portion related to counting in the second counter 112, and does not limit the configuration of the second counter 112. Other logic processing devices may be included in both the first counter 111 and the second counter 112.

In some embodiments, the counter 11 is further configured to receive a first type of pulse signal and a second type of pulse signal, count the first type of pulse signal with the first counter 111, and count the second type of pulse signal with the second counter 112.

It should be noted that the first type pulse signal/the second type pulse signal are both result signals generated in the ECC operation, and are used to indicate different types of errors detected by the data check. Specifically, each first type pulse signal represents that data transmitted by using an odd clock is found to be wrong through data verification, and each second type pulse signal represents that data transmitted by using an even clock is found to be wrong through data verification, and the phases of a system odd clock signal and a system even clock signal are opposite.

Thus, during the ECC operation, the counter 11 counts the first type pulse signal and the second type pulse signal independently; during the built-in self-test, the counter 11 counts only the flag pulse signal.

In particular, the sign pulse signal, the first type pulse signal and the second type pulse signal may be positive pulses or negative pulses, and the pulse types of the sign pulse signal, the first type pulse signal and the second type pulse signal are not necessarily the same. In general, the number of pulses included in the 1 flag pulse signal is 1, but in other embodiments, the number of pulses included in the 1 flag pulse signal may be plural; the same is true for 1 first type pulse signal and 1 second type pulse signal.

In some embodiments, as shown in fig. 2, the counter 11 further comprises a first logic unit 13; the input end of the first logic unit 13 is used for receiving the marking pulse signal and the first type pulse signal, and the output end of the first logic unit 13 is connected with the first counter 111; a first logic unit 13 configured to output 1 first processing signal if 1 flag pulse signal or 1 first type pulse signal is received; the first counter 111 is configured to count the first processing signal.

It should be noted that the first logic unit 13 may include, but is not limited to, the following: and gate, not gate, or gate, nand gate, nor gate, exclusive or gate.

Here, the specific circuit configuration of the first logic unit 13 needs to be determined according to the pulse types and the pulse numbers of the flag pulse signal and the first type pulse signal. For example, assuming that the flag pulse signal and the first type pulse signal are both positive pulses, the first logic unit 13 may select a first or gate with two inputs to output the enabled signal as the first processing signal when the first type pulse signal or the flag pulse signal is enabled, and the first or gate may be formed by a combination of a nor gate and a nor gate; also for example, assuming that the flag pulse signal and the first type pulse signal are both negative pulses, the first logic unit 13 may select a first and gate with two inputs; if each enabled flag pulse signal and each first type pulse signal are accurately captured to ensure the accuracy of the logic processing, each flag pulse signal and each first type pulse signal is composed of a plurality of pulses, the first logic unit 13 also needs to output only one pulse, so that the first counter 11 and the second counter 12 are conveniently counted, or the first counter 11 and the second counter 12 are controlled to be counted only once in a specific period, so that the counting accuracy is improved under the condition of avoiding counting omission. It will be appreciated that the above-described outputting of only one pulse or counting only once within a specific period can be achieved by providing the sampling unit, by controlling the sampling clock period of the sampling unit.

Thus, during the ECC operation, the first counter 111 counts the first type of pulse signals; during the internal self-test, the first counter 111 counts the flag pulse signal.

In some embodiments, as shown in fig. 2, the first counter 111 is further configured to output a carry signal of the first state if its own count value reaches a maximum value; and if the count value of the carry signal does not reach the maximum value, outputting the carry signal in the second state. Here, the first state and the second state are different.

The counter 11 further comprises a gate control unit 14 and a second logic unit 15, wherein the input end of the gate control unit 14 receives the marking pulse signal and the carry signal, and the output end of the gate control unit 14 is used for outputting an intermediate pulse signal; the input end of the second logic unit 15 receives the intermediate pulse signal and the second type pulse signal; specifically, the gate control unit 14 is configured to output the flag pulse signal as an intermediate pulse signal when the carry signal is in the first state; or shielding the mark pulse signal when the carry signal is in the second state; a second logic unit 15 connected to the gate control unit 14 and configured to receive the intermediate pulse signal and output the intermediate pulse signal as a second processing signal; or receiving a second type pulse signal and outputting the second type pulse signal as a second processing signal; a second counter 112 configured to count the second processing signal.

It should be noted that the gate control unit 14 may include, but is not limited to, the following: and gate, not gate, or gate, nand gate, nor gate, depending on the definition of the first state and the second state. For example, if the first state is high and the second state is low, the gate control unit 14 may be a second and gate; for another example, if the first state is low and the second state is high, the gate unit 14 may be an exclusive or gate.

The second logic unit 15 may include, but is not limited to, the following: and gate, not gate, or gate, nand gate, nor gate, exclusive or gate, depending on the pulse type and the number of pulses of the second type of pulse signal and the intermediate pulse signal. For example, assuming that the second type pulse signal and the intermediate pulse signal are both positive pulses, the second logic unit 15 may select a second or gate with two inputs, and the second or gate may be formed by a combination of nor gate and not gate. Also by way of example, assuming that the second type pulse signal and the intermediate pulse signal are both negative pulses, the second logic unit 15 may select a second input third AND gate; if each second type pulse signal or each intermediate pulse signal is composed of a plurality of pulses, the second logic unit may be configured to use the first logic unit, or the second counter may be configured to use the first counter and the sampling clock signal.

Thus, during the ECC operation, the second counter 112 counts the second type of pulse signal; in the built-in self-test process, after the count value of the first counter 111 reaches the maximum value, the next flag pulse signal triggers the count of the second counter 112 and clears the count value of the first counter 111. It can be appreciated that after the count value of the first counter 111 is cleared, the carry signal re-enters the sleep state, that is, the carry signal is in the enable state only when the first counter 111 is full.

Referring to fig. 5, a partial structure of the counter 11 in a specific scenario is provided below. In fig. 5, the flag pulse signal is denoted mBistErrCnt, the carry signal is denoted LowerAllHigh, the first processing signal is denoted ErrCntLo, and the second processing signal is denoted ErrCntHi.

In some embodiments, as shown in fig. 5, the first type of pulse signal includes a first result signal OddLo and a second result signal OddHi, the first result signal OddLo being indicative of low byte data being transmitted with an odd clock being subject to data verification for errors, the second result signal OddHi being indicative of high byte data being transmitted with an odd clock being subject to data verification for errors.

It should be noted that, when the first result signal OddLo and the second result signal OddHi are enabled at the same time, the input timings of the two should be staggered according to the count number of the unit time of the first counter 111, so as to avoid omission.

Correspondingly, the three input terminals of the first logic unit 13 are respectively configured to receive the first result signal OddLo, the second result signal OddHi, and the flag pulse signal mBistErrCnt, and the output terminal of the first logic unit 13 is configured to output the first processing signal ErrCntLo.

Since the first result signal OddLo and the second result signal OddHi both belong to the first type of pulse signal, receiving "1 first result signal OddLo or receiving 1 second result signal OddHi at the same time or in the counting period of the first counter is equivalent to" receiving 1 first type of pulse signal ".

In a specific embodiment, the first logic unit 13 is specifically configured to generate 1 first processing signal ErrCntLo if any one of the first result signal OddLo, the second result signal OddHi, and the flag pulse signal mBistErrCnt is received.

It should be noted that the first result signal OddLo and the second result signal OddHi may be non-pulse signals or pulse signals. In the case where the first result signal OddLo and the second result signal OddHi are pulse signals, the pulse types and the specific pulse numbers thereof are not limited. Accordingly, the specific circuit configuration of the first logic unit 13 needs to be determined according to the pulse types and the specific pulse numbers of the flag pulse signal mBistErrCnt, the first result signal OddLo, and the second result signal OddHi.

As shown in fig. 5, assuming that the sign pulse signal mBistErrCnt, the first result signal OddLo, and the second result signal OddHi are positive pulses, the first logic unit 13 may select the first nor gate 211 and the first nor gate 212 with three inputs, the three inputs of the first nor gate 211 respectively receive the first result signal OddLo, the second result signal OddHi, and the sign pulse signal mBistErrCnt, the output of the first nor gate 211 outputs the first inverted signal ErrCntLoN, and the first inverted signal ErrCntLoN generates the first processing signal ErrCntLo through the first nor gate 212.

In some embodiments, as shown in fig. 3, the second type of pulse signal includes a third result signal EvenLo and a fourth result signal EvenHi, three inputs of the second logic unit 15 are respectively configured to receive the third result signal EvenLo, the fourth result signal EvenHi, and the intermediate pulse signal, and an output of the second logic unit 15 is configured to output a second processed signal ErrCntHi; the third result signal EvenLo characterizes the low-byte data transmitted with the even clock as found errors by data verification, and the fourth result signal EvenHi characterizes the high-byte data transmitted with the even clock as found errors by data verification.

It should be noted that, when the third result signal EvenLo and the fourth result signal EvenHi are enabled at the same time, the input timings of the third result signal EvenLo and the fourth result signal EvenHi should be staggered according to the count number of times of the first counter 111 in unit time, so as to avoid omission.

It should be noted that, since the third result signal EvenLo and the fourth result signal EvenHi both belong to the second type pulse signal, the "receiving 1 third result signal EvenLo or receiving 1 fourth result signal EvenHi at the same time or in the counting period of the second counter" is equal to the "receiving 1 second type pulse signal". It should be appreciated that the third result signal EvenLo/fourth result signal EvenHi may be a non-pulsed signal or a pulsed signal, while the type of pulses and the particular number of pulses are not limited. Accordingly, the specific circuit configuration of the second logic unit 15 needs to be determined according to the pulse types of the intermediate pulse signal, the third result signal EvenLo, and the fourth result signal EvenHi.

As shown in fig. 5, assuming that the intermediate pulse signal, the third result signal EvenLo, and the fourth result signal EvenHi are positive pulses, the second logic unit 15 may select the second nor gate 214 and the second nor gate 215 with three inputs, the three inputs of the second nor gate 214 respectively receive the intermediate pulse signal, the third result signal EvenLo, and the fourth result signal EvenHi, the output of the second nor gate 214 outputs the second inverted signal ERRCNTHIN, and the first inverted signal ErrCntLoN generates the second processed signal ErrCntHi via the second nor gate 215.

It should also be noted that the ECC operation has multiple verification modes, and that the specific error types characterized by the first result signal OddLo, the second result signal OddHi, the third result signal EvenLo, and the fourth result signal EvenHi may be different, such as corrected errors, uncorrected errors, single byte errors, multi-byte errors, and so forth, in different verification modes.

In a specific embodiment, as shown in fig. 5, the memory 10 further includes a first logic 221, a second logic 222, a third logic 223, and a fourth logic 224. Specific:

A first input terminal of the first logic 221 receives the first check signal DsfUeOdNLo, a second input terminal of the first logic 221 receives the second check signal DsfCeOdNLo, and an output terminal of the first logic 221 outputs the first result signal OddLo;

The first input of the second logic 222 receives the third check signal DsfCeOdNHi, the second input of the second logic 222 receives the fourth check signal DsfUeOdNHi, and the output of the second logic 222 outputs the second result signal OddHi;

A first input terminal of the third logic 223 receives the fifth check signal SBECntNLo, a second input terminal of the third logic 223 receives the sixth check signal DBETrgNLo, and an output terminal of the third logic 223 outputs a third result signal EvenLo;

The first input of the fourth logic 224 receives the seventh check signal SBECntNHi, the second input of the fourth logic 224 receives the eighth check signal DBETrgNHi, and the output of the fourth logic 224 outputs the fourth result signal EvenHi.

It should be noted that, the error correction conditions indicated by the first check signal DsfUeOdNLo and the second check signal DsfCeOdNLo are different, so that they are generated at different times; the error correction conditions indicated by the third check signal DsfCeOdNHi and the fourth check signal DsfUeOdNHi are different, so they are not generated at the same time; the number of errors indicated by the fifth check signal SBECntNLo and the sixth check signal DBETrgNLo are different, both generated at different times; the number of errors indicated by the seventh check signal SBECntNHi and the eighth check signal DBETrgNHi are different and are generated at different times.

Illustratively, the first check signal DsfUeOdNLo characterizes the low-byte data transmitted with the odd clock as being data-verified for errors and the errors are uncorrected, and the second check signal DsfCeOdNLo characterizes the low-byte data transmitted with the odd clock as being data-verified for errors and the errors are corrected; the third check signal DsfCeOdNHi characterizes the high-byte data transmitted with the odd clock that errors are found to exist and the errors are not corrected by data verification, and the fourth check signal DsfUeOdNHi characterizes the high-byte data transmitted with the odd clock that errors are found to exist and the errors are corrected by data verification; the fifth check signal SBECntNLo indicates that the low-byte data transmitted by the even clock is found to have single-data bit errors through data check, the sixth check signal DBETrgNLo indicates that the low-byte data transmitted by the even clock is found to have double-data bit errors through data check, when the single-data bit errors exist, the fifth check signal SBECntNLo is enabled, when the error data bit continues to increase, that is, when the double-data bit errors exist, the sixth check signal DBETrgNLo is enabled, that is, when the double-data bit errors refer to the even-numbered error data bits, the number of the error data bits returns to the odd number when the error data bit continues to increase, and the fifth check signal SBECntNLo is enabled at the moment, and the like; the seventh check signal SBECntNHi indicates that the high byte data transmitted by the even clock is found to have a single data bit error through data checking, the eighth check signal DBETrgNHi indicates that the high byte data transmitted by the even clock is found to have a double data bit error through data checking, and the seventh check signal SBECntNHi is enabled when the single data bit error exists, and the eighth check signal DBETrgNHi is enabled when the error data bit continues to increase, that is, when the double data bit error exists, that is, the double data bit error refers to the even error data bit exists, and the number of the error data bits returns to the odd number when the error data bit continues to increase, and the seventh check signal SBECntNHi is enabled at the same time. The above is only an example, and the meaning of the first check signal DsfUeOdNLo to the eighth check signal DBETrgNHi may vary according to the specific function of the actual circuit and the ECC, and correspondingly, the meaning of the first result signal OddLo to the fourth result signal EvenHi may also vary.

In other embodiments, the fifth check signal SBECntNLo characterizes the low-byte data transferred using the even clock as found to have an odd-bit data error, e.g., bit 1, bit 3, and the sixth check signal DBETrgNLo characterizes the low-byte data transferred using the even clock as found to have an even-bit data error, e.g., bit 2, bit 4; the seventh check signal SBECntNHi characterizes the high-byte data transmitted with the even clock as found to have an odd-bit data error through data checking, and the eighth check signal DBETrgNHi characterizes the high-byte data transmitted with the even clock as found to have an even-bit data error through data checking.

In particular, the first inspection signal DsfUeOdNLo to the eighth inspection signal DBETrgNHi may be non-pulse signals or pulse signals, respectively, and the pulse type and the pulse number are not limited. In the case where the first to eighth check signals DsfUeOdNLo to DBETrgNHi are all negative pulses, as shown in fig. 5, the first logic 221 may use a first nand gate with two inputs, the second logic 222 may use a second nand gate with two inputs, the third logic 223 may use a third nand gate with two inputs, and the fourth logic 224 may use a fourth nand gate with two inputs.

Referring to fig. 6, a schematic diagram of signal connection of the first counter 111 and the second counter 112 is shown. Fig. 6 shows an example of a=16 and b=16, whereby the first count value is denoted ErrCountLo <15:0>, and the second count value is denoted ErrCountHi < 15:0.

In some embodiments, as shown in fig. 6, the first counter 111 is further configured to receive a first enable signal EnErrCntLo; wherein the first enable signal EnErrCntLo in the enable state is used to enable the first counter 111, and the first enable signal EnErrCntLo is in the enable state during at least a portion of the self-test phase and at least a portion of the data verification phase;

A second counter 112 further configured to receive a second enable signal ENERRCNTHI; wherein the second enable signal ENERRCNTHI in the enable state is used to enable the second counter 112, and the second enable signal ENERRCNTHI is in the enable state during at least a portion of the self-test phase and at least a portion of the data verification phase.

It should be noted that, for the first enable signal EnErrCntLo, the enable state may be high or low; the second enable signal ENERRCNTHI may be high or low in its enable state. In this way, for the first counter 111/the second counter 112, both in the ECC operation and in the MBIST test, the corresponding error count is performed, which improves the use efficiency of the device and also enables the MBIST test result to provide more information.

In some embodiments, the first counter 111 is further configured to receive the reset signal Rst and perform a reset operation based on the reset signal Rst; the second counter 112 is further configured to receive the reset signal Rst and perform a reset operation based on the reset signal Rst.

Thus, after each counting is completed, the first counter 111 and the second counter 112 perform a reset operation, that is, the count value ErrCountLo <15:0> of the first counter 111 and the count value ErrCountHi <15:0> of the second counter 112 are cleared, and wait for the next counting process.

In summary, the multiplexing ECC counter (i.e., the counter 11) according to the embodiment of the disclosure achieves the error (Fail) count in the MBIST test, as shown in FIG. 5, the error count of the MBIST test is combined with the error count of the ECC, i.e., the flag pulse signal mBistErrCnt is also input to the counter 11 (which is originally used for performing the error count of the ECC). Since the counter 11 includes the first counter 111 and the second counter 112, each of which outputs a count value of 16 bits (count value is at most 2 ¹⁶ -1), independent counting of different types of errors can be achieved; however, MBIST test generates only one type of error, so the first counter 111 and the second counter 112 are combined, and the first counter 111 is fully charged and then carries to the second counter 112, and a total count value of 32 bits (the count value is 2 ³² -1 at maximum) can be output to represent the total number of errors of MBIST test. Embodiments of the present disclosure have advantages in at least the following aspects: on the one hand, by comparing the total number of errors recorded by the MBIST test with the total number of errors obtained by the CP/FT test under the same condition, a test engineer can more accurately verify whether the MBIST function operates normally; on the other hand, a data Retention time Test (Data Retention Stress) can be performed on a storage unit of the memory by using a Test Mode (Test Mode) carried by an MBIST Test, and the recovery performance of the chip is obtained based on the total number of errors recorded by the MBIST Test, so that the recovery performance is associated with an automatic machine table (Auto Test Equipment, ATE) Test result; on the other hand, the chip with memory failure (core TIMING FAIL) caused by time sequence tension can be quickly corrected (realized by loosening time sequence timing) through the Test Mode of the Test unit carried by the MBIST, if the error disappears after the time sequence is loosened, the data writing error or abnormal writing caused by the time sequence tension is indicated, and the verification result is determined according to the total number of errors recorded by the MBIST Test; on the other hand, the error count multiplexing circuit for MBIST test is implemented by the existing ECC counter, so that the cost for the chip area is very small, and no extra counting circuit is introduced.

In another embodiment of the present disclosure, referring to fig. 7, a schematic flow chart of a built-in self-test method provided by an embodiment of the present disclosure is shown. The method is applied to a memory comprising a counter for counting erroneous data bits resulting from a data check, i.e. the counter is used for counting errors in an ECC operation. As shown in fig. 7, the flow includes:

S301: in the built-in self-test mode, self-test is performed using built-in self-test logic.

S302: during the self-test, the detected data errors are counted using a counter.

if the count value of the first counter does not reach the maximum value, adding one to the count value of the first counter every time 1 data error is detected;

If the count value of the first counter reaches the maximum value, when the next data error is detected, adding one to the count value of the second counter and the count value of the first counter.

In some embodiments, the method further comprises:

Counting the first type of errors by using a first counter; counting the second type of errors by using a second counter;

each first type pulse signal represents that data transmitted by an odd clock is found to be wrong through data verification, and each second type pulse signal represents that data transmitted by an even clock is found to be wrong through data verification, and the phases of a system odd clock signal and a system even clock signal are opposite.

In some embodiments, the method further comprises:

After the self-test is finished, the count value of the first counter and the count value of the second counter are combined and output to be a final error value so as to indicate the total number of errors detected in the self-test.

In this way, the embodiment of the disclosure counts the data errors detected in the built-in self-test by using the counter in the ECC operation, on one hand, the total number of errors detected by the built-in self-test is recorded, whether the built-in self-test works normally can be accurately judged by combining the test result of the CP/FT test, and the specific influence of the improvement means on the data errors can be embodied in the system level test; on the other hand, since the error count of the built-in self-test is multiplexed with the counter in the ECC function, no extra chip area is required.

In yet another embodiment of the present disclosure, reference is made to FIG. 8, which illustrates a schematic diagram of the composition and structure of a test system 40 provided by an embodiment of the present disclosure. As shown in fig. 8, the test system 40 includes a memory controller 401 and the aforementioned memory 10, and the memory controller 401 is connected to the memory 10;

a memory controller 401 configured to send a self-test instruction to the memory 10;

the memory 10 is configured to perform a self-test using built-in test logic after receiving a self-test instruction, during which the detected data errors are counted using a counter.

The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments. The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A memory, wherein the memory comprises a counter, and the counter is used for counting error data bits obtained by data verification;

the memory also comprises a built-in self-test module;

the built-in self-test module is configured to perform self-test by using built-in self-test logic, and outputs 1 mark pulse signal when 1 data error is detected in the process of executing the self-test;

The counter is connected with the built-in self-test module and is configured to receive the marking pulse signals and count the marking pulse signals in the self-test process.

2. The memory of claim 1, wherein the counter comprises a first counter and a second counter;

The counter is configured to add one to the count value of the first counter when the count value of the first counter does not reach the maximum value and each time 1 marking pulse signal is received;

And after the count value of the first counter reaches the maximum value, when the next marking pulse signal is received, adding one to the count value of the second counter and the count value of the first counter respectively.

3. The memory of claim 2, wherein the memory is configured to store, in the memory,

The counter is further configured to receive a first type pulse signal and a second type pulse signal, count the first type pulse signal by using the first counter, and count the second type pulse signal by using the second counter;

each first type pulse signal represents that data transmitted by an odd clock is found by data verification, each second type pulse signal represents that data transmitted by an even clock is found by data verification, and the phases of the system odd clock signal and the system even clock signal are opposite.

4. The memory of claim 3, wherein the counter further comprises a first logic unit; the input end of the first logic unit is used for receiving the marking pulse signal and the first type pulse signal, and the output end of the first logic unit is connected with the first counter;

The first logic unit is configured to output 1 first processing signal if 1 sign pulse signal or 1 first type pulse signal is received;

The first counter is configured to count the first processing signal.

5. The memory of claim 3, wherein,

The first counter is further configured to output a low-order carry signal in a first state if the count value of the first counter reaches a maximum value; if the count value of the carry signal does not reach the maximum value, outputting a carry signal in a second state;

The counter also comprises a gating unit and a second logic unit, wherein the input end of the gating unit receives the marking pulse signal and the carry signal, and the output end of the gating unit is used for outputting an intermediate pulse signal; the input end of the second logic unit receives the intermediate pulse signal and the second type pulse signal;

The gating unit is configured to output the marking pulse signal as an intermediate pulse signal when the carry signal is in a first state; or shielding the flag pulse signal when the carry signal is in the second state;

the second logic unit is connected with the gate control unit and is configured to receive the intermediate pulse signal and output the intermediate pulse signal as a second processing signal; or receiving the second type pulse signal and outputting the second type pulse signal as the second processing signal;

The second counter is configured to count the second processing signal.

6. The memory of claim 4, wherein the first type of pulse signal comprises a first result signal and a second result signal, three inputs of the first logic unit are respectively configured to receive the first result signal, the second result signal, and the flag pulse signal, and an output of the first logic unit is configured to output the first processing signal;

The first result signal characterizes that the low byte data transmitted by the odd clock is found by data verification, and the second result signal characterizes that the high byte data transmitted by the odd clock is found by data verification.

7. The memory of claim 5, wherein the second type pulse signal includes a third result signal and a fourth result signal, three inputs of the second logic unit are respectively configured to receive the third result signal, the fourth result signal, and the intermediate pulse signal, and an output of the second logic unit is configured to output the second processing signal;

The third result signal represents that the low-byte data transmitted by the even clock is found to be wrong through data verification, and the fourth result signal represents that the high-byte data transmitted by the even clock is found to be wrong through data verification.

8. The memory of claim 3, wherein,

The first counter is further configured to receive a first enable signal; wherein the first enable signal in an enable state is used to enable the first counter, the first enable signal being in an enable state during at least part of the self-test phase and at least part of the data verification phase;

The second counter is further configured to receive a second enable signal; wherein the second enable signal in an enable state is used to enable the second counter, the second enable signal being in an enable state during at least part of the self-test phase and at least part of the data verification phase.

9. The memory according to any of claims 2-8, wherein,

The counter is further configured to combine and output the count value of the first counter and the count value of the second counter to be final error values after the self-test is finished, so as to indicate the total number of errors detected in the self-test at this time.

10. The built-in self-test method is characterized by being applied to a memory comprising a counter, wherein the counter is used for counting error data bits obtained by data verification; the method comprises the following steps:

In the built-in self-test mode, self-test is performed by using built-in self-test logic; and

During the self-test, the counter is used to count the detected data errors.

11. The method of claim 10, wherein the counter comprises a first counter and a second counter; the counting of the detected data errors with a counter includes:

And if the count value of the first counter reaches the maximum value, adding one to the count value of the second counter and the count value of the first counter when the next data error is detected.

12. The method of claim 11, wherein the method further comprises:

Counting the first type of errors by using the first counter; counting the second type of errors by using the second counter;

13. The method according to claim 11 or 12, characterized in that the method further comprises:

14. A test system, wherein the test system comprises a memory controller and a memory, the memory controller and the memory are connected;

The memory controller is configured to send a self-test instruction to the memory;

The memory is configured to perform a self-test using built-in test logic after receiving the self-test instruction, and to count detected data errors using a counter during the self-test.