CN117528277A - Analog-to-digital conversion circuit and image sensor including the same - Google Patents

Abstract

An analog-to-digital conversion circuit and an image sensor including a comparator are provided. The analog-to-digital conversion circuit includes a counter and a comparator, the comparator including: a first P-type transistor having a gate connected to a first input node of the comparator; a second P-type transistor having a gate connected to a second input node of the comparator; a first N-type transistor having a gate connected to the first input node and a drain connected to the first P-type transistor; a second N-type transistor having a gate connected to the second input node and a drain connected to the second P-type transistor; and a transistor having a gate connected to the drain of the first N-type transistor and a source to which a ground voltage or a power supply voltage is applied.

Description

Analog-to-digital conversion circuit and image sensor including the same

Cross Reference to Related Applications

The present application is based on and claims priority from korean patent application No.10-2022-0098123 filed at the korean intellectual property office on month 8 and 5 of 2022 and korean patent application No.10-2022-0144622 filed at the korean intellectual property office on month 11 and 2 of 2022, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

The present inventive concept relates to an image sensor, and more particularly, to an analog-to-digital conversion circuit including a comparator and an image sensor including the same.

Background

The image sensor is used to capture a two-dimensional image or a three-dimensional image of an object. The image sensor may generate an image of an object by using a photoelectric conversion element that operates according to the intensity of light reflected from the object. CMOS image sensors have been widely used due to recent developments in Complementary Metal Oxide Semiconductor (CMOS) technology. Correlated Double Sampling (CDS) is used to remove reset noise of pixels of CMOS image sensors. Analog-to-digital conversion circuits using CDS technology are required to have high performance for image quality improvement.

Disclosure of Invention

The inventive concept provides an analog-to-digital conversion circuit including a comparator having a reduced noise level and an image sensor including the same.

According to some aspects of the inventive concept, there is provided an analog-to-digital conversion circuit comprising a counter and a comparator, wherein the comparator comprises: a first P-type transistor having a gate connected to a first input node of the comparator; a second P-type transistor having a gate connected to a second input node of the comparator; a first N-type transistor having a gate connected to the first input node and a drain connected to the first P-type transistor; a second N-type transistor having a gate connected to the second input node and a drain connected to the second P-type transistor; and a transistor having a gate connected to the drain of the first N-type transistor and a source to which a ground voltage or a power supply voltage is applied.

According to some aspects of the inventive concept, there is provided an image sensor including: a pixel array including a plurality of pixels; a ramp generator configured to generate a ramp signal; and an analog-to-digital conversion circuit configured to convert a pixel signal output from the pixel array into a digital signal, the analog-to-digital conversion circuit including a comparator and a counter, wherein the comparator includes: a first P-type transistor having a gate connected to a first input node, the first input node receiving the ramp signal; a second P-type transistor having a gate connected to a second input node, the second input node receiving the pixel signal; a first N-type transistor having a gate connected to the first input node; a second N-type transistor having a gate connected to the second input node; and a transistor having a gate connected to a drain of the first N-type transistor and a source to which a ground voltage or a power supply voltage is applied.

According to some aspects of the inventive concept, there is provided an image sensor including: a pixel array having a plurality of pixels connected to a plurality of column lines; a ramp generator configured to generate a ramp signal; and a plurality of analog-to-digital conversion circuits, each including a first comparator and a second comparator configured to generate a comparison result signal by comparing a pixel signal output via a corresponding column line among the plurality of column lines with the ramp signal, wherein the first comparator includes: a first P-type transistor and a first N-type transistor, the first P-type transistor and the first N-type transistor receiving the ramp signal; a second P-type transistor and a second N-type transistor, the second P-type transistor and the second N-type transistor receiving the pixel signal; a first output node through which a result of comparison of the pixel signal and the ramp signal is output as a first output signal; a second output node through which a second output signal is output; and a transistor having a gate connected to the second output node and a source to which a ground voltage or a power supply voltage is applied.

Drawings

Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram illustrating an image sensor according to some example embodiments;

FIG. 2 is a block diagram illustrating a pixel included in an image sensor and a column parallel analog-to-digital conversion circuit (ADC) connected to the pixel, according to some example embodiments;

fig. 3 and 4 are circuit diagrams illustrating examples of a first comparator included in an ADC according to some example embodiments;

fig. 5 is a circuit diagram illustrating an example of a second comparator included in an ADC according to some example embodiments;

fig. 6 is a timing diagram showing signals input to the comparison circuit shown in fig. 2 to explain the operation of the ADC shown in fig. 2;

fig. 7 is a circuit diagram illustrating an example of a first comparator included in an ADC according to some example embodiments;

fig. 8A and 8B are timing charts showing signals input to the comparison circuit of the first comparator shown in fig. 7 to explain the operation of the ADC shown in fig. 2;

FIG. 9 is a block diagram illustrating an ADC of an image sensor according to some example embodiments;

fig. 10 is a diagram illustrating a ramp signal provided to an ADC of an image sensor according to some example embodiments;

FIG. 11 is a diagram illustrating a ramp signal provided to an ADC according to some example embodiments;

fig. 12 is a circuit diagram illustrating a pixel according to some example embodiments;

FIG. 13 is a block diagram illustrating an image sensor according to some example embodiments;

fig. 14 is a schematic diagram illustrating an image sensor according to some example embodiments.

Detailed Description

Hereinafter, example embodiments will be described with reference to the accompanying drawings.

Fig. 1 is a block diagram illustrating an image sensor 100 according to some example embodiments.

The image sensor 100 may be included in an electronic device having an image sensing function or a light sensing function. For example, the image sensor 100 may be included in an electronic device such as a camera, a smart phone, a wearable device, an internet of things (IoT) device, a tablet Personal Computer (PC), a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), and/or a navigation device. In addition, the image sensor 100 may be included in an electronic device that is part of a vehicle, a piece of furniture, a manufacturing facility, a door, a measurement device, or the like.

The image sensor 100 may include a pixel array 110, a row driver 120, an analog-to-digital converter (ADC) 130, a ramp generator 160, a timing generator 170, and a buffer 180.

The pixel array 110 includes a plurality of pixels 111 arranged in a matrix form and each connected to a plurality of row lines and a plurality of column lines COL. Each pixel 111 includes a photosensitive element. For example, the photosensitive device may include a photodiode, a phototransistor, a photogate, and/or a pinned photodiode. Each pixel 111 may include at least one photosensitive element, and in some example embodiments, each pixel 111 may include a plurality of photosensitive elements.

Each pixel 111 may sense light by using a photosensitive element, and may convert the sensed light into an electrical pixel signal PXS (refer to fig. 2). The pixel signal PXS may include a reset signal generated according to a reset operation of each pixel 111 and an image signal generated according to a photosensitive operation of each pixel 111.

Each pixel 111 may sense light in a particular spectral region. For example, the pixels 111 may include red pixels each configured to convert light in a red spectral region into an electrical signal, green pixels each configured to convert light in a green spectral region into an electrical signal, and blue pixels each configured to convert light in a blue spectral region into an electrical signal. A color filter configured to transmit light in a specific spectral region may be disposed over each pixel 111.

The timing generator 170 may output control signals or clock signals to the row driver 120, the ADC 130, and the ramp generator 160 to control operations or timings of the row driver 120, the ADC 130, and the ramp generator 160.

The row driver 120 may drive the pixel array 110 in row units. The row driver 120 may decode a row control signal (e.g., an address signal) generated by the timing generator 170, and may select at least one of the row lines of the pixel array 110 in response to the decoded row control signal. For example, the row driver 120 may generate a row selection signal. The pixel array 110 may output the pixel signal PXS through a row line selected by a row selection signal supplied from the row driver 120.

The ADC 130 may convert the pixel signal PXS, which is an analog signal received from the pixel array 110, into a digital signal. The ADC 130 may include a comparison block 140 and a counter block 150.

The comparison block 140 may include a plurality of comparison Circuits (COMP) 141, and each comparison circuit 141 may be connected to at least one corresponding column line COL among the column lines COL. Each of the comparison circuits 141 may receive the RAMP signal RAMP from the RAMP generator 160 and may compare the RAMP signal RAMP with the pixel signal PXS output from the pixel 111 connected to the column line COL. The counter block 150 may include a plurality of Counters (CNTs) 151.

That is, each of the comparison circuits 141 may receive the pixel signal PXS through at least one corresponding column line COL among the column lines COL, and may receive the RAMP signal RAMP from the RAMP generator 160, and may output a comparison result signal by comparing the pixel signal PXS and the RAMP signal RAMP with each other. Each of the comparison circuit 141 and the counter 151 may be referred to as a Correlated Double Sampling (CDS) circuit capable of CDS, and in particular, may be referred to as a column parallel CDS circuit. The pixel signal PXS output from the pixel 111 may have a deviation caused by a pixel specific characteristic of the pixel 111 and/or a deviation caused by a different logic characteristic for outputting the pixel signal from the pixel 111. In order to compensate for such deviation between the pixel signals PXS, CDS may be performed by calculating a reset component (or reset signal) and an image component of each pixel signal PXS and extracting a difference between the reset component and the image component as an effective signal component.

Each of the comparison circuits 141 may include a first comparator configured to compare the pixel signal PXS and the RAMP signal RAMP with each other and a second comparator configured to amplify and output an output of the first comparator. In this case, the first comparator may have a noise reduction circuit configuration, and thus the comparison circuit 141 may reduce noise and prevent or reduce degradation of the quality of the image data IDTA in a low-illuminance environment.

The RAMP generator 160 may generate a RAMP signal RAMP. The RAMP generator 160 may generate a RAMP signal RAMP in response to the RAMP control signal CTRP supplied from the timing generator 170. The ramp control signal CTRP may include a ramp enable signal and a mode signal. When the RAMP enable signal is activated, the RAMP generator 160 may generate a RAMP signal RAMP having a slope set based on the mode signal. For example, the RAMP generator 160 may generate the RAMP signal RAMP decreasing with a constant slope as described later with reference to fig. 6, or the RAMP generator 160 may generate the RAMP signal RAMP increasing with a constant slope as described with reference to fig. 8A and 8B.

The counters 151 may be respectively connected to output terminals of the comparison circuits 141 so that counting may be performed based on an output signal (e.g., a comparison result signal) of each of the comparison circuits 141. The counter control signal CTCS may include a counter clock signal, a counter reset signal for controlling a reset operation of the counters 151, and an inversion signal for inverting an internal bit of each counter 151. The counter block 150 may count the comparison result signal according to a counter clock signal, and may output the counted result as a digital signal.

The counter 151 may include an up/down counter and a bit-wise reverse counter. In this case, the bit-wise reverse counter may perform operations similar to those of the up/down counter. For example, the bitwise-inversion counter may have a function of performing only up-counting, and a function of inverting all internal bits of the bitwise-inversion counter in response to a specific input signal to calculate a complement of 1. After the bit-wise reverse counter performs the reset count, the bit-wise reverse counter may return the complement of 1, i.e., a negative value, by inverting the result of the reset count.

However, the image sensor 100 of the present disclosure is not limited thereto. The image sensor 100 may further include a count code generator configured to perform a count encoding operation under the control of the timing generator 170. The count code generator may be implemented as a gray code generator, and may generate a plurality of code values having a resolution according to a set number of bits as the count code. For example, the counter 151 may include a latch circuit and an arithmetic circuit, wherein the latch circuit may receive the count number from the count code generator and the output signal from the comparison block 140, and may latch a code value of the count code at a time when the level of the comparison signal transitions. The arithmetic circuit may calculate the reset value and the image signal value to generate an image signal value from which the reset level of the pixel 111 is removed. The counter block 150 may output the image signal value from which the reset level is removed as the pixel value.

The buffer 180 may temporarily store the digital signal output from the ADC 130, and then may read out, amplify, and output the digital signal. The buffer 180 may include a column memory block 181 and a sense amplifier 182, and the column memory block 181 may include a plurality of memories 183. The memory 183 may temporarily store the digital signal output from the counter 151, and may output the digital signal to the sense amplifier 182, and the sense amplifier 182 may sense and amplify the digital signal output from the memory 183. The sense amplifier 182 may output the amplified digital signal as image data IDTA.

Fig. 2 is a block diagram illustrating a pixel 111 of the image sensor 100 and a column-parallel ADC 131 connected to the pixel 111 according to some example embodiments. For convenience of explanation, the following description will be given together with the pixels 111 of some example embodiments.

Referring to fig. 2, the pixel 111 may include a photodiode PD, a transfer transistor TX, a floating diffusion node FD, a reset transistor RX, a driving transistor DX, and a selection transistor SX. The photodiode PD may be replaced with another photoelectric conversion element.

The photodiode PD can generate photo-charges according to the intensity of incident light. The transfer transistor TX may transfer the photo-charge generated by the photodiode PD to the floating diffusion FD according to a transfer control signal TS output from the row driver 120 (see fig. 1). The driving transistor DX may amplify the photo-charge according to the potential of the photo-charge accumulated in the floating diffusion node FD and transfer the photo-charge to the selection transistor SX. The drain of the selection transistor SX may be connected to the source of the driving transistor DX, and the pixel signal PXS may be output to the column line COL according to the selection signal SEL output from the row driver 120. The reset transistor RX may reset the floating diffusion node FD to the power supply voltage VDD according to a reset control signal RS supplied from the row driver 120.

Fig. 2 shows that the pixel 111 has a 4-transistor (4T) structure including one photodiode PD and four transistors TX, RX, DX, and SX. However, the pixel 111 of the image sensor 100 of the present inventive concept is not limited to the structure shown in fig. 2. The pixel 111 may have a 3-transistor (3T) structure including one photodiode PD and three transistors selected from the transfer transistor TX, the reset transistor RX, the driving transistor DX, and the selection transistor SX.

The column parallel ADC 131 may include a comparison circuit 141 and a counter 151. For ease of illustration, fig. 2 shows one comparison circuit 141 and one counter 151 included in the column-parallel ADC 131 connected to one column line COL. However, as described with reference to fig. 1, the ADC 130 may include a plurality of column-parallel ADCs 131, and the plurality of column-parallel ADCs 131 include a plurality of comparison circuits 141 and a plurality of counters 151 connected to a plurality of column lines COL.

The comparison circuit 141 may include a first comparator 210, a second comparator 220, and capacitors C1 and C2. The first comparator 210 may include a differential amplifier, and the differential amplifier may be implemented as an Operational Transconductance Amplifier (OTA), an operational amplifier, or the like.

The first input node of the first comparator 210 may receive the RAMP signal RAMP as the first input signal INP, and the second input node of the first comparator 210 may receive the pixel signal PXS as the second input signal INN. The first comparator 210 may compare the pixel signal PXS and the RAMP signal RAMP received through the capacitors C1 and C2, and output the comparison result as an output signal OS1P through the first output node OP.

The second comparator 220 may amplify the output signal OS1P output from the first comparator 210 or invert the output signal OS1P output from the first comparator 210. For example, the second comparator 220 may be implemented as an amplifier. For example, the second comparator 220 may include a differential amplifier or an inverter. The output signal OS2 output from the second comparator 220 may be supplied to the counter 151 as a comparison result signal.

The comparison circuit 141 may be initialized in response to the auto-zero signal in the auto-zero period before performing the comparison operation. For example, the auto-zero signal may include a first auto-zero signal AZ1 (refer to fig. 4) input to the first comparator 210 and a second auto-zero signal AZ2 (refer to fig. 5) input to the second comparator 220.

The counter 151 may output the digital signal DS by counting the comparison result signal (i.e., the output signal OS2 of the second comparator 220) based on the count clock signal CLK. The counter 151 may transmit the digital signal DS to the buffer 180 (refer to fig. 1).

Fig. 3 and 4 are circuit diagrams illustrating first comparators 210 and 210a as examples that may be included in the ADC 130 according to example embodiments. The first output signal OS1P shown in fig. 3 and 4 may be the same as the output signal OS1P shown in fig. 2.

Referring to fig. 3, the first comparator 210 may include a plurality of transistors MP11, MP12, MN11, MN12, and MPX and a current source CS. The first comparator 210 may include a first P-type transistor MP11, a second P-type transistor MP12, a first N-type transistor MN11, a second N-type transistor MN12, and a transistor MPX. The transistor MPX may be a P-type transistor. The first comparator 210 may be referred to as an OTA having a 6 transistor (6T) structure.

In some example embodiments, the current source CS may be implemented with an N-type metal oxide semiconductor (NMOS) transistor (i.e., an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET)). The node of the current source CS may be connected to a ground voltage and the current source CS may generate the bias current IS.

The gates of the first and second N-type transistors MN11 and MN12 may receive differential inputs (e.g., the first and second input signals INP and INN), respectively. The gates of the first and second P-type transistors MP11 and MP12 may receive differential inputs (e.g., the first and second input signals INP and INN), respectively. For example, the RAMP signal RAMP may be received as the first input signal INP, and the pixel signal PXS may be received as the second input signal INN. The first N-type transistor MN11, the second N-type transistor MN12, the first P-type transistor MP11, and the second P-type transistor MP12 may generate a differential current according to a level difference between the first input signal INP and the second input signal INN.

The source of the first P-type transistor MP11 and the source of the second P-type transistor MP12 may be connected to a first node (e.g., drain) of the transistor MPX, and the power supply voltage VDD may be applied to a second node (e.g., source) of the transistor MPX. The drain of the first P-type transistor MP11 may be connected to the second output node OPN outputting the second output signal OS1N, and the drain of the second P-type transistor MP12 may be connected to the first output node OP outputting the first output signal OS 1P. A gate of the transistor MPX may be connected to the second output node OPN.

The source of the first N-type transistor MN11 and the source of the second N-type transistor MN12 may be connected to a current source CS. The drain of the first N-type transistor MN11 may be connected to the second output node OPN outputting the second output signal OS1N, and the drain of the second N-type transistor MN12 may be connected to the first output node OP outputting the first output signal OS 1P.

When the first input signal INP is the same as the second input signal INN, the current flowing through the first N-type transistor MN11 and the first P-type transistor MP11 may be the same as the current flowing through the second N-type transistor MN12 and the second P-type transistor MP 12. When the first input signal INP and the second input signal INN are different from each other, the current flowing through the first N-type transistor MN11 and the first P-type transistor MP11 may be different from the current flowing through the second N-type transistor MN12 and the second P-type transistor MP 12. The sum of currents flowing through the first N-type transistor MN11 and the second N-type transistor MN12 may be equal to the bias current IS.

The first and second output signals OS1P and OS1N may be determined based on the amounts of currents flowing through the first and second N-type transistors MN11 and MN 12. When the level of the first input signal INP is higher than the level of the second input signal INN, the amount of current flowing in the first N-type transistor MN11 may be greater than the amount of current flowing in the second N-type transistor MN12, so that the level of the first output signal OS1P may increase and the level of the second output signal OS1N may decrease.

In the inventive concept, a magnitude V of noise (e.g., thermal noise) occurring in the second input signal INN due to the first comparator 210 ² Can be calculated by the following equation I. In equation 1, k refers to boltzmann constant, and T refers to temperature. In addition, γ refers to a constant related to the characteristics of the transistor of the first comparator 210. In other words, γ is related to the manufacturing process of the first comparator 210. In addition, BW refers to a value determined by bandwidth. In addition, in the case of the optical fiber,g _m,in refers to the transconductance of the first N-type transistor MN11 and the second N-type transistor MN12, and g _m,in2 Refers to the transconductance of the first P-type transistor MP11 and the second P-type transistor MP 12.

[ equation 1]

Unlike the first comparator 210 of the inventive concept, since the comparator of the comparative example has a current mirror structure, the magnitude V of noise occurring in the second input signal INN ² Can be calculated by the following equation 2. In equation 2, g _m,in Refers to the transconductance of the N-type transistor of the comparator of the comparative example, and g _m,l Refers to the transconductance of the P-type transistor of the comparator of the comparative example.

[ equation 2]

Unlike the comparator of the comparative example, the first comparator 210 of the present inventive concept does not have a current mirror structure (i.e., does not have a mirror load transistor). In addition, the first comparator 210 of the present inventive concept may include a P-type transistor to which the first input signal INP and the second input signal INN are input. That is, the first comparator 210 of the present inventive concept may include a first P-type transistor MP11 and a second P-type transistor MP12. Accordingly, the first comparator 210 of the inventive concept may reduce noise occurring in the second input signal INN, and may prevent or reduce degradation of image data in a low illumination environment, as compared to the comparative example.

Referring to fig. 4, the first comparator 210a may include a plurality of transistors MP11, MP12, MN11, MN12, and MPX and a current source CS. In addition, the first comparator 210a may further include a plurality of switching circuits SW1 and SW2. When the switching circuits SW1 and SW2 are turned on, an input node to which the second input signal INN is input may be connected to the first output node OP to which the first output signal OS1P is output, and an input node to which the first input signal INP is input may be connected to the second output node OPN to which the second output signal OS1N is output.

For example, the switching circuits SW1 and SW2 may receive a first auto-zero signal AZ1 for turning on the switching circuits SW1 and SW2 in an auto-zero period. The first auto-zero signal AZ1 may be received from the timing generator 170 (refer to fig. 1). When the switching circuits SW1 and SW2 are turned on, the voltage levels of the first input signal INP, the second input signal INN, the first output signal OS1P, and the second output signal OS1N may become equal to each other, and at this time, the voltage levels of the first input signal INP, the second input signal INN, the first output signal OS1P, and the second output signal OS1N may be referred to as auto-zero voltages. In addition, for example, in a comparison operation period in which the first comparator 210a performs a comparison operation, the switch circuits SW1 and SW2 may be turned off.

Fig. 5 is a circuit diagram illustrating a second comparator 220 as an example that may be included in the ADC 130 according to some example embodiments. The first output signal OS1P shown in fig. 5 may be the same as the output signal OS1P shown in fig. 2.

Referring to fig. 5, the second comparator 220 may include a plurality of transistors MP2 and MN2, a switching circuit SW2, and a capacitor CA. The first output node OP of the first comparator 210 may be connected to the gate of the P-type transistor MP2 of the second comparator 220, and the first output signal OS1P of the first comparator 210 may be input to the second comparator 220 as an input signal. The power supply voltage VDD may be applied to the source of the P-type transistor MP2, and the drain of the P-type transistor MP2 may be connected to an output node to which the output signal OS2 of the second comparator 220 is output.

The drain of the N-type transistor MN2 may be connected to the output node of the second comparator 220, and a ground voltage may be applied to the source of the N-type transistor MN 2. That is, the P-type transistor MP2 and the N-type transistor MN2 may be connected in series with each other. The N-type transistor MN2 may operate as a current source and may generate a bias current based on a voltage at a node of the capacitor CA.

Fig. 6 is a timing chart showing signals input to the comparison circuit 141 shown in fig. 2 to explain the operation of the column parallel ADC 131 shown in fig. 2.

Referring to fig. 2 and 6, a period from time T0 to time T1 may be defined as an auto-zero period, and a period from time T1 to time T8 may be defined as a comparison operation period. The auto-zero signal AZS (e.g., the first auto-zero signal AZ1 shown in fig. 4 and the second auto-zero signal AZ2 shown in fig. 5) may be active from time T0 to time T1, and the comparison circuit 141 may be initialized in response to the auto-zero signal AZS. The input nodes and/or the output nodes of the first comparator 210 and the second comparator 220 may have the same level.

For digital conversion of the reset signal, an offset may be applied to the RAMP signal RAMP at time T2, and then the RAMP signal RAMP may decrease from time T3 to time T5. The counter 151 may count the count clock signal CLK during a period from time T3 to time T4 in which the polarity of the output signal OS2 of the second comparator 220 changes.

After the digital conversion of the reset signal is completed, an offset may be applied again to the RAMP signal RAMP at time T5 to convert the image signal into a digital signal at time T5. After time T5, the transfer transistor TX may be turned on, and the second input signal INN to the first comparator 210 may change due to the charge accumulated in the photodiode PD during the exposure time. In fig. 6, for ease of illustration, it is assumed that the second input signal INN to the first comparator 210 is unchanged because the photo-charges generated by the photodiode PD are not accumulated.

For digital conversion of the image signal, the RAMP signal RAMP may decrease during a period from time T6 to time T8. The counter 151 may count the count clock signal CLK during a period from time T6 to time T7 in which the polarity of the output signal OS2 of the second comparator 220 changes. To perform the next read operation, an offset may be applied again to the RAMP signal RAMP at time T8.

When the digital conversion of the image signal of a specific pixel is completed, the column parallel ADC 131 may be initialized to perform correlated double sampling for the next pixel. The variation of the signals shown in fig. 6 is an example, and the timing of each signal may be modified according to a method of implementing the column parallel ADC 131 (e.g., the structures of the first comparator 210 and the second comparator 220).

Fig. 7 is a circuit diagram illustrating a first comparator 210b as an example that may be included in the ADC 130 according to some example embodiments. The first output signal OS1P shown in fig. 7 may be the same as the output signal OS1P shown in fig. 2.

Referring to fig. 7, the first comparator 210b may include a plurality of transistors MP11, MP12, MN11, MN12, and MNX and a current source CS'. The first comparator 210b may include a first P-type transistor MP11, a second P-type transistor MP12, a first N-type transistor MN11, a second N-type transistor MN12, and a transistor MNX. The transistor MNX may be an N-type transistor. The first comparator 210b may be referred to as an OTA having a 6T structure.

In some example embodiments, the current source CS' may be implemented with a PMOS transistor (i.e., a P-type MOSFET). The current source CS 'may be connected to the power supply voltage VDD and may generate the bias current IS'.

The gate of the first N-type transistor MN11 and the gate of the first P-type transistor MP11 may receive the first input signal INP, and the gate of the second N-type transistor MN12 and the gate of the second P-type transistor MP12 may receive the second input signal INN.

The source of the first P-type transistor MP11 and the source of the second P-type transistor MP12 may be connected to a current source CS'. The drain of the first P-type transistor MP11 may be connected to the second output node OPN, and the drain of the second P-type transistor MP12 may be connected to the first output node OP.

The source of the first N-type transistor MN11 and the source of the second N-type transistor MN12 may be connected to a first node (e.g., drain) of the transistor MNX, and a ground voltage may be applied to a second node (e.g., source) of the transistor MNX. The drain of the first N-type transistor MN11 may be connected to the second output node OPN, and the drain of the second N-type transistor MN12 may be connected to the first output node OP.

The first comparator 210b may further include a plurality of switching circuits. Each of the switching circuits may switch between an input node to which the second input signal INN is input and the first output node OP to which the first output signal OS1P is output, or may switch between an input node to which the first input signal INP is input and the second output node OPN to which the second output signal OS1N is output. When the switching circuit is turned on, an input node to which the second input signal INN is input may be connected to the first output node OP to which the first output signal OS1P is output, and an input node to which the first input signal INP is input may be connected to the second output node OPN to which the second output signal OS1N is output.

Fig. 8A and 8B are timing charts showing signals input to a comparison circuit including the first comparator 210a shown in fig. 7 to explain the operation of the column parallel ADC 131 shown in fig. 2. Fig. 8A and 8B illustrate an example of the RAMP signal RAMP described with reference to fig. 1 to explain an operation of the first comparator 210a when the comparator 210a receives the first RAMP signal and the second RAMP signal as inverted RAMP signals.

Referring to fig. 2 and 8A, for digital conversion of an image signal, an offset may be applied to the ramp signal RAMPa at time T2a, and then the ramp signal RAMPa may rise during a period from time T3a to time T5 a. The counter 151 may count the count clock signal CNT during a period from time T3a to time T4a (zero-crossing time), where the voltage level of the ramp signal rapa is equal to the voltage level of the pixel signal PXS at time T4 a.

After the digital conversion of the image signal is completed, an offset may be applied again to the ramp signal ramp in a period from time T5a to time T6 a. In order to convert the reset signal into a digital signal, the ramp signal RAMPa may rise from time T6a to time T8 a. The counter 151 may count the count clock signal CNT during a period from time T6a to time T7a, where the voltage level of the ramp signal rapa is equal to the voltage level of the pixel signal PXS at time T7 a.

Referring to fig. 2 and 8B, for digital conversion of the reset signal, a first offset may be applied to the ramp signal ramp B at time T2B, and then the ramp signal ramp B may rise during a period from time T3B to time T5B. The counter 151 may count the count clock signal CNT during a period from time T3b to time T4b (zero-crossing time), where the voltage level of the ramp signal RAMPb is equal to the voltage level of the pixel signal PXS at time T4 b.

After the digital conversion of the reset signal is completed, a second offset may be applied to the ramp signal RAMPb in a period from time T5b to time T6 b. In this case, the voltage level of the ramp signal RAMPb at the time T5b when the second offset is applied may be lower than the voltage level of the ramp signal RAMPb at the time T2b when the first offset is applied.

In order to convert the image signal into a digital signal, the ramp signal RAMPb may rise during a period from time T6b to time T8 b. The counter 151 may count the count clock signal CNT during a period from time T6b to time T7b, where the voltage level of the ramp signal RAMPb is equal to the voltage level of the pixel signal PXS at time T7 b.

Fig. 9 is a block diagram illustrating a column-parallel ADC 131' that may be included in the image sensor 100 according to some example embodiments. In fig. 9 and 2, the same reference numerals denote the same elements, and a repetitive description thereof will be omitted.

Referring to fig. 9, the column parallel ADC 131' may include a first comparator 210, a second comparator 220, a counter 151, first to fourth capacitors C1, C2, C3 and C4, and switching circuits SWA1 and SWA2. The ADC 30 described with reference to fig. 1 may include a plurality of column-parallel ADCs 131'. The first comparator 210 may be one of the first comparators 210, 210a, and 210b described with reference to fig. 3, 4, and 7.

The first capacitor C1 may be connected to the first input node of the first comparator 210, and the first comparator 210 may receive the RAMP signal RAMP as the first input signal INP through the first capacitor C1. The second capacitor C2 may be connected to the second input node of the first comparator 210, and the first comparator 210 may receive the pixel signal PXS as the second input signal INN through the second capacitor C2.

The third capacitor C3 may be connected in parallel to the first capacitor C1 according to a switching operation of the first switching circuit SWA 1. The first switching circuit SWA1 may connect a node of the third capacitor C3 to a node of the first capacitor C1 or a ground voltage in response to the first switching signal SWS 1. Accordingly, the capacitance of the capacitor connected to the first input node of the first comparator 210 may vary according to the switching operation of the first switching circuit SWA 1.

In addition, according to the switching operation of the second switching circuit SWA2, the fourth capacitor C4 may be connected in parallel to the second capacitor C2. The second switching circuit SWA2 may connect a node of the fourth capacitor C4 to a node of the second capacitor C2 or a ground voltage in response to the second switching signal SWS2. Accordingly, the capacitance of the capacitor connected to the second input node of the first comparator 210 may vary according to the switching operation of the second switching circuit SWA 2. The first and second switching signals SWS1 and SWS2 may be received from the timing generator 170 (refer to fig. 1).

The timing generator 170 (e.g., from fig. 1) may provide the first and second switching signals SWS1 and SWS2 to the column parallel ADC 131' according to an analog gain of the first comparator 210. For example, in a high-light environment, the timing generator 170 may relatively reduce the analog gain (e.g., about 1 to about 1.99 times). In this case, the timing generator 170 may attenuate the first and second input signals INP and INN by generating the first and second switching signals SWS1 and SWS2 to connect the nodes of the first and second switching circuits SWA1 and SWA2 to the ground voltage. Conversely, for example, in a low-light environment, the timing generator 170 may relatively increase the analog gain (e.g., about 2 to about 16 times). In this case, the timing generator 170 may generate the first switching signal SWS1 to connect the first capacitor C1 and the third capacitor C3 in parallel with each other, and generate the second switching signal SWS2 to connect the second capacitor C2 and the fourth capacitor C4 in parallel with each other.

Fig. 10 is a diagram illustrating ramp signals provided to column-parallel ADCs 131' that may be included in image sensor 100, according to some example embodiments. Fig. 11 is a diagram illustrating a ramp signal provided to column-parallel ADC 131' according to some example embodiments.

Referring to fig. 9 to 11, the RAMP generator 160' may generate the first RAMP signal RAMP1 and/or the second RAMP signal RAMP2. In some example embodiments, the RAMP generator 160' may include a current source and a resistor, and may generate the first RAMP signal RAMP1 or the second RAMP signal RAMP2 by changing an amount of current output from the current source or resistance of the resistor. Alternatively, in some example embodiments, the RAMP generator 160' may include a first RAMP generator configured to generate the first RAMP signal RAMP1 and a second RAMP generator configured to generate the second RAMP signal RAMP2.

The first RAMP signal RAMP1 and the second RAMP signal RAMP2 may have different slopes in a period in which the image signal and the reset signal are sampled. For example, the slope SL1 of the first RAMP signal RAMP1 may be greater than the slope SL2 of the second RAMP signal RAMP2.

The image sensor 100 of the present inventive concept can adjust the gain of the ramp voltage according to the external environment. The "gain" of the ramp voltage may refer to the degree of amplification of the signal. That is, the larger the slope of the ramp voltage, the smaller the gain; and the smaller the slope of the ramp voltage, the greater the gain. As the slope of the ramp voltage increases, the number of times the counter 151 counts may decrease, and thus the magnitude of the digital signal DS may decrease. In contrast, as the slope of the ramp voltage decreases, the number of times the counter 151 counts may increase, and thus the magnitude of the digital signal DS may increase.

Accordingly, in a high illuminance environment, the first RAMP signal RAMP1 having a relatively small gain may be supplied to the column parallel ADC 131'. When the first RAMP signal RAMP1 is supplied to the column parallel ADC 131', the node of the first switch circuit SWA1 and the node of the second switch circuit SWA2 may be connected to a ground voltage to attenuate the first input signal INP and the second input signal INN. Conversely, in a low illumination environment, the second RAMP signal RAMP2 having a relatively large gain may be provided to the column-parallel ADC 131'. When the second RAMP signal RAMP2 is supplied to the column parallel ADC 131', the first capacitor C1 and the third capacitor C3 may be connected in parallel with each other, and the second capacitor C2 and the fourth capacitor C4 may be connected in parallel with each other.

Fig. 12 is a circuit diagram illustrating a pixel according to some example embodiments. In fig. 12 and 2, the same reference numerals denote the same elements, and a repetitive description thereof will be omitted.

Referring to fig. 12, the pixel 111' may include a photodiode PD, a transfer transistor TX, a floating diffusion FD, a reset transistor RX, a driving transistor DX, and a selection transistor SX. In addition, the pixel 111' may include a gain control transistor CGX (also referred to as a conversion gain control transistor CGX) and a capacitor C _L . The gain control transistor CGX may operate in response to a gain control signal CGS. Capacitor C _L May be a passive capacitor having a fixed capacitance or a variable capacitance, a capacitor formed by or connected to the source/drain of the gain control transistor CGX, or a parasitic capacitor formed by another capacitor that may be connected to the source/drain of the gain control transistor CGX.

The photodiode PD may generate electric charges according to the intensity of light, and thus the amount of electric charges generated by the photodiode PD may vary according to an image capturing environment (e.g., a low-illuminance environment or a high-illuminance environment). For example, in a high illuminance environment, the amount of charge generated by the photodiode PD may reach the full well capacity (FWC, full well capacity) of the photodiode PD. However, in a low-illuminance environment, the amount of charge generated by the photodiode PD may not reach the FWC of the photodiode PD.

The reset transistor RX may be turned on in response to a reset control signal RS applied to a gate of the reset transistor RX to reset the floating diffusion node FD based on the power supply voltage VDD. In this case, the gain control transistor CGX may be turned on together with the reset transistor RX in response to the gain control signal CGS received through the gate of the gain control transistor CGX, and thus the power supply voltage VDD may be applied to the floating diffusion node FD to reset the floating diffusion node FD.

The transfer transistor TX can be responsive toTurned on in response to a transfer control signal TS applied to the gate of the transfer transistor TX to transfer the charge generated by the photodiode PD to the floating diffusion FD, and thus the charge may be accumulated in the floating diffusion FD. That is, a parasitic capacitor may be formed at the floating diffusion node FD, and charges may be accumulated in the parasitic capacitor formed by the floating diffusion node FD. In addition, when the gain control transistor CGX is turned on, charge can be transferred between the floating diffusion node FD and the capacitor C _L Accumulation in the parasitic capacitor formed.

The charge accumulated in the floating diffusion node FD may be converted into a voltage. The conversion gain (the unit of the conversion gain may be, for example, μv/e) is determined by the capacitance of the floating diffusion node FD, and may be inversely proportional to the capacitance of the floating diffusion node FD. The conversion gain may be decreased when the capacitance of the floating diffusion node FD is increased, and may be increased when the capacitance of the floating diffusion node FD is decreased.

The gain control transistor CGX may be turned on or off based on a gain control signal CGS received through a gate of the gain control transistor CGX. Capacitor C when the gain control transistor CGX is turned on _L Is connected to the floating diffusion node FD, and the floating diffusion node FD has parasitic capacitance and is formed by a capacitor C _L The resulting capacitance, so that the total capacitance can be increased. The conversion gain when the gain control transistor CGX is turned off may be larger than the conversion gain when the gain control transistor CGX is turned on. The state in which the gain control transistor CGX is turned off may be referred to as a High Conversion Gain (HCG) mode, and the state in which the gain control transistor CX is turned on may be referred to as a Low Conversion Gain (LCG) mode.

As described above, the pixel 111' may operate in one of the HCG mode and the LCG mode according to whether the gain control transistor CGX is turned on or turned off. In a low illuminance condition, the HCG mode may be selected, and thus the low light detection performance of the image sensor 100 may be improved. In addition, under high illumination conditions, LCG mode may be selected. In this case, the capacitance of the floating diffusion node FD of the pixel 111' is large, and thus the FWC may increase. Therefore, the high light detection performance of the image sensor 100 can be improved.

As described above, the pixel 111' has a Dual Conversion Gain (DCG) to sense low-intensity light and high-intensity light, and thus the operation range (e.g., dynamic range) of the image sensor 100 may be widened (or increased) based on the operation mode. In some example embodiments, the pixels 111' may continuously operate in the HCG mode and the LCG mode during the readout period, and thus, the processor receiving the image data IDTA (refer to fig. 1) from the image sensor 100 (refer to fig. 1) may combine the first image obtained in the HCG mode with the second image obtained in the LCG mode to generate an image having a High Dynamic Range (HDR). The pixel 111' having DCG shown in fig. 12 is only an example, and the configuration of the pixel may be modified in various ways.

Referring to fig. 9 and 12, in a high illumination environment, the pixel 111' may operate in an LCG mode, and the node of the first and second switching circuits SWA1 and SWA2 may be connected to a ground voltage to attenuate the first and second input signals INP and INN. In addition, in a low illumination environment, the pixel 111' may operate in an HCG mode in which the first capacitor C1 and the third capacitor C3 are connected in parallel with each other, and the second capacitor C2 and the fourth capacitor C4 are connected in parallel with each other.

Fig. 13 is a block diagram illustrating an image sensor 100 according to some example embodiments.

Referring to fig. 1 and 13, the image sensor 100 (refer to fig. 1) may further include a multiplexer MUX. The multiplexer MUX may connect the plurality of column lines COL to the ADC 130. The column line COL may include a first column line COL1 and a second column line COL2, and the column parallel ADC 131 may include a first column parallel ADC 131a and a second column parallel ADC 131b.

For example, the first multiplexer 191 may connect the first column line COL1 to the first column-parallel ADC 131a, and may connect the second column line COL2 to the first column-parallel ADC 131a. In addition, for example, the second multiplexer 192 may connect the second column line COL2 to the second column-parallel ADC 131b, and may connect the first column line COL1 to the second column-parallel ADC 131b. The first column-parallel ADC 131a and the second column-parallel ADC 131b may each include at least one first comparator selected from the group consisting of the first comparator 210 described with reference to fig. 3, the first comparator 210a described with reference to fig. 4, and the first comparator 210b described with reference to fig. 7. The first column-parallel ADC 131a and the second column-parallel ADC 131b may be the same as the column-parallel ADC 131 described with reference to fig. 2 or the column-parallel ADC 131' described with reference to fig. 9.

The first multiplexer 191 and the second multiplexer 192 may differently connect the first column line COL1 and the second column line COL2 to the first column-parallel ADC 131a and the second column-parallel ADC 131b according to the mode change signal. For example, the first multiplexer 191 and the second multiplexer 192 may connect the first column line COL1 to the first column-parallel ADC 131a, and may connect the second column line COL2 to the second column-parallel ADC 131b.

Alternatively, for example, the first column line COL1 and the second column line COL2 may be connected to one column-parallel ADC (one of the first column-parallel ADC 131a and the second column-parallel ADC 131 b) for analog combining operation (analog binning operation).

Alternatively, for example, to obtain HDR, the first multiplexer 191 and the second multiplexer 192 may connect the first column line COL1 to the first column-parallel ADC 131a and the second column-parallel ADC 131b in a first period, and then may connect the second column line COL2 to the first column-parallel ADC 131a and the second column-parallel ADC 131b in a second period. In this case, different ramp signals (e.g., ramp signals having different slopes) may be input to the first column-parallel ADC 131a and the second column-parallel ADC 131b, respectively. The image sensor 100 may obtain a piece of image data by combining the data generated in the first period with the data generated in the second period.

Fig. 14 is a schematic diagram illustrating an image sensor 1000 according to some example embodiments.

Referring to fig. 14, the image sensor 1000 may be a stacked image sensor including a first chip CP1 and a second chip CP2 stacked in a vertical direction. The image sensor 1000 may be an example of the image sensor 100 described with reference to fig. 1 and other figures.

The first chip CP1 may include a pixel region PR1 and a pad region PR2, and the second chip CP2 may include a peripheral circuit region PR3 and a lower pad region PR2'. A pixel array in which a plurality of pixels PX are arranged may be formed in the pixel region PR 1. Each pixel PX may be the same as the pixel 111 described with reference to fig. 2 or the pixel 111' described with reference to fig. 12.

The peripheral circuit region PR3 of the second chip CP2 may include a logic circuit block LC and may include a plurality of transistors. For example, the logic circuit block LC may include at least one selected from the group consisting of the row driver 120, the ADC 130, the ramp generator 160, the timing generator 170, and the buffer 180 described with reference to fig. 1.

The lower PAD region PR2 'of the second chip CP2 may include a lower conductive PAD'. A plurality of lower conductive PADs PAD 'may be provided, and the lower conductive PADs PAD' may correspond to the upper conductive PADs PAD, respectively. The lower conductive PAD' may be electrically connected to the upper conductive PAD of the first chip CP1 through the via structure VS.

The image sensor 1000 may also include a memory. The memory may be provided in the second chip CP 2. However, the embodiment is not limited thereto. Unlike the example embodiment shown in fig. 14, the memory may be disposed in a third chip separated from the first chip CP1 and the second chip CP2, and the first chip CP1, the second chip CP2, and the third chip may be stacked.

When the term "about" or "substantially" is used in this specification in connection with a numerical value, it is intended that the relevant numerical value includes manufacturing tolerances or operating tolerances (e.g., ±10%) around the stated numerical value. Furthermore, when the words "substantially" and "essentially" are used in connection with a geometric shape, it is intended that the precision of the geometric shape is not required, but that the degree of freedom of the shape is within the scope of the present disclosure. Furthermore, whether numerical values or shapes are modified to be "about" or "substantially," it is understood that such values and shapes are to be construed as including manufacturing or operating tolerances (e.g., ±10%) around the numerical values or shapes.

The image sensor 100 (or other circuitry, e.g., pixel array 110, row driver 120, ADC 130, ramp generators 160, 160', timing generator 170, buffer 180, column parallel ADC 131, 131', compare circuit 141, counter 151, first comparator 210, second comparator 220, chip CP1, chip CP2, and other sub-components of the image sensor 100) may include: hardware including logic circuits; a hardware/software combination (e.g., a processor executing software); or a combination thereof. For example, the processing circuitry may more particularly include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and the like.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims (20)

1. An analog-to-digital conversion circuit, the analog-to-digital conversion circuit comprising:

a counter; and

a comparator, the comparator comprising:

a first P-type transistor having a gate connected to a first input node of the comparator;

a second P-type transistor having a gate connected to a second input node of the comparator;

a first N-type transistor having a gate connected to the first input node and a drain connected to the first P-type transistor;

a second N-type transistor having a gate connected to the second input node and a drain connected to the second P-type transistor; and

a transistor, a gate of which is connected to the drain of the first N-type transistor, and a source of which is applied with a ground voltage or a power supply voltage.

2. The analog-to-digital conversion circuit of claim 1, wherein the comparator further comprises a switching circuit connected between the first input node and the drain of the first N-type transistor.

3. The analog-to-digital conversion circuit of claim 1, wherein the comparator further comprises a current source connected to a source of the first N-type transistor and a source of the second N-type transistor.

4. The analog-to-digital conversion circuit of claim 1, wherein,

the source of the transistor is connected to the ground voltage;

the drain of the transistor is connected to the source of the first N-type transistor and the source of the second N-type transistor, and

the transistor is an N-type transistor.

5. The analog-to-digital conversion circuit of claim 4, wherein the comparator further comprises a current source connected to a source of the first P-type transistor and a source of the second P-type transistor.

6. The analog-to-digital conversion circuit of claim 4, wherein the signal input to the first input node of the comparator is a ramp signal that rises according to a particular slope.

7. The analog-to-digital conversion circuit of claim 1, further comprising:

a first capacitor connected to the first input node of the comparator;

a second capacitor connected to the second input node of the comparator;

a third capacitor connected to one node of the first capacitor;

a fourth capacitor connected to one node of the second capacitor;

a first switching circuit configured to connect one node of the third capacitor to ground or another node of the first capacitor; and

a second switching circuit configured to connect one node of the fourth capacitor to ground or another node of the second capacitor.

8. An image sensor, the image sensor comprising:

a pixel array including a plurality of pixels;

a ramp generator configured to generate a ramp signal; and

an analog-to-digital conversion circuit configured to convert a pixel signal output from the pixel array into a digital signal, the analog-to-digital conversion circuit including a comparator and a counter, the comparator including:

A first P-type transistor having a gate connected to a first input node of the comparator, the first input node receiving the ramp signal;

a second P-type transistor having a gate connected to a second input node of the comparator, the second input node receiving the pixel signal;

a first N-type transistor having a gate connected to the first input node;

a second N-type transistor having a gate connected to the second input node; and

and a transistor having a gate connected to a drain of the first N-type transistor and a source to which a ground voltage or a power supply voltage is applied.

9. The image sensor of claim 8, wherein the comparator further comprises:

a switching circuit connected between the first input node and the drain of the first N-type transistor, an

And a switching circuit connected between the second input node and the drain of the second N-type transistor.

10. The image sensor of claim 8, wherein,

the source of the transistor is connected to the supply voltage,

The drain of the transistor is connected to the source of the first P-type transistor, and

the transistor is a P-type transistor.

11. The image sensor of claim 8, wherein,

the source of the transistor is connected to the ground voltage;

the drain of the transistor is connected to the source of the first N-type transistor, and

the transistor is an N-type transistor.

12. The image sensor of claim 8, wherein the analog-to-digital conversion circuit further comprises:

a first capacitor connected to the first input node of the comparator;

a second capacitor connected to the second input node of the comparator;

a third capacitor connected to one node of the first capacitor;

a fourth capacitor connected to one node of the second capacitor;

a first switching circuit configured to connect one node of the third capacitor to ground or another node of the first capacitor; and

a second switching circuit configured to connect one node of the fourth capacitor to ground or another node of the second capacitor.

13. The image sensor of claim 12 wherein,

in a high illumination environment, the first switching circuit is configured to connect the one node of the third capacitor to ground, and the second switching circuit is configured to connect the one node of the fourth capacitor to ground, and

in a low-light environment, the first switching circuit is configured to connect the one node of the third capacitor to the other node of the first capacitor, and the second switching circuit is configured to connect the one node of the fourth capacitor to the other node of the second capacitor.

14. An image sensor, the image sensor comprising:

a pixel array including a plurality of pixels connected to a plurality of column lines;

a ramp generator configured to generate a ramp signal; and

a plurality of analog-to-digital conversion circuits each including a first comparator and a second comparator configured to generate a comparison result signal by comparing a pixel signal output via a corresponding column line among the plurality of column lines with the ramp signal, the first comparator including:

A first P-type transistor and a first N-type transistor, the first P-type transistor and the first N-type transistor receiving the ramp signal;

a second P-type transistor and a second N-type transistor, the second P-type transistor and the second N-type transistor receiving the pixel signal;

a first output node through which a result of comparison of the pixel signal and the ramp signal is output as a first output signal;

a second output node through which a second output signal is output; and

a transistor, a gate of which is connected to the second output node, and a source of which is applied with a ground voltage or a power supply voltage.

15. The image sensor of claim 14 wherein,

the transistor is a P-type transistor, and the source of the transistor is connected to the power supply voltage, and

the first comparator further includes a current source connected to the first N-type transistor and the second N-type transistor.

16. The image sensor of claim 14 wherein,

the transistor is an N-type transistor, and the source of the transistor is connected to the ground voltage, and

The first comparator further includes a current source connected to the first P-type transistor and the second P-type transistor.

17. The image sensor of claim 14, wherein the plurality of analog-to-digital conversion circuits each further comprise:

a first capacitor connected to a first input node of the first comparator, the first input node configured to receive the ramp signal;

a second capacitor connected to a second input node of the first comparator, the second input node configured to receive the pixel signal;

a third capacitor connected to one node of the first capacitor;

a fourth capacitor connected to one node of the second capacitor;

a first switching circuit configured to connect one node of the third capacitor to ground or another node of the first capacitor; and

a second switching circuit configured to connect one node of the fourth capacitor to ground or another node of the second capacitor.

18. The image sensor of claim 17 wherein,

The ramp generator is configured to generate a first ramp signal and a second ramp signal, and

the slope of the first ramp signal is greater than the slope of the second ramp signal.

19. The image sensor of claim 18 wherein,

based on the plurality of analog-to-digital conversion circuits each receiving the first ramp signal, the first switching circuit is configured to connect the one node of the third capacitor to ground, and the second switching circuit is configured to connect the one node of the fourth capacitor to ground, and

based on the plurality of analog-to-digital conversion circuits each receiving the second ramp signal, the first switching circuit is configured to connect the one node of the third capacitor to the other node of the first capacitor, and the second switching circuit is configured to connect the one node of the fourth capacitor to the other node of the second capacitor.

20. The image sensor of claim 14, further comprising a multiplexer configured to connect the plurality of column lines to the plurality of analog-to-digital conversion circuits,

Wherein the plurality of analog-to-digital conversion circuits comprises a first analog-to-digital conversion circuit and a second analog-to-digital conversion circuit, and

wherein the multiplexer is configured to connect at least one of a first column line and a second column line of the plurality of column lines to the first analog-to-digital conversion circuit and to connect at least one of the first column line and the second column line of the plurality of column lines to the second analog-to-digital conversion circuit.