CN116565010A - Manufacturing method of shielded gate trench type MOS device - Google Patents
Manufacturing method of shielded gate trench type MOS device Download PDFInfo
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- CN116565010A CN116565010A CN202310369311.4A CN202310369311A CN116565010A CN 116565010 A CN116565010 A CN 116565010A CN 202310369311 A CN202310369311 A CN 202310369311A CN 116565010 A CN116565010 A CN 116565010A
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- 238000000034 method Methods 0.000 claims abstract description 24
- 230000008021 deposition Effects 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 58
- 239000002184 metal Substances 0.000 claims description 39
- 238000000151 deposition Methods 0.000 claims description 27
- 210000000746 body region Anatomy 0.000 claims description 23
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
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- 230000005684 electric field Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000000047 product Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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Abstract
The invention belongs to the field of semiconductor device manufacturing, and discloses a manufacturing method of a shielded gate trench type MOS device, wherein the shielded gate trench type MOS device manufactured by the method is provided with a Y-shaped trench, and an inclined notch CD is larger than an inside CD of a straight trench, so that the problems that an electric field line is concentrated at the bottom and low in withstand voltage and high in electric leakage due to the fact that the angle of the conventional U-shaped trench cannot reach 90 degrees and the problem of reducing electric leakage IDSS exists in the straight trench are avoided; the Y-shaped groove enables the shielding gate polycrystal filling morphology to be better and seamless. The shielding gate groove type MOS device is a deep groove device, a gap is easy to appear in the center in the shielding gate polycrystalline deposition process, the gap leaks out in the shielding gate polycrystalline etching process to cause device failure, and the gap can be removed through multiple shielding gate polycrystalline deposition and polycrystalline etching, but the cost is too high, and the invention solves the technical problem and has lower cost.
Description
Technical Field
The invention belongs to the field of semiconductor device manufacturing, and particularly relates to a manufacturing method of a shielded gate trench type MOS device.
Background
The shielded gate trench type MOS device (SGT MOSFET) is used as a switching device, is applied to the fields of new energy electric vehicles, novel photovoltaic power generation and the like, and is a core power control component. Because the SGT capacitance technology is obviously lower than the Trench technology, the switching loss is low, the SGT structure is 3-5 times deeper than the conventional Trench structure, the Trench digging depth can be 3-5 times deeper, more epitaxial volume can be transversely used for preventing voltage, the characteristic on-resistance of the MOSFET device is obviously reduced, and therefore, the switching loss of the SGT MOSFET is ensured and the optimization of capacitance parameters is important.
The structural design of the shielded gate trench has important significance on the product performance, and how to ensure the product performance among batches in the production process of the shielded gate trench transistor, so that the product keeps relatively stable ISGS/IGSS, the product capacitance and the electrical property are optimized, and the problem of polycrystalline filling is guaranteed, which is a technical problem to be solved urgently for the person skilled in the art.
As shown in fig. 1, a method for manufacturing an SGT MOSFET is provided in the prior art, which includes the following steps:
step 1, providing a substrate 200;
step 2, manufacturing a mask oxide layer on the upper surface of the substrate 200, etching to form a mask window, manufacturing a U-shaped groove through the window, and forming a shielding oxide layer 201 on the groove and the surface of the substrate;
step 3, depositing polycrystal in the shielding oxide layer 201 formed on the surface of the groove and the substrate, and forming shielding gate polycrystal 202 by etching;
step 4, carrying out wet etching on the trench and the shielding oxide layer 201 formed on the surface of the substrate to form an opening between the shielding oxide 2101 and the shielding gate polycrystal 202;
step 5, forming an opening on the upper surface of the shielding oxide layer 201 and the shielding gate polycrystal 202 through a thermal oxidation process, and performing thermal oxide layer deposition on the upper surface of the shielding gate polycrystal and the upper surface of the substrate to form a gate oxide layer 203;
step 6, depositing polycrystal on the upper surface of the gate oxide layer 203, and etching to form a gate polycrystal 204;
step 7, forming a P-type body region 205 on the substrate 200 by injecting and pushing a P-type body region window formed by the etched gate polycrystal 204 and the gate oxide layer 203;
step 8, forming an N+ region 206 on the side, far away from the substrate 200, of the upper surface of the P-type body region 205;
step 9, depositing an insulating layer 207 on the upper surface 200 of the substrate;
step 10, etching the insulating oxide layers on two opposite sides of the upper surface of the substrate 200 to form a small groove 208 linking the P-type body region and the n+ region;
step 11, forming a p+ region 209 on the small groove 208 linking the P-type body region and the n+ region by ion implantation and annealing;
step 12, depositing a first layer of metal 210 on the upper surface of the substrate, wherein the first layer of metal 210 is respectively contacted with all surface structures of the P-type body region 205, the N+ region 206 and the P+ region 209;
step 13, depositing a second layer of metal 211 on the first layer of metal 210, and filling the second layer of metal into the small grooves 208 through metal back etching;
step 14, continuing to deposit a third layer of metal 212 on the upper surfaces of the first layer of metal 210 and the second layer of metal 211 deposited on the substrate;
step 15. A fourth layer of metal 213 is deposited on the lower surface of the substrate.
The SGT MOSFET manufactured by the manufacturing method has the advantages that the groove opening in the groove is narrower, the groove depth is deeper, the groove bottom angle is larger, the electric field lines are densely distributed, so that the problem of larger IDSS is caused, the problem of larger ISGS is also caused due to the polycrystalline gap problem in the polycrystalline deposition process in the groove, and the inside of the polycrystal is seriously and directly oxidized; the thick oxide layer of the shielding gate has an uneven state, and the gate oxide fills the surface, so that the capacitance parameter and the IGSS are abnormal.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a manufacturing method of a shielded gate trench type MOS device, which comprises the following steps of
S101, providing a substrate;
s102, manufacturing a Y-shaped groove on the upper surface of the substrate, and forming a shielding oxide layer on the groove and the surface of the substrate;
s103, depositing polycrystal in a shielding oxide layer formed on the surfaces of the Y-shaped groove and the substrate, and forming shielding gate polycrystal by etching;
s104, carrying out dry etching on the Y-shaped groove and the shielding oxide layer formed on the surface of the substrate to enable the shielding oxide layer and the shielding gate to form an opening in a polycrystal manner;
s105, performing thermal oxide layer deposition on the upper surfaces of openings formed by the shielding oxide layer and the shielding gate polycrystal, the upper surfaces of the shielding gate polycrystal and the upper surface of the substrate to form a gate oxide layer;
s106, depositing polycrystal on the upper surface of the gate oxide layer, and etching to form gate polycrystal;
s107, forming a P-type body region on the substrate by injecting ions and pushing and bonding a P-type body region window formed by the etched gate polycrystal and gate oxide layer;
s108, manufacturing an N+ region on one side, far away from the substrate, of the upper surface of the P-type body region;
s109, depositing an insulating layer on the upper surface of the substrate;
s110, etching the insulating oxide layers positioned on two opposite sides of the upper surface of the substrate to form a small groove for linking the P-type body region and the N+ region;
s111, forming a P+ region by ion implantation and annealing of a small groove linking the P-type body region and the N+ region;
s112, depositing a first layer of metal on the upper surface of the substrate;
and S113, depositing a second layer of metal on the first layer of metal, and etching the second layer of metal back through the metal (filling the small grooves).
S114, continuing to deposit a third layer of metal on the upper surfaces of the first layer of metal and the second layer of metal deposited on the substrate;
s115, depositing a fourth layer of metal on the lower surface of the substrate.
Advantageous effects
1. The shielded gate trench type MOS device manufactured by the method has the advantages that the Y-shaped trench is formed, the CD of the inclined notch is larger than the CD in the straight trench, the problems that the conventional U-shaped trench cannot reach 90 degrees due to the fact that the angle of the trench is not equal to 90 degrees, the electric field lines are gathered at the bottom, low withstand voltage and high electric leakage occur, and the problem of reducing electric leakage IDSS exists in the straight trench are avoided.
2. The Y-shaped groove enables the shielding gate polycrystal filling morphology to be better and seamless. The shielding gate groove type MOS device is a deep groove device, a gap is easy to appear in the center in the shielding gate polycrystalline deposition process, the gap leaks out in the shielding gate polycrystalline etching process to cause device failure, and the gap can be removed through multiple shielding gate polycrystalline deposition and polycrystalline etching, but the cost is too high, and the invention solves the technical problem and has lower cost.
3. In the shielding gate polycrystalline etching process, the top polycrystalline morphology is optimized to be flat, after the thermal oxidation process, the morphology is flat, and the source gate leakage current ISGS is reduced due to the good polycrystalline morphology.
4. And dry etching is carried out on the trench and the shielding oxide layer formed on the surface of the substrate, carbon components in the surface glue are converted into a large amount of byproducts by the dry etching and are covered on the shielding oxide layer, the concave-convex shapes with low center and high edge are avoided, flat grooves symmetrical about the polycrystal central axis of the shielding gate are formed, the depth of the shielding oxide layer is the same at all positions of the bottom surface, when the gate oxide layer is formed after the thermal oxide layer process, the heights of the gate oxide layer are uniformly distributed from left to right, and the covering thickness of the gate oxide layer on the side wall is also uniformly distributed from top to bottom, so that the input capacitance CISS and the gate source drain current IGSS are improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a shielded gate trench MOS device of the prior art;
fig. 2 is a schematic flow chart of a method for manufacturing a trench type MOS device with a shield gate according to an embodiment of the present invention;
fig. 3-13 are schematic cross-sectional views of a device during a method for manufacturing a shielded gate trench MOS device according to an embodiment of the invention.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims of this application and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented, for example, in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As shown in fig. 2, the manufacturing method of the shielded gate trench type MOS device of the present invention includes the following steps: s101, providing a substrate 100;
s102, manufacturing a mask oxide layer on the upper surface of the substrate 100, etching to form a mask window, manufacturing a Y-shaped groove through the mask window, and forming a shielding oxide layer 101 on the surfaces of the groove and the substrate, as shown in FIG. 3;
s103, depositing polycrystal in the shielding oxide layer 101 formed on the surfaces of the Y-shaped groove and the substrate, wherein the thickness of the polycrystal is not less than 15000 angstroms, and forming shielding gate polycrystal 102 by etching, as shown in FIG. 4;
s104, carrying out dry etching on the Y-shaped groove and the shielding oxide layer 101 formed on the surface of the substrate to enable the shielding oxide layer 101 and the shielding gate polycrystal 102 to form an opening;
s105, performing thermal oxidation layer deposition on the upper surfaces of openings formed by the shielding oxide layer 101 and the shielding gate polycrystal 102, the upper surface of the shielding gate polycrystal 102 and the upper surface of the substrate 100 to form a gate oxide layer 103, wherein the thickness of the gate oxide layer 103 is not less than 1000 angstroms, as shown in fig. 5;
s106, depositing polycrystal on the upper surface of the gate oxide layer 103, wherein the thickness of the polycrystal is not less than 15000 angstroms, and etching to form a gate polycrystal 104, as shown in FIG. 6;
s107, forming a P-type body region 105 on the substrate 100 by injecting ions and pushing a junction into a P-type body region window formed by the etched gate polycrystal 104 and the gate oxide layer 103, as shown in FIG. 7;
s108, manufacturing an N+ region 106 on the side, away from the substrate 100, of the upper surface of the P-type body region 105, as shown in FIG. 8;
s109. as shown in fig. 9, an insulating layer 107 is deposited on the upper surface of the substrate 100;
s110, etching the insulating oxide layers on two opposite sides of the upper surface of the substrate 100 to form a small groove 108 linking the P-type body region 105 and the N+ region 106;
s111, forming a P+ region 109 by ion implantation and annealing of the small groove 108 linking the P-type body region 105 and the N+ region, as shown in FIG. 10;
s112, as shown in FIG. 11, depositing a first layer of metal 110 on the upper surface of the substrate 100, wherein the first layer of metal 110 is respectively contacted with surface structures such as a P-type body region 105, an N+ region 106, a P+ region 109 and the like;
s113, depositing a second layer of metal 111 on the first layer of metal 110, and filling the second layer of metal 111 into the small groove 108 through metal back etching.
S114, continuing to deposit a third layer of metal 112 on the upper surfaces of the first layer of metal 110 and the second layer of metal 111 deposited on the substrate 100, as shown in FIG. 12;
s115, depositing a fourth layer of metal 113 on the lower surface of the substrate 100.
In one embodiment of the present invention, a special-shaped Y-shaped trench is formed on the upper surface of the substrate 100, a mask oxide layer is deposited on the substrate 100, a photoresist is coated on the mask oxide layer, a pattern formed by the photoresist is etched to form a mask window, in the trench etching step, a low-power (100-140W) and then high-power (150-200W) mode and a multi-step etching mode are adopted to etch a Y-shaped trench, wherein the upper portion of the formed Y-shaped trench is a chute, and the lower portion is a straight trench.
In one embodiment of the present invention, polycrystal is deposited in the Y-shaped trench and the shielding oxide layer 101 formed on the surface of the substrate 100, and the shielding gate polycrystal with smooth surface is formed by the production principle of different gas byproducts, so that abnormal morphology is avoided, and the electric parameters of the ISGS can be reduced in the ISGS test process.
In one embodiment of the present invention, the Y-shaped trench and the shielding oxide layer 101 formed on the surface of the substrate 100 are subjected to dry etching instead of wet etching, the wet etching may cause the concave-convex shape of the shielding oxide layer 101, the Y shape may cause the difference in thickness of shielding oxide layers on both sides, and the flat shielding oxide layer shape may be obtained by dry etching without the problem of undercut, and the method of corrosion-oxidation-corrosion is not required.
What has been described above and shown in the drawings is merely a preferred embodiment of the invention. It should be noted that variations and modifications could be made by those skilled in the art without departing from the principles of the present invention, which would also be considered to be within the scope of the present invention.
Claims (8)
1. A manufacturing method of a shielded gate trench type MOS device comprises the following steps:
s101, providing a substrate (100);
s102, manufacturing a Y-shaped groove on the upper surface of the substrate (100), and forming a shielding oxide layer (101) on the groove and the surface of the substrate;
s103, depositing polycrystal in a shielding oxide layer (101) formed on the surfaces of the Y-shaped groove and the substrate, and forming shielding gate polycrystal (102) through etching;
s104, carrying out dry etching on the Y-shaped groove and a shielding oxide layer (101) formed on the surface of the substrate, so that the shielding oxide layer (101) and a shielding gate polycrystal (102) form an opening;
s105, performing thermal oxide layer deposition on the upper surface of an opening formed by the shielding oxide layer (101) and the shielding gate polycrystal (102), the upper surface of the shielding gate polycrystal (102) and the upper surface of the substrate (100) to form a gate oxide layer (103);
s106, depositing polycrystal on the upper surface of the gate oxide layer (103), and etching to form gate polycrystal (104);
s107, forming a P-type body region (105) on the substrate (100) by injecting ions and pushing and bonding a P-type body region window formed by the etched gate polycrystal (104) and the gate oxide layer (103);
s108, manufacturing an N+ region (106) on one side, far away from the substrate (100), of the upper surface of the P-type body region (105);
s109, depositing an insulating layer (107) on the upper surface of the substrate (100);
s110, etching the insulating oxide layers positioned on two opposite sides of the upper surface of the substrate (100) to form a small groove (108) linking the P-type body region (105) and the N+ region (106);
s111, forming a P+ region (109) by ion implantation and annealing of a small groove (108) linking the P-type body region (105) and the N+ region;
s112, depositing a first layer of metal (110) on the upper surface of the substrate (100);
s113, depositing a second layer of metal (111) on the first layer of metal (110), and filling the second layer of metal (111) into the small groove (108) through metal back etching;
s114, continuing to deposit a third layer of metal (112) on the upper surfaces of the first layer of metal (110) and the second layer of metal (111) deposited on the substrate (100);
s115, depositing a fourth layer of metal (113) on the lower surface of the substrate (100).
2. The method for manufacturing the shielded gate trench type MOS device of claim 1, wherein: in step S102, a mask oxide layer is deposited on the substrate (100), a photoresist is coated on the mask oxide layer, a mask window is formed by etching a pattern formed by the photoresist, in the step of etching a groove, a Y-shaped groove is etched by adopting a mode of etching with low power and then etching with high power, and a mode of etching with multiple steps, the upper part of the formed Y-shaped groove is a chute, and the lower part of the formed Y-shaped groove is a straight chute.
3. The method for manufacturing the shielded gate trench type MOS device of claim 2, wherein: the low power is 100-140W, and the high power is 150-200W.
4. The method for manufacturing the shielded gate trench type MOS device of claim 1, wherein: step (a)
In S103, the polycrystalline thickness is not less than 15000 angstroms.
5. The method for manufacturing the shielded gate trench type MOS device of claim 1, wherein: in step S105, the gate oxide layer (103) has a thickness of not less than 1000 angstroms.
6. The method for manufacturing the shielded gate trench type MOS device of claim 1, wherein: the poly thickness in step S106 is not less than 15000 angstroms.
7. The method for manufacturing the shielded gate trench type MOS device of claim 1, wherein: in step S112, the first metal layer (110) is respectively contacted with the surface structures of the P-type body region (105), the n+ region (106), the p+ region (109) and the like.
8. The method for manufacturing the shielded gate trench type MOS device of claim 1, wherein: the shielding gate poly (102) is formed to be smooth in surface.
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| CN202310369311.4A CN116565010A (en) | 2023-04-10 | 2023-04-10 | Manufacturing method of shielded gate trench type MOS device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117637814A (en) * | 2024-01-26 | 2024-03-01 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
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| CN103311299A (en) * | 2012-03-09 | 2013-09-18 | 飞兆半导体公司 | Shielded gate mosfet device with a funnel-shaped trench |
| CN105702736A (en) * | 2016-01-29 | 2016-06-22 | 上海华虹宏力半导体制造有限公司 | A shield grid oxide layer of a shield grid-deep groove MOSFET and a formation method thereof |
| CN108389858A (en) * | 2018-02-05 | 2018-08-10 | 华润微电子（重庆）有限公司 | The shield grid groove MOSFET device and its manufacturing method of integrated ESD protection diodes |
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| CN113745337A (en) * | 2021-07-19 | 2021-12-03 | 四川遂宁市利普芯微电子有限公司 | Manufacturing method of MOSFET (metal-oxide-semiconductor field effect transistor) with shielded gate trench |
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