CN116363998A - Display panel and display device - Google Patents
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- CN116363998A CN116363998A CN202310340050.3A CN202310340050A CN116363998A CN 116363998 A CN116363998 A CN 116363998A CN 202310340050 A CN202310340050 A CN 202310340050A CN 116363998 A CN116363998 A CN 116363998A
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- 239000003990 capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0257—Reduction of after-image effects
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the invention discloses a display panel and a display device. The display panel comprises at least two pixel circuits; the pixel circuit comprises a data writing module and a frequency adjusting module; the control end of the data writing module is connected with a first scanning signal, and the control end of the frequency adjusting module is connected with a second scanning signal; the data line is connected with the data writing module and is used for transmitting data voltage to the pixel circuit according to the first scanning signal in the data writing stage; the frequency adjustment module is used for controlling the data writing module to write data voltage with a preset driving frequency according to the second scanning signal; the preset driving frequencies of at least two pixel circuits are different. The technical scheme provided by the embodiment realizes different refresh frequencies in different areas of the display panel, and reduces the power consumption of the display panel.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the development of display technology, the requirements of people on the display panel are increasing. The pixel circuit of the existing display panel generally adopts the same refresh frequency to display pictures, and has the problem that different refresh frequency functions are difficult to realize in different areas of the display panel, so that the display panel has higher power consumption.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for realizing different refresh frequencies in different areas of the display panel.
In order to realize the technical problems, the invention adopts the following technical scheme:
according to an aspect of the present invention, an embodiment of the present invention provides a display panel including:
at least two pixel circuits; the pixel circuit comprises a data writing module and a frequency adjusting module; the control end of the data writing module is connected with a first scanning signal, and the control end of the frequency adjusting module is connected with a second scanning signal;
the data line is connected with the data writing module and is used for transmitting data voltage to the pixel circuit according to the first scanning signal in the data writing stage;
the frequency adjustment module is used for controlling the data writing module to write data voltage with a preset driving frequency according to the second scanning signal;
the preset driving frequencies of at least two pixel circuits are different.
Alternatively, the driving frequencies of the pixel circuits located in the same row are the same;
the drive frequencies of at least two rows of pixel circuits are different.
Optionally, the display panel includes at least two display areas along the first direction;
the driving frequencies of the pixel circuits in the same display area are the same;
the driving frequencies of the pixel circuits located in different display areas are different.
Optionally, along the first direction, the display panel sequentially includes a first display area, a second display area, and a third display area;
the driving frequencies of the pixel circuits located in the first display region, the second display region, and the third display region are different.
Optionally, the driving transistor and the light emitting module are connected between the first power supply voltage input end and the light emitting module; the frequency adjustment module is connected between the data writing module and the grid electrode of the driving transistor, and the second pole of the light emitting module is connected with the second power supply voltage input end;
preferably, the pixel circuit further includes: and the storage module is connected between the first power supply voltage input end and the grid electrode of the driving transistor.
Optionally, the pixel circuit further includes:
the driving circuit comprises a compensation module, a driving transistor and a light emitting module;
the driving transistor is connected between the first power supply voltage input end and the light emitting module; the data writing module is connected with the first electrode of the driving transistor to be connected with the first node, the compensating module is connected with the second electrode of the driving transistor to be connected with the second node, and the compensating module is connected with the grid electrode of the driving transistor to be connected with the third node;
the control end of the compensation module is connected with the first scanning signal; the compensation module is used for writing information containing the threshold voltage of the driving transistor to the grid electrode of the driving transistor in the data writing stage;
the driving transistor is used for generating a driving signal according to the voltage of the grid electrode of the driving transistor in the light-emitting stage to drive the light-emitting module to emit light;
the data writing module is used for writing data voltage to the grid electrode of the driving transistor in the data writing stage;
the frequency adjustment module is connected between the compensation module and the third node; or the frequency adjustment module is connected between the data writing module and the first node; alternatively, the frequency adjustment module is connected between the second pole of the driving transistor and the second node; the frequency adjustment module is used for controlling the period of the writing frame and the holding frame according to the on or off of the second scanning signal so as to adjust the driving frequency of the pixel circuit.
Optionally, the second scan signal is used for being a lighting signal in a data writing stage of a writing frame, and is a blanking signal in a data writing stage of a holding frame;
the frequency adjustment module is used for responding to the second scanning signal, being conducted in a data writing stage of the writing frame and being turned off in a data writing stage of the holding frame.
Optionally, the pixel circuit further includes:
the system comprises a first initialization module and a second initialization module;
the first initialization module is connected between the compensation module and the initialization line, the control end of the first initialization module is connected with a third scanning signal, and the first initialization module is used for initializing the grid electrode of the driving transistor in the first initialization stage;
the second initialization module is connected between the anode of the light-emitting module and the initialization line, the control end of the second initialization module is connected with a fourth scanning signal, and the second initialization module is used for initializing the anode of the light-emitting module in the second initialization stage.
Optionally, the pixel circuit further includes:
the control ends of the first light-emitting control module and the second light-emitting control module are connected with light-emitting control signals, and the first light-emitting control module is connected between the first power supply voltage input end and the first node;
the second light-emitting control module is connected between the second node and the anode of the light-emitting module, and the cathode of the light-emitting module is electrically connected with the second power supply voltage input end;
preferably, the pixel circuit further includes: the storage module is connected between the first power supply voltage input end and the third node.
According to another aspect of the present invention, there is provided a display device including: the display panel provided in the first aspect.
The display panel provided by the embodiment of the invention is provided with the frequency adjustment module, and the control end of the frequency adjustment module is connected with the second scanning signal. The frequency adjustment module controls the data writing module to write the data voltage with a preset driving frequency according to the second scanning signal, and the preset driving frequency of the at least two pixel circuits is different through setting the period of the second scanning signal, so that the at least two pixel circuits are charged with different preset driving frequencies, different refreshing frequencies of the display panel are realized in different areas, and the power consumption of the display panel is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings needed in the description of the embodiments of the present invention, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the contents of the embodiments of the present invention and these drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a pixel circuit of a display panel according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a driving timing of a pixel circuit of a display panel according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a driving timing of a pixel circuit of another display panel according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another display panel according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of another display panel according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a pixel circuit of another display panel according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a pixel circuit of another display panel according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a driving timing of a pixel circuit of a display panel according to another embodiment of the present invention;
fig. 10 is a schematic diagram of a driving timing of a pixel circuit of a display panel according to another embodiment of the present invention;
fig. 11 is a schematic structural diagram of a pixel circuit of another display panel according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a pixel circuit of a display panel according to another embodiment of the present invention;
fig. 13 is a schematic diagram showing a driving timing of a pixel circuit of a display panel according to another embodiment of the present invention;
fig. 14 is a schematic diagram showing a driving timing of a pixel circuit of a display panel according to another embodiment of the present invention;
fig. 15 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Based on the above technical problems, the present embodiment proposes the following solutions:
fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Fig. 2 is a schematic structural diagram of a pixel circuit of a display panel according to an embodiment of the present invention. Fig. 3 is a schematic diagram of a driving timing of a pixel circuit of a display panel according to an embodiment of the present invention. Fig. 4 is a schematic diagram of a driving timing of a pixel circuit of another display panel according to an embodiment of the present invention. Referring to fig. 1 to 4, a display panel 100 according to an embodiment of the present invention includes at least two pixel circuits 10; the pixel circuit 10 includes a data writing module 1 and a frequency adjusting module 2; the control end of the data writing module 1 is connected with a first scanning signal S2, and the control end of the frequency adjusting module 2 is connected with a second scanning signal S4; a data line connected to the data writing module 1, the data line being configured to transmit a data voltage Vdata to the pixel circuit 10 according to the first scan signal S2 in a data writing phase t 2; the frequency adjustment module 2 is configured to control the data writing module 1 to write the data voltage Vdata at a preset driving frequency according to the second scanning signal S4; the preset driving frequencies of at least two pixel circuits 10 are different.
Specifically, the data writing module 1 writes the data voltage Vdata transmitted on the data line into the gate of the driving transistor T1 of the pixel circuit 10 in the data writing stage T2. The driving process of the display panel includes a write frame and a sustain frame. The length of time of the hold frame between two adjacent write frames determines the frequency at which the data voltage Vdata of the write frame charges the pixel circuit 10. The frequency adjustment module 2 is responsive to the second scan signal S4, and the second scan signal S4 can control the frequency adjustment module 2 to be turned on and off.
May be disposed in the writing frame, and when the frequency adjustment module 2 is turned on according to the second scan signal S4, the data writing module 1 may write the data voltage Vdata to the gate of the driving transistor T1 of the pixel circuit 10 to charge the gate of the driving transistor T1 of the pixel circuit 10. May be provided in the holding frame, and when the frequency adjustment module 2 is turned off according to the second scan signal S4, the data writing module 1 cannot write the data voltage Vdata to the gate of the driving transistor T1 of the pixel circuit 10, and the pixel circuit 10 is still in the holding frame. By adjusting the period of the second scan signal S4, thereby adjusting the on state of the frequency adjustment module 2, the data writing module 1 can be adjusted to charge the pixel circuit 10 at a preset driving frequency.
By setting the preset driving frequencies of the at least two pixel circuits 10 to be different, the period of the second scanning signal S4 can be adjusted, so that the at least two pixel circuits 10 are charged at different preset driving frequencies, and the display panel 100 is in different areas, so that different refresh frequencies are realized, and the power consumption of the display panel is reduced.
The display panel 100 provided in this embodiment is provided with the frequency adjustment module 2, and the control end of the frequency adjustment module 2 is connected to the second scan signal S4. The frequency adjustment module 2 controls the data writing module 1 to write the data voltage Vdata at a preset driving frequency according to the second scan signal S4, and sets the preset driving frequencies of the at least two pixel circuits 10 to be different, so that the at least two pixel circuits 10 are charged at different preset driving frequencies by adjusting the period of the second scan signal S4, so that the display panel 100 achieves different refresh frequencies in different areas.
Alternatively, with continued reference to fig. 1, the driving frequencies of the pixel circuits 10 located in the same row are the same on the basis of the above-described embodiment; the drive frequencies of at least two rows of pixel circuits 10 are different.
Specifically, the pixel circuits 10 located in the same row can write the data voltage Vdata with the same driving frequency, so that the number of the first scanning lines transmitting the first scanning signal S2 in the pixel circuits 10 and the number of the second scanning lines transmitting the second scanning signal S4 can be saved, the transmittance of the display panel 100 is improved, and the display panel 100 is convenient to set the optical devices under the screen.
Setting the driving frequencies of the at least two rows of pixel circuits 10 to be different may be performed by setting the driving frequencies of the at least two rows of pixel circuits 10 to be different so that the at least two rows of pixel circuits 10 are charged at different driving frequencies by adjusting the period of the second scan signal S4 of the pixel circuit 10 located in the same row so that the display panel 100 achieves different driving frequencies in different regions. The pixel circuit 10 can be driven at different driving frequencies in different regions of the display panel 100 according to the display requirement of the display panel 100, so that the pixel circuit 10 is suitable for the display requirement of the display panel 100 such as a folding screen, the power consumption of the display panel 100 is reduced, and the user experience of the display panel 100 is improved.
Optionally, fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention. On the basis of the above-described embodiment, referring to fig. 5, the display panel 100 may include at least two display regions in the first direction Y; the driving frequencies of the pixel circuits 10 located in the same display area are the same; the driving frequencies of the pixel circuits 10 located in different display areas are different.
Specifically, the first direction Y may include a row direction or a column direction of the pixel circuit 10. The display panel 100 is divided into at least two display areas along the first direction Y. The driving frequencies of the pixel circuits 10 located in the same display area may be set to be the same, so that the same timing of the second scan signal S4 may be used to drive the pixel circuits 10 in the same display area, so as to improve the driving efficiency of the pixel circuits 10 in the same display area.
The driving frequencies of the pixel circuits 10 positioned in different display areas are different, the driving frequencies of the pixel circuits 10 in each display area can be flexibly set according to the needs, different refresh frequencies in different areas of the display panel 100 are realized, the display panel 100 can meet the application scenes of different refresh frequency requirements conveniently, the display effect of the display panel 100 is improved, and the power consumption of the display panel 100 is reduced.
Note that, fig. 5 exemplarily illustrates a case where the display panel 100 includes three display areas in the column direction, and the positions and the number of the display areas included in the display panel 100 may be set as needed, which is not limited in any way.
Alternatively, with continued reference to fig. 5, the display panel 100 includes a first display area A1, a second display area A2, and a third display area A3 in this order along the first direction Y, based on the above-described embodiments; the driving frequencies of the pixel circuits 10 located in the first, second, and third display areas A1, A2, and A3 are different.
Specifically, the display panel 100 includes a first display area A1, a second display area A2, and a third display area A3 in this order along the first direction Y, so that the display panel 100 is conveniently configured as a display panel having different driving frequency requirements, such as a folded display panel 100. For example, the display panel 100 may be provided as a two-fold display panel 100, and the display panel 100 includes a first display area A1, a second display area A2, and a third display area A3. The driving frequencies of the pixel circuits 10 located in the first, second, and third display areas A1, A2, and A3 may be set to be different, for example, the driving frequency of the second display area A2 is the largest. Alternatively, the driving frequencies of the pixel circuits 10 located in the first, second, and third display areas A1, A2, and A3 may be set to gradually vary, for example, gradually increase or gradually decrease. By way of example, the driving frequency of the pixel circuit 10 located in the first display area A1 may be set to 120Hz, the driving frequency of the pixel circuit 10 in the second display area A2 may be set to 60Hz, and the driving frequency of the pixel circuit 10 in the third display area A3 may be set to 30Hz. The setting can reasonably set the driving frequency of different display areas of the display panel 100 according to the requirement of the display screen of the display panel 100, the display requirement of the display panel 100 is better met, the electric quantity of a display device can be better saved, the standby time of the display device is improved, the power consumption of the display panel 100 is reduced, and the use experience of a user is improved.
Optionally, on the basis of the above embodiment, with continued reference to fig. 2 to fig. 4, the pixel circuit 10 provided in this embodiment may further include: the driving transistor T1 and the light emitting module D1, wherein the driving transistor T1 is connected between the first power supply voltage input end VDD and the light emitting module D1; the frequency adjustment module 2 is connected between the data writing module 1 and the gate of the driving transistor T1, and the second pole of the light emitting module D1 is connected to the second power voltage input terminal VSS. Optionally, the pixel circuit 10 may further include: and a storage module Cst connected between the first power voltage input terminal VDD and the gate of the driving transistor T1.
Specifically, the driving transistor T1 is configured to generate a driving signal according to the voltage of its gate in the light-emitting stage T4 to drive the light-emitting module D1 to emit light; the data writing module 1 is configured to write the data voltage Vdata to the gate of the driving transistor T1 in the data writing phase T2. The frequency adjustment module 2 is used for controlling the period of the writing frame and the holding frame according to the second scanning signal S4 to adjust the driving frequency of the pixel circuit 10. The arrangement realizes that different areas of the display panel 100 have different refresh frequencies, is convenient for the display panel 100 to meet the application scene of different refresh frequency demands, improves the display effect of the display panel 100, and reduces the power consumption of the display panel 100.
Optionally, fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Fig. 7 is a schematic structural diagram of a pixel circuit of another display panel according to an embodiment of the present invention. Fig. 8 is a schematic structural diagram of a pixel circuit of another display panel according to an embodiment of the present invention.
On the basis of the above-described embodiment, referring to fig. 6 to 14, the pixel circuit 10 provided in this embodiment may further include: a compensation module 3, a driving transistor T1, and a light emitting module D1; the driving transistor T1 is connected between the first power voltage input terminal VDD and the light emitting module D1; the first poles of the data writing module 1 and the driving transistor T1 are connected to the first node N1, the second poles of the compensation module 3 and the driving transistor T1 are connected to the second node N2, and the gate of the compensation module 3 and the driving transistor T1 are connected to the third node N3.
The control end of the compensation module 3 is connected with a first scanning signal S2; the compensation module 3 is used for writing information including the threshold voltage of the driving transistor T1 to the gate of the driving transistor T1 in the data writing stage T2. The driving transistor T1 is configured to generate a driving signal according to a voltage of its gate in the light emitting stage T4 to drive the light emitting module D1 to emit light. The data writing module 1 is configured to write the data voltage Vdata to the gate of the driving transistor T1 in the data writing phase T2.
Fig. 9 is a schematic diagram of a driving timing of a pixel circuit of a display panel according to another embodiment of the present invention. Fig. 10 is a schematic diagram of a driving timing of a pixel circuit of a display panel according to another embodiment of the present invention. Referring to fig. 6 to 10, the frequency adjustment module 2 is connected between the compensation module 3 and the third node N3. The frequency adjustment module 2 is used for controlling the period of the writing frame and the holding frame according to the second scanning signal S4 to adjust the driving frequency of the pixel circuit 10.
Specifically, the compensation module 3 may include a P-type transistor, and the control terminal of the compensation module 3 is connected to the first scanning signal S2. In the data writing stage T2, the compensation module 3 is turned on in response to the first scan signal S2 at the control end, so that the data voltage Vdata is written into the gate of the driving transistor T1 through the data writing module 1, the driving transistor T1, the compensation module 3 and the frequency adjustment module 2, and the pixel circuit 10 is charged.
Further, the frequency adjustment module 2 may include a switching transistor, and fig. 8 exemplarily illustrates a case where the frequency adjustment module 2 includes a P-type transistor and the data writing module 1 includes a P-type transistor. Fig. 9 exemplarily shows a timing chart at a data writing frame. In the data writing stage T2 of the writing frame, the first scan signal S2 is a low level signal, the data writing module 1 is turned on, the second scan signal S4 is a low level signal, and the frequency adjusting module 2 is turned on, so that the data voltage Vdata transmitted on the data line is written into the gate of the driving transistor T1 of the pixel circuit 10.
Fig. 10 exemplarily shows a timing diagram of a hold frame. The frequency of the first scan signal S2 of each pixel circuit 10 of the display panel 100 may be the same. In the hold frame, the second scan signal S4 is at a high level, so that the frequency adjustment module 2 is turned off, thereby making the data writing module 1 unable to write the data voltage Vdata to the gate of the driving transistor T1 of the pixel circuit 10 even if the first scan signal S2 comes, so that the time length of the hold frame of the pixel circuit 10 can be set as needed. The second scan signal S4 controls the period of turning on or off the frequency adjustment module 2, thereby controlling the period of the writing frame and the holding frame of the pixel circuit 10, and realizing adjustment of the driving frequency of the pixel circuit 10.
Fig. 11 is a schematic structural diagram of a pixel circuit of a display panel according to another embodiment of the present invention. Referring to fig. 6, 9 to 11, the frequency adjustment module 2 is connected between the data writing module 1 and the first node N1.
Specifically, the difference from the above embodiment is that the frequency adjustment module 2 is connected between the data writing module 1 and the first node N1, and the frequency adjustment module 2 is configured to control the period of writing the frame and maintaining the frame according to the second scan signal S4 to adjust the driving frequency of the pixel circuit 10. The driving process is similar to that of the above embodiment, and will not be described again.
Fig. 12 is a schematic structural diagram of a pixel circuit of a display panel according to another embodiment of the present invention. Fig. 13 is a schematic diagram of a driving timing of a pixel circuit of a display panel according to another embodiment of the present invention. Fig. 14 is a schematic diagram of a driving timing of a pixel circuit of a display panel according to another embodiment of the present invention. Referring to fig. 12 to 14, the frequency adjustment module 2 is connected between the second pole of the driving transistor T1 and the second node N2.
Specifically, the difference from the above embodiment is that the frequency adjustment module 2 is connected between the second pole of the driving transistor T1 and the second node N2, and the frequency adjustment module 2 is configured to control the period of writing the frame and maintaining the frame according to the second scan signal S4 to adjust the driving frequency of the pixel circuit 10. The specific driving process is as follows:
fig. 13 exemplarily shows a timing chart at a data writing frame. In the data writing stage T2 of the writing frame, the first scan signal S2 is a low level signal, the data writing module 1 is turned on, the second scan signal S4 is a low level signal, and the frequency adjusting module 2 is turned on, so that the data voltage Vdata transmitted on the data line is written into the gate of the driving transistor T1 of the pixel circuit 10. Fig. 14 exemplarily shows a timing chart of a hold frame. In the second time period T2 'of the hold frame, the second scan signal S4 is a high level signal, so that the frequency adjustment module 2 is turned off, and thus the data writing module 1 cannot write the data voltage Vdata to the gate of the driving transistor T1 of the pixel circuit 10 even if the first scan signal S2 arrives, so that the time length of the second time period T2' of the hold frame of the pixel circuit 10 can be set as needed. The second scan signal S4 controls the period of turning on or off the frequency adjustment module 2, thereby controlling the period of the writing frame and the holding frame of the pixel circuit 10, and realizing adjustment of the driving frequency of the pixel circuit 10.
In the light emitting stage t4 of the writing frame, the first scan signal S2 is a high level signal, the data writing module 1 is turned off, the second scan signal S4 is a low level signal, the frequency adjusting module 2 is turned on, the light emitting control signal EM is a low level signal, and the first light emitting control module 7 and the second light emitting control module 8 are both turned on, so that the light emitting module D1 emits light. In the fourth period t4' of the hold frame, the second scan signal S4 is a low level signal, so that the frequency adjustment module 2 is turned on, the light emission control signal EM is a low level signal, and both the first light emission control module 7 and the second light emission control module 8 are turned on, so that the light emission module D1 emits light.
In summary, the arrangement can ensure that the display panel 100 displays images normally, and can realize that different areas of the display panel 100 have different refresh frequencies, so that the display panel 100 can meet application scenes with different refresh frequency requirements, thereby reducing power consumption of the display panel 100 and further improving display effect of the display panel.
Optionally, on the basis of the above embodiment, with reference to fig. 8 to 10, the second scan signal S4 is an on signal in the data writing stage t2 of the writing frame, and is an off signal in the data writing stage of the holding frame; the frequency adjustment module 2 is configured to be turned on during a data writing phase t2 of a writing frame and turned off during a data writing phase of a holding frame in response to the second scan signal S4.
Specifically, the setting may adjust the time and period of the data writing stage of the hold frame and the data writing stage t2 of the writing frame of the display panel 100 by setting the duty ratio of the on signal and the off signal of the second scan signal S4, and further adjust the frequency of writing the data voltage Vdata by the pixel circuit 10, so as to adjust the driving frequency of the pixel circuit 10, so that the display panel 100 may select a suitable driving frequency according to the display requirement, and further reduce the power consumption of the display panel 100.
It should be noted that fig. 10 exemplarily illustrates a case where the hold frame includes a first time period t1', a second time period t2', a third time period t3', and a fourth time period t 4'. Since the holding frame is not written with data and is not initialized, the second time period t2 'of the holding frame corresponds to the data writing period of the holding frame described above, and the fourth time period t4' of the holding frame corresponds to the light emitting period of the holding frame described above. The above-described data writing stage of the holding frame is only for facilitating understanding of the correspondence between the holding frame and the writing frame, and is not limited in any way.
Optionally, with continued reference to fig. 8, the pixel circuit 10 provided in this embodiment may further include a first initialization module 4 and a second initialization module 5; the first initialization module 4 is connected between the compensation module 3 and the initialization line Vref, a control end of the first initialization module 4 is connected to the third scanning signal S1, and the first initialization module 4 is configured to initialize the gate of the driving transistor T1 in the first initialization stage T1; the second initialization module 5 is connected between the anode of the light emitting module D1 and the initialization line Vref, and a control end of the second initialization module 5 is connected to the fourth scan signal S3, and the second initialization module 5 is configured to initialize the anode of the light emitting module D1 in the second initialization stage t 3.
Specifically, in the first initialization stage T1, the first initialization module 4 is turned on according to the third scan signal S1, writes an initialization voltage into the gate of the driving transistor T1, and initializes the gate of the driving transistor T1. The gate voltages of the driving transistors T1 of the pixel circuits 10 are made as uniform as possible between the writing data voltages Vdata by the writing initialization voltage, so that the writing data voltages Vdata are more accurate, and the display uniformity of the display panel 100 can be improved. In the second initialization stage t3, the second initialization module 5 is turned on according to the fourth scan signal S3, and after the data writing stage t2, the second initialization module 5 initializes the anode of the light emitting module D1, so that the anode potential of the light emitting module D1 of each pixel circuit 10 is as consistent as possible, the display screen of each pixel circuit 10 is more accurate in the light emitting stage t4, the defects such as the residual image of the display panel 100 are reduced, and the display effect of the display panel 100 is further improved.
Referring to fig. 10, in the data writing stage of the sustain frame, since the second scan signal S4 is set to a high level signal, the frequency adjustment module 2 is turned off, so that neither the first time period t1' nor the second time period t2' of the pixel circuit sustain frame can write a voltage signal to the gate of the driving transistor, and in the third time period t3' of the sustain frame, an initialization voltage can be written to the anode of the light emitting module D1 through the second initialization module 5.
Optionally, with continued reference to fig. 8, the pixel circuit 10 provided in this embodiment may further include: the first light-emitting control module 7 and the second light-emitting control module 8, wherein the control ends of the first light-emitting control module 7 and the second light-emitting control module 8 are connected with light-emitting control signals, and the first light-emitting control module 7 is connected between the first power supply voltage input end VDD and the first node N1; the second light-emitting control module 8 is connected between the second node N2 and the anode of the light-emitting module D1, and the cathode of the light-emitting module D1 is electrically connected with the second power supply voltage input terminal VSS; preferably, the pixel circuit 10 further includes: the memory module 6, the memory module 6 is connected between the first power voltage input terminal VDD and the third node N3.
Specifically, the first light emitting control module 7 includes a first light emitting control transistor T5, the second light emitting control module 8 includes a second light emitting control transistor T6, the light emitting module D1 includes a light emitting device D1, and the light emitting device D1 may be an organic light emitting device or an inorganic light emitting device, which is not particularly limited herein. When the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on according to the light emitting control signal EM that is connected to the control terminals thereof, the driving transistor T1 generates a driving signal according to the voltage of the gate thereof in the light emitting stage T4 to drive the light emitting module D1 to emit light. The storage module 6 includes a storage capacitor Cst for storing electric energy and stabilizing a gate potential of the driving transistor T1, thereby further improving a voltage holding rate of the potential of the gate of the driving transistor T1, and thus improving a flicker problem.
It should be noted that, in the fourth period T4 'of the holding frame, the light emission control signal EM controls the first light emission control module 7 and the second light emission control module 8 to be turned on, and the driving transistor T1 generates a driving signal according to the voltage of its gate to drive the light emitting module D1 to emit light in the fourth period T4' of the holding frame.
With continued reference to fig. 6, the first power voltage input terminal VDD, the second power voltage input terminal VSS and the initialization voltage Vref in the display panel 100 according to the embodiment of the invention may be connected to the driving chip 20, and the driving chip 20 is configured to provide voltage signals to the first power voltage input terminal VDD, the second power voltage input terminal VSS and the initialization voltage Vref.
Fig. 15 is a schematic structural diagram of a display panel according to an embodiment of the present invention. On the basis of the foregoing embodiments, referring to fig. 15, the display device 200 provided in the embodiment of the present invention, including the display panel 100 provided in any of the foregoing embodiments, has the beneficial effects of the display panel 100 provided in any of the foregoing embodiments, and is not described herein again. The display device 200 provided by the embodiment of the invention can comprise a mobile phone, a computer, a wearable device and other terminals.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A display panel, comprising:
at least two pixel circuits; the pixel circuit comprises a data writing module and a frequency adjusting module; the control end of the data writing module is connected with a first scanning signal, and the control end of the frequency adjusting module is connected with a second scanning signal;
the data line is connected with the data writing module and is used for transmitting data voltage to the pixel circuit according to the first scanning signal in a data writing stage;
the frequency adjustment module is used for controlling the data writing module to write data voltage with a preset driving frequency according to the second scanning signal;
the preset driving frequencies of at least two of the pixel circuits are different.
2. The display panel of claim 1, wherein the display panel comprises,
the driving frequencies of the pixel circuits positioned in the same row are the same;
the driving frequencies of the pixel circuits of at least two rows are different.
3. The display panel of claim 1, wherein the display panel comprises,
the display panel comprises at least two display areas along a first direction;
the driving frequency of each pixel circuit positioned in the same display area is the same;
the driving frequencies of the pixel circuits located in different display areas are different.
4. The display panel according to claim 3, wherein,
the display panel sequentially comprises a first display area, a second display area and a third display area along the first direction;
the driving frequencies of the pixel circuits located in the first display region, the second display region, and the third display region are different.
5. The display panel of claim 1, wherein the pixel circuit further comprises:
the driving transistor is connected between the first power supply voltage input end and the light emitting module; the frequency adjustment module is connected between the data writing module and the grid electrode of the driving transistor, and the second pole of the light emitting module is connected with the second power supply voltage input end;
preferably, the pixel circuit further includes: and the storage module is connected between the first power supply voltage input end and the grid electrode of the driving transistor.
6. The display panel of claim 1, wherein the pixel circuit further comprises:
the driving circuit comprises a compensation module, a driving transistor and a light emitting module;
the driving transistor is connected between the first power supply voltage input end and the light emitting module; the data writing module and the first pole of the driving transistor are connected to a first node, the compensation module and the second pole of the driving transistor are connected to a second node, and the compensation module and the grid of the driving transistor are connected to a third node;
the control end of the compensation module is connected with the first scanning signal; the compensation module is used for writing information containing the threshold voltage of the driving transistor to the grid electrode of the driving transistor in the data writing stage;
the driving transistor is used for generating a driving signal according to the voltage of the grid electrode of the driving transistor in the light-emitting stage to drive the light-emitting module to emit light;
the data writing module is used for writing data voltage to the grid electrode of the driving transistor in a data writing stage;
the frequency adjustment module is connected between the compensation module and the third node; or the frequency adjustment module is connected between the data writing module and the first node; alternatively, the frequency adjustment module is connected between the second pole of the driving transistor and the second node; the frequency adjustment module is used for controlling the period of the writing frame and the holding frame according to the on or off of the second scanning signal so as to adjust the preset driving frequency of the pixel circuit.
7. The display panel of claim 1, wherein the display panel comprises,
the second scanning signal is used for being a lighting signal in a data writing stage of a writing frame and being a blanking signal in a data writing stage of a holding frame;
the frequency adjustment module is used for responding to the second scanning signal, being conducted in the data writing stage of the writing frame and being turned off in the data writing stage of the holding frame.
8. The display panel of claim 6, wherein the pixel circuit further comprises:
the system comprises a first initialization module and a second initialization module;
the first initialization module is connected between the compensation module and the initialization line, a control end of the first initialization module is connected with a third scanning signal, and the first initialization module is used for initializing the grid electrode of the driving transistor in a first initialization stage;
the second initialization module is connected between the anode of the light-emitting module and the initialization line, a control end of the second initialization module is connected with a fourth scanning signal, and the second initialization module is used for initializing the anode of the light-emitting module in a second initialization stage.
9. The display panel of claim 6, wherein the pixel circuit further comprises:
the control ends of the first light-emitting control module and the second light-emitting control module are connected with light-emitting control signals, and the first light-emitting control module is connected between the first power supply voltage input end and the first node;
the second light-emitting control module is connected between a second node and the anode of the light-emitting module, and the cathode of the light-emitting module is electrically connected with a second power supply voltage input end;
preferably, the pixel circuit further includes: and the storage module is connected between the first power supply voltage input end and the third node.
10. A display device, comprising: the display panel of any one of claims 1 to 9.
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| CN202310340050.3A CN116363998A (en) | 2023-03-30 | 2023-03-30 | Display panel and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117437880A (en) * | 2023-12-20 | 2024-01-23 | 维信诺科技股份有限公司 | Display device and control method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117437880A (en) * | 2023-12-20 | 2024-01-23 | 维信诺科技股份有限公司 | Display device and control method thereof |
| CN117437880B (en) * | 2023-12-20 | 2024-06-11 | 维信诺科技股份有限公司 | Display device and control method thereof |
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