CN115421687A - Optical adder, chip and computing equipment - Google Patents

Abstract

The application provides an optical adder, a chip and a computing device. The optical adder includes a first adder and a second adder. The first adder is configured to perform a first addition operation on a first input signal. The first adder includes a first carry output layer. The first carry output layer is configured to output a first carry signal. The first carry signal is obtained by a first addition operation. The second adder is configured to perform a second addition operation on the first carry signal and the second input signal. The second adder includes a second carry input layer. The second carry input layer is configured to receive the first carry signal. The positions of the first carry output layer and the second carry input layer in the light field coincide. The method and the device reduce the number of modulation layers and the occupied space required by the optical adder in the chip, and effectively control the propagation distance of the input signal and the output signal of each adder.

Description

Optical adder, chip and computing equipment

Technical Field

The present application relates to, but is not limited to, the field of optical neural networks, and in particular, to an optical adder, a chip, and a computing device.

Background

Currently, an Optical Neural Network (ONN) can be used to implement operations on optical signals, and is usually integrated in a chip. In particular, the optical neural network can realize the function of an adder that adds optical signals. In this case, as an adder, the optical neural network may receive an input signal and a carry input signal at an input layer, perform an addition operation on the input signal and the carry input signal using a modulation layer, and output an output signal and a carry output signal at an output layer.

When two or more adders based on the optical neural network in a chip are cascaded, since a carry signal output by a previous adder needs to reach a next adder, an output layer of the previous adder needs to be aligned with an input layer of the next adder. As such, these cascaded adders require a staggered layer overlap. This results in a waste of space in the chip and an increase in the number of modulation layers, and the input signal or output signal of the partial adder needs to travel a longer distance.

In view of the above, the present application aims at how to achieve an efficient concatenation of adders based on optical neural networks.

Disclosure of Invention

The application provides an optical adder, a chip and a computing device, which are used for realizing efficient cascade connection of adders based on an optical neural network.

According to a first aspect of the present application, an optical adder is provided. The optical adder includes a first adder and a second adder. The first adder is configured to perform a first addition operation on a first input signal. The first adder includes a first carry output layer. The first carry output layer is configured to output a first carry signal. The first carry signal is obtained by a first addition operation. The second adder is configured to perform a second addition operation on the first carry signal and the second input signal. The second adder includes a second carry input layer. The second carry input layer is configured to receive the first carry signal. The positions of the first carry output layer and the second carry input layer in the optical field are overlapped.

In some possible embodiments, the first adder further comprises a first input signal layer and a first output signal layer. The first input signal layer is configured to receive a first input signal. The first output signal layer is configured to output a first bitsum signal. The first bitwise sum signal is obtained by a first addition operation. The second adder also includes a second input signal layer and a second output signal layer. The second input signal layer is configured to receive a second input signal. The second output signal layer is configured to output a second bitsum signal. The second bitwise sum signal is obtained by a second addition operation.

In some possible embodiments, the first input signal layer is aligned with the second input signal layer in position in the optical field; the first output signal layer is aligned with the second output signal layer in position in the optical field.

In some possible embodiments, the first adder and the second adder are each implemented using an independently trained optical neural network.

In some possible embodiments, the first carry output layer and the second carry input layer are disposed at a modulation layer in the optical neural network.

In some possible embodiments, the second adder further comprises a second carry output layer. The second carry output layer is configured to output a second carry signal. The second carry signal is obtained by a second addition operation.

In some possible embodiments, the optical adder further comprises a third adder. The third adder is configured to perform a third addition operation on the second carry signal and the third input signal. The third adder includes a third carry input layer. The third carry input layer is configured to receive a second carry signal. The second carry output layer coincides with the third carry input layer in position in the light field.

In some possible embodiments, the third adder further comprises a third input signal layer and a third output signal layer. The third input signal layer is configured to receive a third input signal. The third output signal layer is configured to output a third bitsum signal. The third bitwise sum signal is derived by a third addition operation.

In some possible embodiments, the third adder is implemented using an independently trained optical neural network.

According to a second aspect of the present application, a chip is provided. The chip comprises an optical adder as described in the first aspect and any embodiments thereof.

According to a third aspect of the present application, a computing device is provided. The above-mentioned computing device comprises a chip as described in the second aspect.

The technical scheme provided by the application can comprise the following beneficial effects:

in the application, in two or more cascaded adders, the positions of a carry output layer for outputting carry signals in the previous-stage adder and the positions of a carry input layer for inputting the carry signals in the next-stage adder coincide, so that staggered-layer superposition among the adders is not needed, and the increase of the number of modulation layers in a chip and the waste of space are avoided. Therefore, the number of modulation layers and occupied space required by the realization of the optical adder in a chip are reduced, and the propagation distance of the input signal and the output signal of each adder is effectively controlled.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic diagram of a logic structure of a cascade of 4 adders in the related art;

FIG. 2 is a schematic diagram of an optical neural network according to the related art;

FIG. 3 is a schematic diagram of a related art adder based on an optical neural network;

FIG. 4 is a schematic diagram of an optical adder formed by two adders in the related art;

fig. 5 is a schematic structural diagram of an adder based on an optical neural network in an embodiment of the present application;

FIG. 6 is a schematic structural diagram of an optical adder according to an embodiment of the present application;

FIG. 7 is a schematic diagram of another optical adder according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of another optical adder in the embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as structures, devices, and techniques, in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present teachings may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known structures, devices, and methods are omitted so as not to obscure the description of the embodiments of the present application with unnecessary detail.

The adder is a basic logic operation unit in the computing device and is used for realizing addition operation. Adders can be divided into two categories, namely full adders and half adders. For a full adder, the input signal includes an addend, and a low carry, and the output signal includes a sum (or known as a local sum) and a carry. Therefore, the full adder is also called a band-advance adder. For a half adder, the input signal includes an addend and an addend, and the output signal includes a sum and a carry. Thus, a half adder is also referred to as a no-carry adder.

The number of bits of the input addend and addend, and the number of bits of the output sum are limited for a single adder. For example, the number of input bits of a single adder may be 1, 2, 3, 4, and the number of output bits may be 1, 2, 3, 4, respectively. Thus, to achieve summation between larger values, multiple adders may be cascaded to obtain adders with a greater number of input bits and output bits.

Fig. 1 is a schematic diagram of a logic structure of a cascade of 4 adders in the related art. As shown in fig. 1, 4-bit adders ADD1, ADD2, ADD3, ADD4 constitute a 16-bit adder. The 4 adders ADD1, ADD2, ADD3 and ADD4 are all full adders. The carry output terminal Cout1 of the adder ADD1 is connected to the carry input terminal Cin2 of the adder ADD2, the carry output terminal Cout2 of the adder ADD2 is connected to the carry input terminal Cin3 of the adder ADD3, and the carry output terminal Cout3 of the adder ADD3 is connected to the carry input terminal Cin4 of the adder ADD 4. In this way, the carry number transmission among the 4 adders ADD1, ADD2, ADD3 and ADD4 is realized, so that the 4 adders ADD1, ADD2, ADD3 and ADD4 form a 16-bit adder. The addend input a of the 16-bit adder has 16 bits. Specifically, the addend input terminal of the adder ADD1 constitutes the lower 4 bits of the addend input terminal of the 16-bit adder, i.e., a [3 ]; the addend input end of the adder ADD2 forms the next lower 4 bits of the addend input end of the 16-bit adder, namely A [7 ]; the addend input end of the adder ADD3 forms the next highest 4 bits of the addend input end of the 16-bit adder, namely A [11 ]; the addend input of adder ADD4 forms the upper 4 bits of the addend input of the 16-bit adder, i.e., a [ 15. The summand input B of the 16-bit adder has 16 bits. Specifically, the addend input terminal of the adder ADD1 constitutes the lower 4 bits of the addend input terminal of the 16-bit adder, i.e., B [3 ]; the summand input end of the adder ADD2 forms the second lowest 4 bits of the summand input end of the 16-bit adder, namely B [7 ]; the summand input end of the adder ADD3 forms the second highest 4 bits of the summand input end of the 16-bit adder, namely B [11 ]; the summand input of adder ADD4 constitutes the upper 4 bits of the summand input of the 16-bit adder, namely B [ 15. The carry input terminal Cin1 of the adder ADD1 constitutes a carry input terminal of the 16-bit adder, and the carry output terminal Cout4 of the adder ADD4 constitutes a carry output terminal of the 16-bit adder. The sum outputs of the adders ADD1, ADD2, ADD3, ADD4 constitute the lower 4, next upper 4 and upper 4 bits, respectively, of the sum output of the 16-bit adder, namely S [3 ], S [7 ], S [ 4], S [11 ], S [ 8], S [ 15.

It should be noted that the cascade of 4 adders shown in fig. 1 is merely illustrative. In practical application, the number of cascaded adders and the number of bits at the addend input end and the addend input end of each adder may be set according to practical requirements, which is not limited in the present application.

The existing adder may be implemented by a circuit. In the circuit, the carry of the cascaded adders is transmitted in the form of an electrical signal via electrical wiring. Thus, the electrical wiring for transferring the carry-ins can be arranged arbitrarily, and does not substantially occupy additional space, while satisfying the electrical requirements of the circuit.

However, the above adder may also be implemented by an optical neural network. Fig. 2 is a schematic structural diagram of an optical neural network in the related art. As shown in fig. 2, the optical neural network may include at least an input layer Lin, at least one modulation layer Lmod, and an output layer Lout.

The input layer Lin is for receiving light and propagating the received light to the at least one modulation layer Lmod. The light carries data. Here, the light may be coherent light, and may be incident to the input layer Lin in a direction perpendicular to the input layer Lin. At least one modulation layer Lmod is used to implement the calculations based on the above data. In particular, each stage of the modulation layer Lmod may include a plurality of modulation blocks, each of which may phase-modulate light incident thereon. Thus, after the last stage of the modulation layer Lmod, the calculation is completed. The output layer Lout is used to output light from the modulation layer Lmod.

It should be noted that each modulation block in the modulation layer Lmod may have different or the same phase modulation on light; and the degree of phase modulation of each modulation block is adjustable. For example, one modulation block may perform phase modulation in a range of 0 degrees to 360 degrees (i.e., 0 to 2 π). The above process of adjusting the degree of phase modulation of each modulation block in the modulation layer Lmod may be referred to as a training process of the optical neural network.

As can be seen, in the optical neural network shown in fig. 2, the propagation direction of light is constant, i.e., the propagation direction is along the direction of the input layer Lin, the modulation layer Lmod, and the output layer Lout. Changing the propagation direction of light inevitably causes additional losses to the light. Further, since the modulation layer Lmod performs calculation by phase-modulating the light, any change in the phase of the light affects the result of the calculation. Therefore, the propagation distance of the light also needs to be controlled to avoid negatively affecting the phase of the light. In the optical neural network, the input layer may also be referred to as an input plane (input plane); the modulation layer may also be referred to as a diffraction layer; the output layer may also be referred to as an output plane (output plane).

It should be noted that the optical neural network shown in fig. 2 is only schematic. In practical applications, the number of modulation layers in the optical neural network and the number of modulation blocks in each modulation layer may be set according to actual requirements, which is not limited in this application.

Fig. 3 is a schematic structural diagram of an adder based on an optical neural network in the related art. In fig. 3, the adder is a 4-bit full adder as an example. As shown in fig. 3, the adder includes an input layer Lin, 3 modulation layers Lmod, and an output layer Lout. The input layer Lin includes a carry input layer Cin, and an input signal layer Sin. The output layer Lout includes an output signal layer Sout and a carry output layer Cout. The input signal layer Sin can receive an input signal of 4 bits, and the output signal layer Sout can output an output signal of 4 bits. It is understood that, since the output signal output by the output signal layer Sout is the sum of the input signals of the input signal layer Sin, the output signal may also be referred to as a local sum signal. Based on the training process for the optical neural network, the training of the adder based on the optical neural network in fig. 3 can be realized.

It should be noted that the adder shown in fig. 3 is merely illustrative. In practical application, the number of bits of the input signal, the number of bits of the output signal, and the number of modulation layers in the adder may be set according to practical requirements, which is not limited in this application.

When two or more trained adders are cascaded, if the input layers and the output layers of the adders are respectively aligned, light output by the carry output layer of the previous adder needs to be propagated backward from the output layer to the carry input layer of the next adder located at the input layer. However, trained adders cannot achieve this back-propagation without loss of light. Therefore, when implementing the cascade connection of adders based on the optical neural network, in order to implement the transfer of carry between adders at respective stages, adders at respective stages need to be added in a staggered manner.

Fig. 4 is a schematic structural diagram of an optical adder composed of two 4-bit adders in the related art. As shown in fig. 4, the adder ADD1 and the adder ADD2 are hierarchically superimposed. The output layer Lout1 of the adder ADD1 is aligned with the input layer Lin2 of the adder ADD 2. In this way, the carry output layer Cout1 of ADD1 coincides with the position of the carry input layer Cin2 of ADD2 in the light field.

However, the optical adder shown in fig. 4 has the following problems:

(1) Optical neural network based adders are typically integrated in a chip. The portions of block 01 and block 02 shown in fig. 4 are free space. Because the adder ADD1 and the adder ADD2 do not occupy a large empty space, the space in the chip where the optical adder is located is wasted, and the integration level is reduced.

(2) The input signals of the optical adder need to be incident in the same plane, and the output signals need to be incident in the same plane. Due to the existence of the empty spaces shown in the above blocks 01 and 02, both the output light of the adder ADD1 and the input light of the adder ADD2 need to travel over a longer distance, resulting in a change in the phase of the input light and the output light.

(3) Due to the staggered superposition of the adder ADD1 and the adder ADD2, the modulation layers of the two are independent and misaligned. Therefore, the number of modulation layers of the optical adder is larger than the number of modulation layers of either of the adder ADD1 and the adder ADD 2.

It should be noted that the above problem exists in an optical adder formed by cascading any number of optical neural network-based adders in a staggered-layer superposition manner, not only in the optical adder shown in fig. 4.

In order to solve the above problem, embodiments of the present application provide an optical adder. The optical adder includes a first adder and a second adder. The first adder is configured to perform a first addition operation on a first input signal. The first adder includes a first carry output layer. The first carry output layer is configured to output a first carry signal. The first carry signal is obtained by a first addition operation. The second adder is configured to perform a second addition operation on the first carry signal and the second input signal. The second adder includes a second carry input layer. The second carry input layer is configured to receive the first carry signal. The positions of the first carry output layer and the second carry input layer in the optical field are overlapped. Therefore, the adders do not need to be superposed in a staggered mode, and the increase of the number of modulation layers in a chip and the waste of space are avoided. Therefore, the number of modulation layers and the occupied space required for realizing the optical adders in a chip are reduced, and the propagation distances of the input signals and the output signals of the adders are effectively controlled.

In order to explain the technical solution described in the present application, the following description will be given by way of specific examples.

The embodiment of the application provides an adder based on an optical neural network. The adder may be a full adder or a half adder.

In some possible implementations, the adder may be a full adder. In this case, the adder may include an input signal layer, a carry input layer, a plurality of modulation layers, an output signal layer, and a carry output layer. The carry input layer is aligned with the input signal layer or located at one of the plurality of modulation layers. The carry output layer is aligned with the output signal layer or located at one of the plurality of modulation layers. The distance between the carry input layer and the signal input layer is smaller than the distance between the carry output layer and the signal input layer.

In an embodiment, the carry input layer may be located at the first modulation layer, and the carry output layer may be located at the second modulation layer. The first modulation layer may be a modulation layer located one stage or several stages before the second modulation layer. In an embodiment, the carry input layer may be aligned with the input signal layer, and the carry output layer may be located at the second modulation layer. In an embodiment, the carry input layer may be located at the first modulation layer, and the carry output layer may be aligned with the signal output layer. It is to be understood that the first modulation layer may be any one of the plurality of modulation layers except for the last-stage modulation layer, and the second modulation layer may be any one of the plurality of modulation layers except for the first-stage modulation layer.

In some possible embodiments, the adder may be a half adder. In this case, the adder may include an input signal layer, a plurality of modulation layers, an output signal layer, and a carry output layer. The carry output layer is aligned with the output signal layer or located at one of the plurality of modulation layers. It is to be understood that the carry output layer may be any one of the plurality of modulation layers other than the first-stage modulation layer.

In some possible implementations, the adder may include an input signal layer, a carry input layer, a plurality of modulation layers, and an output signal layer. The carry input layer is aligned with the input signal layer or located at one of the plurality of modulation layers. It is to be understood that the carry-in layer may be any one of the plurality of modulation layers except the last one.

Fig. 5 is a schematic structural diagram of an adder based on an optical neural network in an embodiment of the present application. As shown in fig. 5, the adder ADD, and includes an input layer Lin, a modulation layer Lmod, and an output layer Lout. The input signal layer Sin is in the input layer Lin. The output signal layer Sout is in the output layer Lout.

With further reference to fig. 5, the modulation layer Lmod comprises 4 modulation layers Lmod, respectively a first modulation layer Lmod1, a second modulation layer Lmod2, a third modulation layer Lmod3 and a fourth modulation layer Lmod4. The carry input layer Cin is located at the second modulation layer Lmod 2. The carry output layer Cout is located at the third modulation layer Lmod 3.

It should be noted that the structure of the adder shown in fig. 5 is merely illustrative. In the adder based on the optical neural network according to the embodiment of the present application, the number of the modulation layers, the position of the carry input layer, and the position of the carry output layer may all be set according to actual requirements, which is not limited in the present application.

According to an embodiment of the present application, there is further provided an optical adder. The optical adder is composed of two or more adders based on the optical neural network.

Fig. 6 is a schematic structural diagram of an optical adder according to an embodiment of the present application. As shown in fig. 6, the optical adder includes an input layer Lin, an output layer Lout, and 5 modulation layers Lmod1, lmod2, lmod3, lmod4, lmod5. The optical adder is composed of an adder ADD1 and an adder ADD 2. The adder ADD1 includes an input signal layer Sin1, a carry input layer Cin1, an output signal layer Sout1, and a carry output layer Cout1. The adder ADD2 includes an input signal layer Sin2, a carry input layer Cin2, an output signal layer Sout2, and a carry output layer Cout2. The modulation layers Lmod1, lmod2, lmod3, lmod4, lmod5 constitute the modulation layers of the adder ADD1 and the adder ADD2 at the same time.

The signal input layer Sin1 of the adder ADD1 and the signal input layer Sin2 of the adder ADD2 are both located at the input layer Lin. The signal output layer Sout1 of the adder ADD2 and the signal output layer Sout2 of the adder ADD2 are both located at the output layer Lout. The carry input layer Cin1 of the adder ADD1 is located at the modulation layer Lmod 2. The carry output layer Cout1 of the adder ADD1 and the carry input layer Cin2 of the adder ADD2 are overlapped in position in the optical field, and are both located at the modulation layer Lmod 3. The carry output layer Cout2 of the adder ADD2 is located at the modulation layer Lmod4.

It can be understood that the carry output layer Cout1 of the adder ADD1 and the carry input layer Cin2 of the adder ADD2 have substantially the same spatial arrangement, light field distribution, phase relationship. Therefore, the carry signal output by the adder ADD1 at the carry output layer Cout1 can be used as the carry signal input by the adder ADD2 at the carry input layer Cout2.

The adder ADD1 in fig. 6 may be referred to as a first adder, and the adder ADD2 may be referred to as a second adder.

Fig. 7 is a schematic structural diagram of another optical adder in the embodiment of the present application. As shown in fig. 7, the optical adder includes an input layer Lin, an output layer Lout, and 5 modulation layers Lmod1, lmod2, lmod3, lmod4, lmod5. The optical adder is composed of an adder ADD1, an adder ADD2, and an adder ADD3. The modulation layers Lmod1, lmod2, lmod3, lmod4, lmod5 simultaneously constitute the modulation layers of the adder ADD1, the adder ADD2 and the adder ADD3.

The adder ADD1 is a half adder. The adder ADD1 includes an input signal layer Sin1, an output signal layer Sout1, and a carry output layer Cout1. The signal input layer Sin1 of the adder ADD1 is located at the input layer Lin of the optical adder. The signal output layer Sout1 of the adder ADD1 is located at the output layer Lout of the optical adder. The carry output layer Cout1 of the adder ADD1 is located at the modulation layer Lmod3 of the optical adder.

The adder ADD2 is a full adder. The adder ADD2 includes an input signal layer Sin2, a carry input layer Cin2, an output signal layer Sout2, and a carry output layer Cout2. The signal input layer Sin2 of the adder ADD2 is located at the input layer Lin of the optical adder. The signal output layer Sout2 of the adder ADD2 is located at the output layer Lout of the optical adder. The carry input layer Cin2 of the adder ADD2 is located at the modulation layer Lmod3 of the optical adder. The carry output layer Cout2 of the adder ADD2 is located at the modulation layer Lmod4 of the optical adder.

The adder ADD3 is a full adder. The adder ADD3 includes an input signal layer Sin3, a carry input layer Cin3, and an output signal layer Sout3. The signal input layer Sin3 of the adder ADD3 is located at the input layer Lin of the optical adder. The signal output layer Sout3 of the adder ADD3 is located at the output layer Lout of the optical adder. The carry-in layer Cin3 of the adder ADD3 is located at the modulation layer Lmod4 of the optical adder.

The carry output layer Cout1 of the adder ADD1 coincides with the carry input layer Cin2 of the adder ADD2 at the position of the light field. The carry output layer Cout2 of the adder ADD2 coincides with the carry input layer Cin3 of the adder ADD3 in position of the light field.

As can be appreciated, the carry output layer Cout1 of the adder ADD1 and the carry input layer Cin2 of the adder ADD2 have substantially the same spatial arrangement, light field distribution, phase relationship, and the carry signal output by the adder ADD1 at the carry output layer Cout1 can therefore be used as the carry signal input by the adder ADD2 at the carry input layer Cin 2. Likewise, the carry output layer Cout2 of the adder ADD2 and the carry input layer Cin3 of the adder ADD3 have substantially the same spatial arrangement, light field distribution, phase relationship, and the carry signal output by the adder ADD2 at the carry output layer Cout2 can thus be used as the carry signal input by the adder ADD3 at the carry input layer Cin 3.

Note that the adder ADD3 shown in fig. 7 has a carry input layer Cin3, but does not have a carry output layer. However, ADD3 may also have a carry-out layer in some possible implementations.

The adder ADD1 in fig. 7 may be referred to as a first adder, and the cascade of the adders ADD2 and ADD3 may be referred to as a second adder. Thus, the input signal layers Cin2 and Cin3 of the adders ADD2 and ADD3 constitute a second signal input layer, and the output signal layer Cout2 and the output signal layer (not shown) of the adder ADD3 constitute a second signal output layer. The carry input stage Cin2 of the adder ADD2 constitutes a second carry input stage. The carry output layer of the adder ADD3 constitutes a second carry output layer.

Fig. 8 is a schematic structural diagram of another optical adder in the embodiment of the present application. As shown in fig. 8, the optical adder includes an input layer Lin, an output layer Lout, and M modulation layers Lmod1, lmod2, 8230 \8230;, lmodM. The optical adder is composed of N +1 adders including adder ADD1, adder ADD21, adder ADD22, adder 8230, adder 8230and adder ADD2N. M is a positive integer, and N is a positive integer greater than 2. M modulation layers Lmod1, lmod2, and/or 8230, and Lmod M constitute modulation layers of the adders ADD1, ADD21, and/or 8230, and ADD2N.

The adder ADD1 is a half adder. The adder ADD1 includes an input signal layer Sin1, an output signal layer Sout1, and a carry output layer Cout1. The signal input layer Sin1 of the adder ADD1 is located at the input layer Lin of the optical adder. The signal output layer Sout1 of the adder ADD is located at the output layer Lout of the optical adder.

Adder ADD2k is a full adder, where 1 ≦ k < N. The adder ADD2k includes an input signal layer Sin2k, a carry input layer Cin2k, and output signal layers Sout2k and a carry output layer Cout2k. The signal input layer Sin2k of the adder ADD2k is located at the input layer Lin of the optical adder. The signal output layer Sout2k of the adder ADD2k is located at the output layer Lout of the optical adder.

The adder ADD2N is a full adder. The adder ADD2N includes an input signal layer Sin2N, a carry input layer Cin2N, and an output signal layer Sout2N. The signal input layer Sin2N of the adder ADD2N is located at the input layer Lin of the optical adder. The signal output layer Sout2N of the adder ADD2N is located at the output layer Lout of the optical adder.

The adder ADD1 in fig. 8 may be referred to as a first adder, and the cascade of the adders ADD21, ADD22, 8230\8230and ADD2N may be referred to as a second adder. Thus, each of the adders ADD21, ADD22, \8230;, ADD2N may be referred to as a sub-adder.

In the adders ADD21, ADD22, 8230- \8230:, ADD2N, a carry input layer Cin2i of the adder ADD2i (2 ≦ i ≦ N) is located at a specific modulation layer among M modulation layers Lmod1, lmod2, \8230;, lmodM, and the modulation layer where the carry input layer Cin2i of the adder ADD2i is located more backward with respect to the modulation layer where the carry input layer Cin2 (i-1) of the adder ADD2 (i-1) of the previous stage is located, and the two modulation layers differ by one stage or more. The carry input layer Cin2i of the adder ADD2i and the carry output layer Cout2 (i-1) of the adder ADD2 (i-1) overlap in position. It will be appreciated that the carry input stage Cin21 of the adder ADD21 coincides with the carry output stage Cout1 of the adder ADD 1. Therefore, for the adder ADD2i, the distance between the carry input layer Cin2i and the input layer Lin (i.e., the second input signal layer Sout 2) is smaller than the distance between the carry output layer Cout2i and the input layer Lin.

As can be appreciated, the carry output layer Cout1 of the adder ADD1 and the carry input layer Cin21 of the adder ADD21 have substantially the same spatial arrangement, light field distribution, phase relationship, and the carry signal output by the adder ADD1 at the carry output layer Cout1 can therefore be used as the carry signal input by the adder ADD21 at the carry input layer Cout 21. Likewise, the carry input layer Cin2i of the adder ADD2i and the carry output layer Cout2 (i-1) of the adder ADD2 (i-1) have substantially the same spatial arrangement, light field distribution, phase relationship, and the carry signal output by the adder ADD2 (i-1) at the carry output layer Cout2 (i-1) can be used as the carry signal input by the adder ADD2i at the carry input layer Cin2 i.

It will be appreciated that in some possible embodiments, the adder ADD2N may also include a carry output layer (not shown).

The adder ADD1 in fig. 8 may be referred to as a first adder, and the cascade of the adders ADD21, ADD22, 8230\8230and ADD2N may be referred to as a second adder. Accordingly, the adders ADD21, ADD22, 8230, cin21, cin22, 8230, cin2N constitute the second signal input layer, and the output signal layers Cout21, cout22, 8230, and Cout2N constitute the second signal output layer. The carry input layer Cin21 of the adder ADD21 constitutes a second carry input layer, and the carry output layer of the adder ADD2N constitutes a second carry output layer.

The structures of the optical adders shown in fig. 6, 7 and 8 are merely exemplary. In the optical adder in the embodiment of the present application, the following contents may be set according to actual requirements: the number of cascaded adders, the number of bits of each adder, whether the adder is a full adder or a half adder, whether the last-stage adder has a carry output layer, the number of modulation layers, whether the carry input layer of the first-stage adder is at the input layer or the modulation layer, whether the carry output layer of the last-stage adder is at the modulation layer or the output layer, and the modulation layer where the carry input layer and the carry output layer of each adder are located.

Based on the same inventive concept, the embodiment of the application also provides a chip. The chip comprises the optical adder.

Based on the same inventive concept, the embodiment of the application also provides the computing device. The computing device comprises the chip.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (11)

1. An optical summer, comprising:

a first adder configured to perform a first addition operation on a first input signal, wherein the first adder includes a first carry output layer configured to output a first carry signal, the first carry signal resulting from the first addition operation;

a second adder configured to perform a second addition operation on the first carry signal and a second input signal, wherein the second adder includes a second carry input layer configured to receive the first carry signal;

wherein, the positions of the first carry output layer and the second carry input layer in the light field are overlapped.

2. The optical adder according to claim 1, wherein the first adder further comprises:

a first input signal layer configured to receive the first input signal;

a first output signal layer configured to output a first bit sum signal, wherein the first bit sum signal is obtained by the first addition operation;

and wherein the second adder further comprises:

a second input signal layer configured to receive the second input signal;

a second output signal layer configured to output a second bitwise sum signal, wherein the second bitwise sum signal is a result of the second addition operation.

3. The optical adder according to claim 2, wherein the first input signal layer is aligned with the second input signal layer in position in the optical field; the first output signal layer is aligned with the second output signal layer in position in the optical field.

4. The optical summer of claim 1, wherein the first summer and the second summer are each implemented using independently trained optical neural networks.

5. The optical adder according to claim 4, wherein the first carry output layer and the second carry input layer are disposed at a modulation layer in the optical neural network.

6. The optical adder according to any one of claims 1 to 5, wherein the second adder further comprises:

a second carry output layer configured to output a second carry signal, wherein the second carry signal is obtained by the second addition operation.

7. The optical adder according to claim 6, further comprising:

a third adder configured to perform a third addition operation on the second carry signal and a third input signal, wherein the third adder includes a third carry input layer configured to receive the second carry signal;

wherein the second carry output layer coincides with the third carry input layer in position in the light field.

8. The optical adder according to claim 7, wherein the third adder further comprises:

a third input signal layer configured to receive the third input signal;

a third output signal layer configured to output a third bit sum signal, wherein the third bit sum signal is obtained by the third addition operation.

9. The optical adder according to claim 7, wherein the third adder is implemented using an independently trained optical neural network.

10. A chip comprising an optical adder according to any one of claims 1 to 9.

11. A computing device comprising the chip of claim 10.

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