CN114724490B - GOA circuit and display device - Google Patents
GOA circuit and display device Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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Abstract
The invention discloses a GOA circuit and display equipment, and the main technical scheme comprises the following steps: the GOA circuit comprises: a signal supply circuit for supplying a reset control signal to the row data reset circuit and a refresh control signal to the row data write circuit; the data processor is used for respectively issuing control instructions corresponding to the refreshing requirements of the pixel circuit to the row data reset circuit and the row data write-in circuit, and the refreshing requirements are used for reflecting whether the pixel circuit needs to be refreshed or not; the row data reset circuit is used for carrying out first transmission processing on the reset control signal according to a control instruction issued by the data processor so as to enable the pixel circuit to execute operation corresponding to a processing result of the first transmission processing; and the row data writing circuit is used for carrying out second transmission processing on the refreshing control signal according to the control command issued by the data processor so as to enable the pixel circuit to execute the operation corresponding to the processing result of the second transmission processing.
Description
Technical Field
The invention relates to the technical field of display, in particular to a GOA circuit and display equipment.
Background
A Gate On Array (GOA) display device is generally provided with a signal supply circuit and a pixel circuit. When the display device performs display refresh, a row-by-row refresh mode is usually adopted. The row-by-row refreshing is that the signal providing circuit outputs a refreshing control signal and a reset control signal of each row of pixel circuits in the display device, so that each row of pixel circuits is controlled to be refreshed in sequence.
At present, in the row-by-row refresh mode, all pixel circuits in the display device need to be refreshed, and even if some pixel circuits do not need to be refreshed, the refresh operation is performed. It can be seen that the existing row-by-row refreshing mode cannot independently control whether a certain row of pixel circuits is refreshed or not.
Disclosure of Invention
In view of the above, the present invention provides a GOA circuit and a display device, and the main objective of the invention is to individually control whether a row of pixel circuits is refreshed or not.
In order to achieve the above purpose, the present invention mainly provides the following technical solutions:
in a first aspect, the present invention provides a GOA circuit, including: the device comprises a signal providing circuit, a data processor, a row data resetting circuit and a row data writing circuit; the row data reset circuit is respectively connected with the pixel circuit, the signal supply circuit and the data processor; the line data writing circuit is respectively connected with the pixel circuit, the signal providing circuit and the data processor;
the signal providing circuit is used for providing a reset control signal for the row data reset circuit and providing a refresh control signal for the row data writing circuit;
the data processor is used for respectively issuing control instructions corresponding to the refreshing requirements of the pixel circuit to the row data reset circuit and the row data write-in circuit, and the refreshing requirements are used for reflecting whether the pixel circuit needs to be refreshed or not;
the row data reset circuit is used for carrying out first transmission processing on the reset control signal according to a control instruction issued by the data processor so as to enable the pixel circuit to execute operation corresponding to a processing result of the first transmission processing;
and the row data writing circuit is used for carrying out second transmission processing on the refreshing control signal according to a control instruction issued by the data processor so as to enable the pixel circuit to execute operation corresponding to a processing result of the second transmission processing.
In a second aspect, the present invention provides a display apparatus comprising: the GOA circuit of the first aspect.
By means of the technical scheme, the GOA circuit comprises a signal providing circuit, a data processor, a row data resetting circuit and a row data writing circuit. The data processor respectively issues control instructions corresponding to the refreshing requirements of the pixel circuit to the row data reset circuit and the row data writing circuit. The row data reset circuit carries out first transmission processing on the reset control signal provided by the signal providing circuit according to the control instruction issued by the data processor, so that the pixel circuit executes the operation corresponding to the processing result of the first transmission processing. And the row data writing circuit carries out second transmission processing on the refresh control signal provided by the signal providing circuit according to the control command issued by the data processor, so that the pixel circuit executes the operation corresponding to the processing result of the second transmission processing. Therefore, in the scheme provided by the invention, the data processor can control whether the row data reset circuit transmits the reset control signal to the pixel circuit or not according to the refreshing requirement of the pixel circuit, and control whether the row data write-in circuit transmits the refreshing control signal to the pixel circuit or not, so as to control whether the pixel circuit is refreshed or not. Therefore, the scheme provided by the invention can independently control whether the pixel circuit in one row is refreshed or not.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of a GOA circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a pixel circuit according to another embodiment of the invention;
FIG. 3 is a diagram illustrating a timing diagram of a variation of a pulse signal according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a GOA circuit according to another embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a timing diagram of a change of a pulse signal according to another embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As shown in fig. 1, an embodiment of the present invention provides a GOA circuit, which mainly includes: a signal supply circuit 11, a data processor 12, a line data reset circuit 13, and a line data write circuit 14.
The connection relation related to the GOA circuit is as follows: the line data reset circuit 13 is connected to the pixel circuit 10, the signal supply circuit 11, and the data processor 12, respectively. The line data writing circuit 14 is connected to the pixel circuit 10, the signal supply circuit 11, and the data processor 12, respectively.
The interaction relation involved by the above-mentioned GOA circuit is as follows:
a signal supply circuit 11 for supplying a reset control signal to the row data reset circuit 13 and a refresh control signal to the row data write circuit 14.
And the data processor 12 is configured to issue control instructions corresponding to refresh requirements of the pixel circuit 10 to the row data reset circuit 13 and the row data write circuit 14, where the refresh requirements are used to indicate whether the pixel circuit 10 needs to be refreshed or not.
And a row data reset circuit 13, configured to perform a first transmission process on the reset control signal according to a control instruction issued by the data processor 12, so that the pixel circuit 10 performs an operation corresponding to a processing result of the first transmission process.
And the row data writing circuit 14 is configured to perform a second transmission process on the refresh control signal according to the control instruction issued by the data processor 12, so that the pixel circuit 10 performs an operation corresponding to a processing result of the second transmission process.
The following is a detailed description of the components involved in the GOA circuit shown in fig. 1:
the pixel circuit 10:
a plurality of rows of pixel circuits 10 are included in the display device, and the display of the display device is performed by each row of pixel circuits 10. The pixel circuit 10 includes a data refresh control terminal and a data reset control terminal. The refresh operation of the pixel circuit is completed by the reset control signal received by the data reset control terminal and the refresh control signal received by the data refresh control terminal, so that whether the pixel circuit is refreshed or not can be controlled by controlling the transmission of the reset control signal to the data reset control terminal and the transmission of the refresh control signal to the data refresh control terminal.
As shown in fig. 2, fig. 2 shows a pixel circuit, which includes: the transistor M1, the transistor M2, the transistor M3, the transistor M4, the transistor M5, the transistor M6, the capacitor C, the light emitting element P, the first power supply terminal ELVDD1, the second power supply terminal ELVDD2 (ELVDD 2 is used to stabilize the voltage of the capacitor C), the data signal terminal Vdata, the initialization voltage terminal Vinit, the ground terminal ELVSS, the control signal terminal EM, the data refresh control terminal, and the data reset control terminal.
The data reset control terminal is used for receiving a reset control signal and controlling the transistor M5 to be turned on under the reset control signal. The voltage of the capacitor C in the pixel circuit 10 after the transistor M5 is turned on is reset to the initialization voltage by the voltage supplied from Vinit. The data refresh control terminal is used for receiving a refresh control signal and controlling the transistors M1 and M4 to be turned on after the voltage of the capacitor C is reset to the initialization voltage under the refresh control signal. The data signal terminal Vdata supplies a data voltage, and the transistor M3 transmits a current to the capacitor C under the action of the data voltage and the voltage stored in the capacitor C, so that the capacitor C stores a voltage required for the light emission of the light emitting element P based on the data voltage supplied from the data signal terminal Vdata on the basis of the initialization voltage. In addition, after the pixel circuit 10 stores the voltage required for the light emitting element P to emit light in the capacitor C, the control signal terminal EM controls the transistors M2 and M6 to be turned on, and the driving voltage terminal ELVDD1 supplies the driving voltage. The transistor M3 transmits a driving current to the light emitting element P through the transistor M3 under the action of the driving voltage and the voltage stored in the capacitor C, so that the light emitting element emits light at the driving current.
The signal supply circuit 11:
the signal supply circuit 11 is configured to supply a reset control signal and a refresh control signal to refresh the pixel circuits 10 of each row according to the reset control signal and the refresh control signal.
The reset control signal, which is a pulse signal having timing variations, is used to control the pixel circuit 10 to be reset. Illustratively, as shown in fig. 3, fig. 3 is a timing diagram of pulse signal change, and a line segment a in fig. 3 represents a level timing change of the reset control signal at the data reset control terminal. When the reset control signal reaches the data reset control terminal of the pixel circuit 10 shown in fig. 2, the line segment a is at a low level in the region T1, the transistor M5 is turned on in the timing sequence corresponding to the region T1, and the voltage of the capacitor C in the pixel circuit 10 is reset to the initialization voltage by the voltage provided by the initialization voltage terminal Vinit when the transistor M5 is turned on. After the voltage of the capacitor C is reset to the initialization voltage, in order to avoid the voltage at the initialization voltage terminal Vinit from affecting the subsequent refresh operation of the pixel circuit 10, the reset control signal enters the regions T2 and T3, the reset control signal is at a high level in the regions T2 and T3, and the transistor M5 is turned off in the timing sequence corresponding to the regions T2 and T3.
The refresh control signal is used to control the pixel circuit 10 to refresh the display, and is a pulse signal having timing variations. As shown in fig. 3, a line segment B in fig. 3 represents a level timing variation of the refresh control signal at the data refresh control terminal. When the refresh control signal reaches the data refresh control terminal of the pixel circuit 10 shown in fig. 2, the line segment B is at a high level in the region T1, and the transistor M1 and the transistor M4 are turned off in the time sequence corresponding to the region T1, thereby avoiding affecting the process of resetting the capacitor C to the initialization voltage. Then, after the voltage of the capacitor C is reset to the initialization voltage, the refresh control signal enters the region T2. The line segment B is at a low level in the region T2, the transistor M1 and the transistor M4 are turned on in a timing sequence corresponding to the region T2, the data signal terminal Vdata provides a data voltage, and the transistor M3 transmits a current to the capacitor C under the action of the driving voltage and the voltage stored in the capacitor C, so that the capacitor C stores a voltage required for the light emission of the light emitting element P based on the data voltage provided by the data signal terminal Vdata on the basis of the initialization voltage. Then, after the capacitor C performs voltage storage based on the data voltage, the refresh control signal enters the region T3. The line segment B is at a low level in the T3 region, the transistors M1 and M4 are turned off in a timing sequence corresponding to the T3 region, the control signal terminal EM controls the transistors M2 and M6 to be turned on, the driving voltage terminal ELVDD1 provides a driving voltage, and the transistor M3 transmits a driving current to the light emitting element P under the action of the driving voltage and the voltage stored in the capacitor C, so that the light emitting element emits light under the driving current.
Since the reset of the pixel circuit 10 is a precondition for the pixel circuit 10 to perform refresh display, when the pixel circuit 10 needs to perform refresh display, the reset control signal is transmitted to the pixel circuit 10 prior to the refresh control signal.
The data processor 12:
the data processor 12 is configured to issue control commands corresponding to refresh requirements of the pixel circuits 10 to the row data reset circuit 13 and the row data write circuit 14, respectively. The refresh requirement of the pixel circuit 10 is used to indicate whether the pixel circuit 10 needs to be refreshed, so the data processor 12 issues control commands to the row data writing circuit 14 and the row data resetting circuit 13 respectively based on the refresh requirement of the pixel circuit 10, and can control whether the refresh control signal and the reset control signal used for refreshing the pixel circuit 10 are transmitted to the pixel circuit 10.
Specifically, when it is determined that the refresh requirement of the pixel circuit 10 is the need for refresh, the data processor 12 issues a data refresh control command for pixel circuit refresh to the row data reset circuit 13 and the row data write circuit 14, respectively, so that the row data reset circuit 13 transmits a reset control signal for resetting the pixel circuit 10 to the pixel circuit 10, and the row data write circuit 14 transmits a refresh control signal for refresh to the pixel circuit 10.
Specifically, when it is determined that the refresh requirement of the pixel circuit 10 does not need to be refreshed, the data processor 12 issues a data non-refresh control command that the pixel circuit does not refresh to the row data write circuit 14 and the row data reset circuit 13, respectively, so that the row data reset circuit 13 does not transmit the reset control signal for resetting the pixel circuit 10 to the pixel circuit 10, and the row data write circuit 14 does not transmit the refresh control signal for refreshing to the pixel circuit 10, thereby maintaining the current state of the pixel circuit 10 and not performing a refresh operation.
The line data reset circuit 13:
the line data reset circuit 13 is configured to perform a first transmission process on the reset control signal according to a control instruction issued by the data processor 12, so that the pixel circuit 10 performs an operation corresponding to a processing result of the first transmission process. The first transmission process described herein is related to specific control issued by the data processor 12, and specific implementation conditions of the row data reset circuit 13 include the following two types:
first, the data reset circuit 13 performs a first transmission process on the reset control signal according to the control instruction issued by the data processor 12 under the data refresh control instruction issued by the data processor 12, and the first transmission process includes: the reset control signal is transmitted to the pixel circuit 10 to cause the pixel circuit 10 to perform a reset operation under the reset control signal. Specifically, the reset control signal is transmitted to the data reset control terminal of the pixel circuit 10, and the data reset control terminal performs the reset operation under the reset control signal, thereby completing the reset of the pixel circuit 10.
Secondly, the first transmission processing of the reset control signal by the row data reset circuit 13 according to the control instruction issued by the data processor 12 under the data non-refresh control instruction issued by the data processor 12 is as follows: the first sustain signal is transmitted to the pixel circuit 10 so that the pixel circuit 10 maintains the current state under the first sustain signal. Specifically, the reset control signal is not transmitted to the data reset control terminal of the pixel circuit 10, and the data reset control terminal maintains the current control action, so that the pixel circuit is not reset, and the pixel circuit is not refreshed.
The line data write circuit 14:
the line data writing circuit 14 is configured to perform a second transmission process on the refresh control signal according to the control instruction issued by the data processor 12, so that the pixel circuit 10 performs an operation corresponding to a processing result of the second transmission process. Specific implementations of the line data writing circuit 14 include the following two types:
first, the second transmission processing performed by the row data writing circuit 14 on the refresh control signal according to the control instruction issued by the data processor 12 under the data refresh control instruction issued by the data processor 12 is: the refresh control signal is transmitted to the pixel circuit 10 to cause the pixel circuit 10 to perform a refresh operation under the refresh control signal. Specifically, the refresh control signal is transmitted to the data refresh control terminal of the pixel circuit 10, and the data refresh control terminal performs the refresh operation under the refresh control signal, thereby completing the reset of the pixel circuit 10.
Second, the second transmission processing performed by the row data writing circuit 14 on the refresh control signal according to the control instruction issued by the data processor 12 under the data non-refresh control issued by the data processor 12 is: the second sustain signal is transmitted to the pixel circuit 10 so that the pixel circuit 10 maintains the current state under the second sustain signal. Specifically, the refresh control signal is not transmitted to the data refresh control terminal of the pixel circuit 10, and the data refresh control terminal maintains the current control action, so that the pixel circuit is not refreshed.
Since the reset of the pixel circuit 10 is a precondition for the pixel circuit 10 to perform refresh display, the refresh control signal is transmitted to the pixel circuit 10 after the reset control signal when the pixel circuit 10 needs to perform refresh.
According to the GOA circuit provided by the embodiment of the invention, the GOA circuit comprises a signal providing circuit, a data processor, a row data resetting circuit and a row data writing circuit. The data processor respectively issues control instructions corresponding to the refreshing requirements of the pixel circuits to the row data reset circuit and the row data write circuit. And the row data reset circuit carries out first transmission processing on the reset control signal according to a control instruction issued by the data processor so as to enable the pixel circuit to execute operation corresponding to a processing result of the first transmission processing. And the row data writing circuit carries out second transmission processing on the refresh control signal according to a control command issued by the data processor so as to enable the pixel circuit to execute operation corresponding to a processing result of the second transmission processing. Therefore, in the scheme provided by the embodiment of the invention, the data processor can control whether the row data reset circuit transmits the reset control signal to the pixel circuit or not according to the refreshing requirement of the pixel circuit, and control whether the row data write-in circuit transmits the refreshing control signal to the pixel circuit or not, so as to control whether the pixel circuit is refreshed or not. Therefore, the scheme provided by the embodiment of the invention can independently control whether the pixel circuits in one row are refreshed or not.
The following takes the GOA circuit shown in fig. 4 as an example, and the specific structure and the relationship between the components of the GOA circuit are specifically described:
the pixel circuit 10:
in practical applications, each pixel circuit in the display device may be deployed with the GOA circuit provided in the embodiment of the present invention, and the specific deployment manner may be as follows: each pixel circuit has its own row data reset circuit 13 and row data write circuit 14. The signal supply circuit 11 and the data processor 12 are shared by all the pixel circuits.
For convenience of description, the following describes the relationship between the pixel circuit 10 and the signal providing circuit 11, the data processor 12, the row data reset circuit 13, the row data write circuit 14 and the pixel circuit 10 in the GOA circuit provided by the embodiment of the present invention by taking one pixel circuit 10 as an example, as shown in fig. 4, fig. 4 only shows the connection relationship between the pixel circuit of the nth row and the row data write circuit 14 and the row data reset circuit 13 in the display device, the specific circuit structure of the pixel circuit of the nth row is not shown in fig. 4, and the structure of the pixel circuit of the nth row refers to fig. 2.
The signal supply circuit 11:
the signal supply circuit 11 is configured to supply a reset control signal and a refresh control signal to refresh the pixel circuits 10 of each row according to the reset control signal and the refresh control signal.
Illustratively, as shown in fig. 4, the signal supply circuit 11 supplies the pixel circuits of the nth row with the reset control signal and the refresh control signal, so that the pixel circuits of the nth row are refreshed according to the reset control signal and the refresh control signal.
The data processor 12:
the data processor 12 is configured to issue control commands corresponding to refresh requirements of the pixel circuits 10 to the row data reset circuit 13 and the row data write circuit 14, respectively. The specific implementation process of the data processor 12 sending the control instruction corresponding to the refresh requirement of the pixel circuit 10 to the row data reset circuit 13 and the row data write circuit 14 respectively is as follows: a data processor 12, specifically configured to issue a data refresh control command for pixel circuit refresh to the row data reset circuit 13 and the row data write circuit 14, respectively, when it is determined that the current frame data of the pixel circuit 10 is different from the previous frame data; when it is determined that the current frame data of the pixel circuit 10 is the same as the previous frame data, a data non-refresh control command for not refreshing the pixel circuit is issued to the row data reset circuit 13 and the row data write circuit 14, respectively.
Specifically, the data processor 12 determines that the current frame data of the pixel circuit 10 is different from the previous frame data, and indicates that the display data of the pixel circuit 10 is changed, and the pixel circuit 10 needs to be refreshed in order to make the display of the pixel circuit 10 correspond to the display data, and therefore, issues a data refresh control command for pixel circuit refresh to the row data reset circuit 13 and the row data write circuit 14, respectively.
Specifically, the data processor 12 determines that the current frame data of the pixel circuit 10 is the same as the previous frame data, and indicates that the display data of the pixel circuit 10 has not changed, and in order to reduce power consumption due to pixel circuit refresh, the display of the pixel circuit 10 may be maintained in the current state, and at this time, the pixel circuit 10 does not need to be refreshed, and issues a data non-refresh control command that the pixel circuit does not refresh to the row data reset circuit 13 and the row data write circuit 14, respectively.
Further, the data processor 12 is further configured to determine whether a non-refresh signal is received when it is determined that the current frame data of the pixel circuit 10 is different from the previous frame data; when it is determined that the non-refresh signal is received, a data non-refresh control command for causing the pixel circuits to not refresh is issued to the row data reset circuit 13 and the row data write circuit 14, respectively.
Specifically, in order to avoid the pixel circuit from being refreshed in a manner that the user does not need to refresh the pixel circuit, the data processor needs to continuously determine whether to receive a non-refresh signal when determining that the current frame data of the pixel circuit 10 is different from the previous frame data, where the non-refresh signal is issued by the user based on the viewing requirement of the user. When it is determined that the non-refresh signal is received, it indicates that the user needs to maintain the display of the pixel circuit and does not need to refresh, and therefore, a data non-refresh control command for not refreshing the pixel circuit is issued to each of the row data reset circuit 13 and the row data write circuit 14. When it is determined that the non-refresh signal is not received, it indicates that the user does not need to maintain the display of the pixel circuit, and the pixel circuit needs to be refreshed, and therefore, a data refresh control command for refreshing the pixel circuit is issued to the row data reset circuit 13 and the row data write circuit 14, respectively.
The line data reset circuit 13:
the row data reset circuit 13 performs a first transmission process on the reset control signal according to the control instruction issued by the data processor 12, where the first transmission process is related to a specific control instruction issued by the data processor 12, and specifically includes the following two control conditions:
first, when the data processor 12 issues a data refresh control command, the row data reset circuit 13 is specifically configured to transmit a reset control signal to the data reset control terminal of the pixel circuit 10 under the data refresh control command issued by the data processor 12, so that the data reset control terminal performs a reset operation under the reset control signal.
The reset control signal is used to control the pixel circuit 10 to reset. The following describes the reset condition of the pixel circuit 10 after the reset control signal is transmitted to the data reset control terminal by taking fig. 2 and fig. 3 as an example. When the reset control signal reaches the data reset control terminal shown in fig. 2, the line segment a of the reset control signal shown in fig. 3 is at a low level in the region T1, the transistor M5 is turned on in a timing sequence corresponding to the region T1, and the voltage of the capacitor C in the pixel circuit 10 is reset to the initialization voltage by the voltage provided by the initialization voltage terminal Vinit when the transistor M5 is turned on. After the voltage of the capacitor C is reset to the initialization voltage, in order to avoid the influence of the voltage at the initialization voltage terminal Vinit on the refresh of the subsequent pixel circuit 10, the reset control signal enters the regions T2 and T3, the reset control signal is at a high level in the regions T2 and T3, and the transistor M5 is turned off in the timing sequence corresponding to the regions T2 and T3.
It should be noted that the reset of the pixel circuit 10 is a precondition for the update of the pixel circuit 10, and therefore, the transmission of the reset control signal from the row data reset circuit 13 to the data reset control terminal needs to be completed before the transmission of the refresh control signal from the row data write circuit 14 to the data refresh control terminal.
Illustratively, the pixel circuit in the previous row adjacent to the pixel circuit in the nth row is the pixel circuit in the (n-1) th row, and at the same time when the row data write circuit 14 corresponding to the pixel circuit in the (n-1) th row transmits the refresh control signal corresponding to the pixel circuit in the nth row to the data refresh control terminal thereof, the data processor 11 determines that the pixel circuit in the nth row needs to be refreshed, and controls the row data reset circuit 13 corresponding to the pixel circuit in the nth row to transmit the reset control signal corresponding to the pixel circuit in the nth row to the data reset control terminal of the pixel circuit in the nth row, so as to reset the pixel circuit in the nth row to prepare for refreshing.
Second, when the data processor 12 issues the data non-refresh control command, the row data reset circuit 13 is specifically configured to transmit the first maintaining signal to the data reset control terminal of the pixel circuit 10 under the data non-refresh control command issued by the data processor 12, so that the data reset control terminal maintains the current state under the first maintaining signal.
The first sustain signal is used for maintaining the current state of the data reset control terminal, so that the pixel circuit does not perform the reset operation. Illustratively, as shown in fig. 2, the current state of the data reset control terminal is that the control transistor M5 is turned off. The row data reset circuit 13 transmits the first sustain signal to the data reset control terminal of the pixel circuit under the data non-refresh control instruction issued by the data processor 12, and the data reset control terminal continues to control the transistor M5 to be turned off, so that the initialization voltage terminal Vinit cannot provide the initialization voltage to the capacitor C, and the pixel circuit is not updated.
The specific structure of the row data reset circuit 13 is: the line data reset circuit 13 includes a first switching element 131 and a second switching element 132. The specific connection relationship between the first switching element 131 and the second switching element 132 is: the first switching element 131 has a first terminal connected to the data processor 12, a second terminal connected to the signal supply circuit 13, and a third terminal connected to the first node K1. The first node K1 described herein is connected to the data reset control terminal of the pixel circuit. The second switching element 132 has a first terminal connected to the data processor 12, a second terminal connected to the first control terminal 133, and a third terminal connected to the first node K1. The first control terminal 133 is here described for generating a first maintenance signal. The first maintaining signal is used for maintaining the current state of the data reset control terminal. The specific type of the first control terminal 133 is not limited in this embodiment, and for example, the first control terminal 133 is an off-voltage terminal, the off-voltage signal provided by the first control terminal 133 is a first sustain signal, and under the first sustain signal, the transistor M5 in fig. 2 is turned off, so that the capacitor C cannot be reset to the initialization voltage.
The specific implementation of the first switching element 131 and the second switching element 132 is as follows:
a first switching element 131 for turning on under a data refresh control command; and closing the circuit under the control command of not refreshing the data. The second switch element 132 is configured to be turned off under the data refresh control command and turned on under the data non-refresh control command.
When the first switch element 131 is turned on and the second switch element 132 is turned off, the reset control signal provided by the signal providing circuit 11 is transmitted to the data reset control terminal of the pixel circuit 10 through the first switch element 131 and the first node K1, so that the data reset control terminal controls the corresponding transistor M5 to be turned on under the reset control signal, so that the transistor M5 of the pixel circuit 10 is turned on, and the voltage of the capacitor C in the pixel circuit 10 is reset to the initialization voltage by the voltage provided by the initialization voltage terminal Vinit.
When the first switch element 131 is turned off and the second switch element 132 is turned on, the reset control signal provided by the signal providing circuit 11 is not transmitted to the pixel circuit 10, but the first sustain signal provided by the first control terminal 133 is transmitted to the data reset control terminal of the pixel circuit 10 through the second switch element 132 and the first node K1, so that the data reset control terminal maintains the current state under the first sustain signal, thereby the pixel circuit 10 does not perform the refresh operation.
In practical applications, the specific types of the first switching element 131 and the second switching element 132 are not limited in this embodiment. Exemplary are as follows:
illustratively, as shown in fig. 4, the first switching element 131 is a first transistor N1. The second switching element 131 is a second transistor N2. The first transistor N1 has a gate connected to the data processor 12, a source connected to the signal supply circuit 11, and a drain connected to the first node K1. The gate of the second transistor N2 is connected to the data processor 12, the source is connected to the first control terminal 133, and the drain is connected to the first node K1. The first transistor N1 is turned on under a data refresh control command and turned off under a data non-refresh control command. The second transistor N2 is turned off under the data refresh control command and turned on under the data non-refresh control command.
Illustratively, the first switching element 131 includes a first switch and a first controller. The second switching element 131 includes a second switch and a second controller. The first controller is connected to the data processor 12 at a first terminal and to the first switch at a second terminal. The first switch has a first terminal connected to the second terminal of the first controller, a second terminal connected to the signal supply circuit 11, and a third terminal connected to the first node K1. The second controller is connected to the data processor 12 at a first terminal and to the second switch at a first terminal. A first terminal of the second switch is connected to a second terminal of the second controller, a second terminal is connected to the first control terminal 133, and a third terminal is connected to the first node K1. The first controller controls the first switch to be turned on under the data refreshing control command, and controls the first switch to be turned off under the data non-refreshing control command. The second controller controls the second switch to be closed under the data refreshing control command, and controls the second switch to be opened under the data non-refreshing control command.
The line data write circuit 14:
the line data writing circuit 14 is configured to perform a second transmission process on the refresh control signal according to the control instruction issued by the data processor 12, so that the pixel circuit 10 performs an operation corresponding to a processing result of the second transmission process. The second transmission process described herein is related to the specific control issued by the data processor 12, and the specific implementation of the row data writing circuit 14 includes the following two cases:
first, when the data processor 12 issues a data refresh control command, the row data write circuit 14 is specifically configured to transmit a refresh control signal to the data refresh control terminal of the pixel circuit 10 under the data refresh control command issued by the data processor 12, so that the data refresh control terminal performs a refresh operation under the refresh control signal.
The refresh control signal is used to control the pixel circuit 10 to refresh. The following takes fig. 2 and fig. 3 as an example to describe the refresh situation of the pixel circuit 10 after the refresh control signal is transmitted to the data refresh control terminal. When the refresh control signal reaches the data refresh control terminal shown in fig. 2, the line segment B of the refresh control signal shown in fig. 3 is at a high level in the region T1, and the transistor M1 and the transistor M4 are turned off in the timing sequence corresponding to the region T1, thereby avoiding an influence on the process of resetting the voltage of the capacitor C to the initialization voltage. Then, after the voltage reset initialization of the capacitor C is completed, the refresh control signal enters the region T2. The line segment B is at a low level in the region T2, the transistor M1 and the transistor M4 are turned on in a timing sequence corresponding to the region T2, the data voltage provided by the data signal terminal Vdata, and the transistor M3 transmits a current to the capacitor C under the action of the driving voltage and the voltage stored in the capacitor C, so that the capacitor C stores a voltage required for the light emission of the light emitting element P based on the data voltage provided by the data signal terminal Vdata on the basis of the initialization voltage. Then, after the capacitor C performs voltage storage based on the data voltage, the refresh control signal enters the region T3. The line segment B is at a low level in the T3 region, the transistors M1 and M4 are turned off in a timing sequence corresponding to the T3 region, the control signal terminal EM controls the transistors M2 and M6 to be turned on, the driving voltage terminal ELVDD1 provides a driving voltage, and the transistor M3 transmits a driving current to the light emitting element P under the action of the driving voltage and the voltage stored in the capacitor C, so that the light emitting element emits light under the driving current.
Second, when the data processor 12 issues the data non-refresh control command, the row data writing circuit 14 is specifically configured to transmit the second maintaining signal to the data refresh control terminal of the pixel circuit 10 under the data non-refresh control command issued by the data processor 12, so that the data refresh control terminal maintains the current state under the second maintaining signal.
The second sustain signal is used for maintaining the current state of the data refresh control terminal, so that the pixel circuit does not perform the refresh operation. Illustratively, as shown in fig. 2, the current control of the data refresh control terminal is to control the transistors M1 and M4 to be turned off. The row data writing circuit 14 transmits the second sustain signal to the data refresh control terminal of the pixel circuit 10 under the data non-refresh control command issued by the data processor 12, and the data refresh control terminal continues to control the transistors M1 and M4 to be turned off, so that the data signal terminal Vdata cannot provide the initialization data voltage to the capacitor C, and the pixel circuit is not refreshed.
The specific structure of the line data write circuit 14 is: the line data writing circuit 14 includes a third switching element 141 and a fourth switching element 142. The third switching element 141 has a first terminal connected to the data processor 12, a second terminal connected to the signal supply circuit 11, and a third terminal connected to the second node K2. Wherein the second node K2 is connected to the data refresh control terminal of the pixel circuit. The fourth switching element 142 has a first terminal connected to the data processor 12, a second terminal connected to the second control terminal 143, and a third terminal connected to the second node K2. The second control terminal 143 is here described as being used to generate the second maintenance signal. The second maintaining signal is used for maintaining the current state of the data refreshing control terminal. The specific type of the second control terminal 143 is not limited in this embodiment, and for example, the second control terminal 143 is an off-voltage terminal, the off-voltage signal provided by the second control terminal 143 is a second sustain signal, and under the second sustain signal, the transistors M1 and M4 in fig. 2 are turned off, so that the voltage of the capacitor C is not refreshed.
The specific implementation procedures of the third switching element 141 and the fourth switching element 142 are as follows:
a third switching element 141 for being turned on under a data refresh control command; and closing the circuit under the control command of not refreshing the data. And the fourth switching element 142 is configured to be turned off under the data refresh control command and turned on under the data non-refresh control command.
When the third switching element 141 is turned on and the fourth switching element 142 is turned off, the refresh control signal is transmitted to the data refresh control terminal of the pixel circuit 10 through the third switching element 141 and the second node K2, so that the data refresh control terminal controls the corresponding transistors M1 and M4 to be turned on under the refresh control signal, thereby allowing the capacitor C of the pixel circuit 10 to store a voltage required for the light emission of the light emitting element P based on the data voltage provided by the data signal terminal Vdata on the basis of the initialization voltage.
When the third switching element 141 is turned off and the fourth switching element 142 is turned on, the refresh control signal is not transmitted to the pixel circuit 10, but the second sustain signal provided by the second control terminal 143 is transmitted to the data refresh control terminal of the pixel circuit 10 through the fourth switching element 142 and the second node K2, so that the data refresh control terminal maintains the current state under the second sustain signal, thereby the pixel circuit 10 does not perform the refresh operation.
In practical applications, the specific types of the third switching element 141 and the fourth switching element 142 are not specifically limited in this embodiment. Exemplary are as follows:
illustratively, as shown in fig. 4, the third switching element 141 is a third transistor N3. The fourth switching element 142 is a fourth transistor N4. The third transistor N3 has a gate connected to the data processor 12, a source connected to the signal supply circuit 11, and a drain connected to the second node K2. The fourth switching element 142 is a fourth transistor N4, a gate of the fourth transistor N4 is connected to the data processor 12, a source thereof is connected to the second control terminal 143, and a drain thereof is connected to the second node K2. The third transistor N3 is turned on under the data refresh control command and turned off under the data non-refresh control command. The fourth transistor N4 is turned off under the data refresh control command and turned on under the data non-refresh control command.
Illustratively, the third switching element 141 includes a third switch and a third controller. The fourth switching element includes a fourth switch and a fourth controller. The first terminal of the third controller is connected to the data processor 12, the second terminal is connected to the third switch, the first terminal of the third switch is connected to the second terminal of the third controller, the second terminal is connected to the signal supply circuit 11, and the third terminal is connected to the second node K2. A first terminal of the fourth controller is connected to the data processor 12 and a second terminal is connected to a first terminal of the fourth switch. The first terminal of the fourth switch is connected to the second terminal of the fourth controller, the second terminal is connected to the second control terminal 143, and the third terminal is connected to the second node K2. The third controller controls the third switch to be opened under the data refreshing control command, and controls the third switch to be closed under the data non-refreshing control command. The fourth controller controls the fourth switch to be closed under the data refreshing control instruction, and controls the fourth switch to be opened under the data non-refreshing control instruction.
Further, the specific operation of the pixel circuit for both refresh and non-refresh scenarios will be described below with respect to fig. 2-5.
First, refreshing a scene
When the pixel circuits in the display device are scanned to the (n-1) th row of pixel circuits, the data processor 12 judges that the current frame data of the nth row of pixel circuits is different from the previous frame data, determines that the nth row of pixel circuits needs to be refreshed, and respectively sends out data refreshing control commands for refreshing the nth row of pixel circuits to the row data writing circuit 14 and the row data resetting circuit 13.
The row data reset circuit 13 transmits the reset control signal provided by the signal providing circuit to the data reset control terminal of the nth row pixel circuit under the data refresh control command issued by the data processor 12, so that the data reset control terminal performs the reset operation under the reset control signal. The reset operation here is specifically:
the pixel circuit enters a reset and initialization stage, and the specific process of the reset and initialization stage is as follows: when the reset control signal reaches the data reset control terminal shown in fig. 2, the line segment a of the reset control signal shown in fig. 3 is at a low level in the region T1, and the transistor M5 is turned on at a timing corresponding to the region T1. The line segment a of the refresh control signal shown in fig. 3 is at a high level in the region T1, and the transistors M1 and M4 are turned off. In fig. 3, a line segment C represents a target signal supplied from the control signal terminal EM, the line segment C is at a high level in the region T1, and the transistors M2 and M6 are turned off. Since both transistors M2 and M1 are off, no voltage is supplied to the source of transistor M3 and therefore M3 is also off. When the transistor M5 is turned on and the transistors M1, M2, M3, M4, and M6 are turned off, the voltage of the capacitor C in the pixel circuit of the nth row is reset to the initialization voltage by the voltage provided by the initialization voltage terminal Vinit.
The pixel circuit enters a programming stage, and the programming stage specifically comprises the following processes: after the voltage of the capacitor C is reset to the initialization voltage, the row data writing circuit 14 transmits the refresh control signal to the data refresh control terminal of the pixel circuit in the nth row under the data refresh control command issued by the data processor 12, so that the data refresh control terminal performs the refresh operation under the refresh control signal. The refresh operation here is specifically: in order to avoid the influence of the voltage at the initialization voltage terminal Vinit on the refresh operation of the pixel circuits in the subsequent nth row, the segment B of the reset control signal enters the region T2, the reset control signal is at a high level in the region T2, and the transistor M5 is turned off in the timing sequence corresponding to the region T2. The segment a indicating the refresh control signal enters the region T2, the refresh control signal is at a low level in the region T2, and the transistors M1 and M4 are turned on in a timing corresponding to the region T2. The line segment C in fig. 3, which represents the target signal supplied from the control signal terminal EM, is at a high level in the region T2, and the transistors M2 and M6 are turned off. Since the transistor M1 is turned on, the data signal terminal Vdata provides the data voltage to the source of the transistor M3, and thus M3 is also in an on state. When the transistors M1, M3, and M4 are turned on and the transistors M2, M5, and M6 are turned off, the transistor M3 transmits a current to the capacitor C by the data voltage and the voltage stored in the capacitor C, so that the capacitor C stores a voltage required for the light emission of the light emitting element P based on the data voltage provided from the data signal terminal Vdata on the basis of the initialization voltage.
The pixel circuit enters a light-emitting stage, and the specific process of the light-emitting stage is as follows: after the capacitor C stores the voltage based on the data voltage provided by the data signal terminal Vdata, in order to avoid the influence of the data voltage provided by the data signal terminal Vdata on the light emitting operation of the pixel circuit in the subsequent nth row, the line segment B indicating the reset control signal enters the region T3, the reset control signal is at a high level in the region T3, and the transistor M5 is turned off in the time sequence corresponding to the region T3. The line segment a representing the refresh control signal enters the region T3, the refresh control signal is high in the region T3, the transistors M1 and M4 are turned off during the timing corresponding to the region T3. In fig. 3, a line segment C representing a target signal supplied from the control signal terminal EM is at a low level in the region T3, and the transistors M2 and M6 are turned on. Since the transistor M2 is turned on, the driving voltage terminal ELVDD1 provides the driving voltage to the source of the transistor M3, and thus the transistor M3 is also in an on state. When the transistors M1, M3, and M6 are turned on and the transistors M2, M4, and M5 are turned off, the transistor M3 transmits a driving current to the light emitting element P for the transistor M3 under the driving voltage and the voltage stored in the capacitor C, so that the light emitting element emits light under the driving current.
Second, not refreshing the scene
When the pixel circuits in the display device are scanned to the (n-1) th row of pixel circuits, the data processor 12 judges that the current frame data of the nth row of pixel circuits is the same as the previous frame data, determines that the nth row of pixel circuits does not need to be refreshed, and respectively sends a data non-refreshing control command that the nth row of pixel circuits do not refresh to the row data writing circuit 14 and the row data resetting circuit 13.
The row data reset circuit 13 does not transmit the reset control signal to the data reset control terminal of the nth row of pixel circuits under the data non-refresh control instruction issued by the data processor 12, and transmits the first sustain signal provided by the first control terminal 133 to the data reset control terminal of the nth row of pixel circuits, so that the data reset control terminal maintains the current state under the first sustain signal. Here, the current state is maintained specifically as follows:
the pixel circuit enters a reset and initialization stage, and the reset and initialization stage specifically comprises the following processes: as shown in fig. 5, fig. 5 is a timing diagram of the pulse signal change. When the first sustain signal reaches the data reset control terminal shown in fig. 2, the line segment D of the first sustain signal shown in fig. 5 is at a high level in the region T1, and the transistor M5 is turned off at a timing corresponding to the region T1. The segment E of the signal of the data refresh control terminal shown in fig. 5 is at a high level in the region T1, and the transistors M1 and M4 are turned off, that is, the transistors M1 and M4 maintain the current state. The line segment F in fig. 5, which represents the target signal supplied from the control signal terminal EM, is at a high level in the region T1, and the transistors M2 and M6 are turned off. Since the transistors M1 to M6 are all turned off, the voltage of the capacitor C in the pixel circuit of the nth row is not reset and remains at the voltage corresponding to the previous frame data.
The pixel circuit enters a programming stage, and the programming stage specifically comprises the following processes: the row data writing circuit 14 transmits the second holding signal provided by the second control terminal 142 to the data refresh control terminal under the data non-refresh control command issued by the data processor 12, so that the data refresh control terminal maintains the current state under the second holding signal. Here, the current state is maintained specifically as follows: as shown in fig. 5, the line segment D indicating the first sustain signal enters the region T2, the first sustain signal is at a high level in the region T2, and the transistor M5 is turned off in a timing corresponding to the region T2. The line segment E of the signal of the data refresh control terminal shown enters the region T2, and is at a high level in the region T2, and the transistors M1 and M4 maintain the off state in the timing corresponding to the region T2, and it should be noted that the signal of the data refresh control terminal at this time is the second maintenance signal. The line segment F in fig. 5, which represents the target signal supplied from the control signal terminal EM, is at a high level in the region T2, and the transistors M2 and M6 are turned off. Since the transistors M1 to M6 are all turned off, the voltage of the capacitor C in the pixel circuit of the nth row is not refreshed and remains at the voltage corresponding to the previous frame data.
The pixel circuit enters a light-emitting stage, and the light-emitting stage specifically comprises the following processes: as shown in fig. 5, the line segment D indicating the first sustain signal enters the region T3, the first sustain signal is at a high level in the region T3, and the transistor M5 is turned off in a timing corresponding to the region T3. The line segment E of the signal of the data refresh control terminal shown enters the region T3, and is at a high level in the region T3, and the transistors M1 and M4 maintain the off state in the timing corresponding to the region T3, and it should be noted that the signal of the data refresh control terminal at this time is the second maintenance signal. In fig. 5, a line segment F indicating the target signal supplied from the control signal terminal EM is at a low level in the region T3, and the transistors M2 and M6 are turned on. Since the transistor M2 is turned on, the driving voltage terminal ELVDD1 provides the driving voltage to the source of the transistor M3, and thus the transistor M3 is also in an on state. When the transistors M1, M3, and M6 are turned on and the transistors M2, M4, and M5 are turned off, the transistor M3 transmits a driving current to the light emitting element P for the transistor M3 under the driving voltage and the voltage stored in the capacitor C, so that the light emitting element emits light under the driving current.
Further, another embodiment of the present invention also provides a display apparatus including: the GOA circuit is described above.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
It will be appreciated that the relevant features of the method and apparatus described above are referred to one another. In addition, "first", "second", and the like in the above embodiments are for distinguishing the embodiments, and do not represent merits of the embodiments.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The algorithms and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus. Various general purpose systems may also be used with the teachings herein. The required structure for constructing such a system will be apparent from the description above. Moreover, the present invention is not directed to any particular programming language. It is appreciated that a variety of programming languages may be used to implement the teachings of the present invention as described herein, and any descriptions of specific languages are provided above to disclose the best mode of the invention.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.
The various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components of the method, apparatus and framework for operation of a deep neural network model in accordance with embodiments of the present invention. The present invention may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present invention may be stored on computer-readable media or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
Claims (10)
1. A GOA circuit, comprising: the device comprises a signal providing circuit, a data processor, a row data resetting circuit and a row data writing circuit; the row data reset circuit is respectively connected with the pixel circuit, the signal supply circuit and the data processor; the line data writing circuit is respectively connected with the pixel circuit, the signal providing circuit and the data processor;
the signal providing circuit is used for providing a reset control signal for the row data resetting circuit and a refreshing control signal for the row data writing circuit;
the data processor is used for respectively issuing control instructions corresponding to the refreshing requirements of the pixel circuit to the row data reset circuit and the row data write-in circuit, and the refreshing requirements are used for reflecting whether the pixel circuit needs to be refreshed or not;
the row data reset circuit is used for carrying out first transmission processing on the reset control signal according to a control instruction issued by the data processor so as to enable the pixel circuit to execute operation corresponding to a processing result of the first transmission processing; an operation corresponding to a processing result of the first transfer processing is for satisfying a refresh requirement of the pixel circuit;
the row data writing circuit is used for carrying out second transmission processing on the refreshing control signal according to a control instruction issued by the data processor so as to enable the pixel circuit to execute operation corresponding to a processing result of the second transmission processing; an operation corresponding to the processing result of the second transfer processing is for satisfying a refresh requirement of the pixel circuit.
2. The GOA circuit of claim 1, wherein the data processor is configured to issue a data refresh control command for refreshing the pixel circuits to the row data writing circuit and the row data resetting circuit, respectively, upon determining that current frame data of the pixel circuits is different from previous frame data; and when the current frame data of the pixel circuit is judged to be the same as the previous frame data, respectively sending a data non-refreshing control command that the pixel circuit does not refresh to the row data writing circuit and the row data resetting circuit.
3. The GOA circuit of claim 2, wherein the data processor is further configured to determine whether a no-refresh signal is received upon determining that current frame data of the pixel circuit is different from previous frame data; and when the non-refreshing signal is judged to be received, respectively issuing a data non-refreshing control instruction that the pixel circuit does not refresh to the row data writing circuit and the row data resetting circuit.
4. The GOA circuit of claim 2, wherein the row data reset circuit is specifically configured to transmit the reset control signal to the pixel circuit under a data refresh control command issued by the data processor, so that the pixel circuit performs a reset operation under the reset control signal;
the row data writing circuit is specifically configured to transmit the refresh control signal to the pixel circuit under a data refresh control instruction issued by the data processor, so that the pixel circuit executes a refresh operation under the refresh control signal, where the reset control signal is transmitted before the refresh control signal.
5. The GOA circuit of claim 2, wherein the row data reset circuit is specifically configured to transmit a first sustain signal to the pixel circuit under a data non-refresh control instruction issued by the data processor, so that the pixel circuit maintains a current state under the first sustain signal;
the row data writing circuit is specifically configured to transmit a second maintenance signal to the pixel circuit under a data non-refresh control instruction issued by the data processor, so that the pixel circuit maintains a current state under the second maintenance signal.
6. The GOA circuit of any one of claims 2-5, wherein the row data reset circuit comprises: a first switching element and a second switching element;
a first switch element, a first end of which is connected with the data processor, a second end of which is connected with the signal providing circuit, and a third end of which is connected with a first node, and is used for being turned on under the data refreshing control instruction; closing the data under the control command of not refreshing the data; the first node is connected with a data reset control end of the pixel circuit;
a first switch element, a first end of which is connected with the data processor, a second end of which is connected with a first control end, and a third end of which is connected with the first node, and is used for being closed under the data refreshing control instruction and being opened under the data non-refreshing control instruction; the first control end is used for generating a first maintaining signal.
7. The GOA circuit of claim 6, wherein the first switching element is a first transistor; the grid electrode of the first transistor is connected with the data processor, the source electrode of the first transistor is connected with the signal providing circuit, and the drain electrode of the first transistor is connected with the first node;
and/or the presence of a gas in the atmosphere,
the second switching element is a second transistor; and the grid electrode of the second transistor is connected with the data processor, the source electrode of the second transistor is connected with the first control end, and the drain electrode of the second transistor is connected with the first node.
8. A GOA circuit according to any one of claims 2 to 5, wherein the row data writing circuit comprises:
a third switching element, a first end of which is connected with the data processor, a second end of which is connected with the signal providing circuit, and a third end of which is connected with a second node, and is used for being turned on under the data refreshing control instruction; closing the data under the control command of not refreshing the data; the second node is connected with a data refreshing control end of the pixel circuit;
a fourth switching element, a first end of which is connected with the data processor, a second end of which is connected with the second control end, and a third end of which is connected with the second node, and is used for being closed under the data refreshing control instruction and being opened under the data non-refreshing control instruction; wherein the second control terminal is used for generating a second maintenance signal.
9. The GOA circuit of claim 8, wherein the third switching element is a third transistor; the grid electrode of the third transistor is connected with the data processor, the source electrode of the third transistor is connected with the signal providing circuit, and the drain electrode of the third transistor is connected with the second node;
and/or the presence of a gas in the gas,
the fourth switching element is a fourth transistor, a gate of the fourth transistor is connected to the data processor, a source of the fourth transistor is connected to the second control terminal, and a drain of the fourth transistor is connected to the second node.
10. A display device, characterized in that the display device comprises: the GOA circuit of any one of claims 1-9.
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| CN110111738A (en) * | 2019-05-31 | 2019-08-09 | 京东方科技集团股份有限公司 | Pixel circuit, display base plate, display device and driving method |
| CN112004089A (en) * | 2020-09-04 | 2020-11-27 | 白华 | Method for supporting local refreshing of any display area |
| CN114283762A (en) * | 2021-12-22 | 2022-04-05 | 南京阿吉必信息科技有限公司 | Dynamic refreshing display driving method, server and storage medium |
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