CN114695318A - WAT electrical property test layout - Google Patents
WAT electrical property test layout Download PDFInfo
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- CN114695318A CN114695318A CN202210187331.5A CN202210187331A CN114695318A CN 114695318 A CN114695318 A CN 114695318A CN 202210187331 A CN202210187331 A CN 202210187331A CN 114695318 A CN114695318 A CN 114695318A
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- patterns
- grid electrode
- active region
- wat
- electrode patterns
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- 238000012360 testing method Methods 0.000 title claims abstract description 24
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000003466 welding Methods 0.000 claims abstract description 6
- 238000013461 design Methods 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 9
- 230000008569 process Effects 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003203 everyday effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a WAT electrical property test layout, which comprises an active region graph; a plurality of contact hole patterns which are respectively positioned at two ends of the active region pattern and are distributed at equal intervals; welding pad patterns respectively positioned at two ends of the active region pattern and connected with the contact hole pattern; multiple groups of gate patterns arranged at equal intervals between the contact hole patterns at the two ends of the active region pattern; each group of grid electrode patterns comprises at least one group of first grid electrode patterns and at least one group of second grid electrode patterns which are distributed in a staggered mode, one ends of the first grid electrode patterns and one ends of the second grid electrode patterns respectively exceed the active area patterns, and the other ends of the first grid electrode patterns and the second grid electrode patterns are respectively located in the range of the active area patterns. The test layout of the invention measures the resistance between the welding pads, if a smaller normal metal silicide resistance is obtained, the whole snake-shaped active area is proved not to have silicide process interruption, namely, the film combination is not generated, and if the resistance is larger and even has an open circuit phenomenon, the film combination is possibly generated between the grids, and the process needs to be improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a WAT electrical property test layout.
Background
With the development of the times, the chip becomes a ' necessity ' of global life, with the progress of chip technology, people's life is more and more intelligent, each trip is more and more convenient, and the amount of information available every day is also more and more large.
As the requirements for integrated circuit design and fabrication become higher and higher, the feature size of MOS transistors becomes smaller and smaller, and many processes are even at the limit of continuous squeezing process.
One of the important links of the feature size reduction is that the line width of a polysilicon gate (metal gate) is reduced, and then the distance between the gates is also reduced, so as to achieve the goal of reducing the whole device.
Since the pitch between the gates becomes smaller, a merge phenomenon may occur during thin film deposition after gate formation, which may block subsequent ion implantation and silicide formation.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a WAT electrical test layout, which is used to solve the problem in the prior art that due to the decreased inter-gate spacing, merging (merge) may occur during the deposition of a thin film after the gate formation, which may block the subsequent ion implantation and silicide formation.
To achieve the above and other related objects, the present invention provides a WAT electrical test layout, comprising:
an active area pattern;
a plurality of contact hole patterns which are respectively positioned at two ends of the active region pattern and are distributed at equal intervals;
the welding pad patterns are respectively positioned at two ends of the active region patterns and connected with the contact hole patterns;
a plurality of groups of grid electrode patterns which are arranged at equal intervals and are positioned between the contact hole patterns at two ends of the active region pattern, a plurality of groups of grid electrode patterns which are sequentially distributed at equal intervals and are positioned between the welding pad patterns and in the active region; wherein,
each group of grid electrode patterns comprises at least one group of first and second grid electrode patterns which are distributed in a staggered mode, one ends of the first and second grid electrode patterns respectively exceed the active region patterns, and the other ends of the first and second grid electrode patterns are respectively located in the range of the active region patterns.
Preferably, the distance between the first gate pattern and the second gate pattern satisfies a minimum design rule in layout design.
Preferably, from one end of the active region pattern to the other end, the critical dimensions of the widths of the first and second gate patterns in each group of the gate patterns sequentially increase.
Preferably, the critical dimensions of the first and second gate patterns in each group of gate patterns are equal.
Preferably, the number of the groups of the gate patterns is three.
Preferably, each group of the gate patterns includes two groups of the first and second gate patterns.
Preferably, the graph in the layout design is a rectangle.
Preferably, the layout is used for detecting the integrity of silicide formation.
As described above, the WAT electrical test layout of the present invention has the following beneficial effects:
the invention provides a test layout, during testing, the resistance between welding pads is measured, if a smaller normal metal silicide resistance is obtained, the whole snake-shaped active area is proved to have no silicide process interruption, namely no film merging, and if the resistance is larger and even has an open circuit phenomenon, the film merging possibly occurs between grids, and the process needs to be improved.
Drawings
FIG. 1 is a schematic diagram of a WAT electrical test layout according to the present invention;
fig. 2 is a schematic diagram of the serpentine active region of the present invention.
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Referring to fig. 1, the present invention provides a WAT electrical test layout, including:
an active area pattern;
a plurality of contact hole patterns 20 respectively positioned at both ends of the active region pattern 10 and equidistantly distributed;
a pad pattern 30 respectively located at both ends of the active region pattern 10 and connected to the contact hole pattern 20;
that is, the contact hole pattern 20 and the pad pattern 30, which are connected, measure the resistance between the two pads in the semiconductor device manufactured according to the layout for both ends of the test pattern of the WAT electrical test layout, and can obtain the resistance of the device between the two pads.
In an alternative embodiment, the two pad patterns 30 are respectively disposed on two sides of the active region pattern 10, and according to this arrangement, the pads on the two ends are far from the gate, so that the combination is not easy to occur.
A plurality of gate patterns 40 disposed between the pad patterns 30 and the contact hole patterns 20 connected thereto and on the active region patterns 10, and sequentially and equidistantly distributed; wherein,
each group of gate patterns 40 comprises at least one group of first gate patterns (401) and second gate patterns (402) which are distributed in a staggered mode, one ends of the first gate patterns (401) and the second gate patterns (402) respectively exceed the active region patterns 10, the other ends of the first gate patterns (401) and the second gate patterns (402) are respectively located in the range of the active region patterns 10, and the distance between the first gate patterns (401) and the second gate patterns (402) is equal to the distance between the gate patterns 40.
In an alternative embodiment, the distance between the first and second gate patterns (401,402) satisfies a minimum design rule in layout design, i.e., a semiconductor device obtained later according to the layout satisfies a minimum design rule size of a manufacturing process.
In an alternative embodiment, the critical dimension of the width of the first and second gate patterns (401,402) in each set of gate patterns 40 increases from one end of the active area pattern 10 to the other end.
In an alternative embodiment, the critical dimensions of the first and second gate patterns (401,402) in each group of gate patterns 40 are equal, that is, the first and second gate patterns (401,402) are both equal in size and shape.
In an alternative embodiment, the number of sets of gate patterns 40 is three.
In an alternative embodiment, each set of gate patterns 40 includes two sets of first and second gate patterns (401, 402).
In an alternative embodiment, the shapes of the figures in the layout design are rectangles.
In an alternative embodiment, referring to fig. 2, a serpentine active area pattern 10 structure is formed from left to right, and a semiconductor device manufactured according to the pattern structure is tested by measuring the resistance between pads, and if a small normal metal silicide resistance is obtained, it is proved that no silicide process interruption occurs in the whole serpentine active area, that is, no film merging occurs, and if the resistance is large, even an open circuit occurs, it is illustrated that film merging may occur between gates, so as to facilitate detection of the resistance between pads.
In an alternative embodiment, the layout is used for silicide formation integrity detection.
It should be noted that the drawings provided in this embodiment are only for schematically illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings and not drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may be more complicated.
In summary, the present invention provides a test layout, during testing, the resistance between the pads is measured, and if a smaller normal metal silicide resistance is obtained, it is proved that the silicide process interruption does not occur in the whole snake-shaped active region, that is, the film merging does not occur, and if the resistance is larger and even there is an open circuit, it indicates that the film merging may occur between the gates, and the process needs to be improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A WAT electrical test layout, comprising:
an active area pattern;
a plurality of contact hole patterns which are respectively positioned at two ends of the active region pattern and are distributed at equal intervals;
the welding pad patterns are respectively positioned at two ends of the active region patterns and connected with the contact hole patterns;
a plurality of groups of gate patterns which are arranged at equal intervals are positioned between the contact hole patterns at the two ends of the active region pattern; wherein,
each group of grid electrode patterns comprises at least one group of first and second grid electrode patterns which are distributed in a staggered mode, one ends of the first and second grid electrode patterns respectively exceed the active region patterns, and the other ends of the first and second grid electrode patterns are respectively located in the range of the active region patterns.
2. The WAT electrical test layout of claim 1, wherein: the distance between the first grid electrode graph and the second grid electrode graph meets the minimum design rule in layout design.
3. The WAT electrical test layout of claim 1, wherein: from one end of the active region pattern to the other end, the critical dimension of the width of the first grid electrode pattern and the critical dimension of the width of the second grid electrode pattern in each group of grid electrode patterns are sequentially increased.
4. The WAT electrical test layout of claim 1, wherein: and the critical dimensions of the first grid electrode graph and the second grid electrode graph in each group of grid electrode graphs are equal.
5. The WAT electrical test layout of claim 1, wherein: the number of the groups of the grid patterns is three.
6. The WAT electrical test layout of claim 1, wherein: each group of grid electrode patterns comprises two groups of first grid electrode patterns and second grid electrode patterns.
7. The WAT electrical test layout according to any one of claims 1 to 6, wherein: the shape of the graph in the layout design is rectangular.
8. The WAT electrical test layout of claim 1, wherein: the layout is used for detecting the integrity of silicide formation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210187331.5A CN114695318A (en) | 2022-02-28 | 2022-02-28 | WAT electrical property test layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210187331.5A CN114695318A (en) | 2022-02-28 | 2022-02-28 | WAT electrical property test layout |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114695318A true CN114695318A (en) | 2022-07-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210187331.5A Pending CN114695318A (en) | 2022-02-28 | 2022-02-28 | WAT electrical property test layout |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114695318A (en) |
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2022
- 2022-02-28 CN CN202210187331.5A patent/CN114695318A/en active Pending
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