CN114490467A - Message processing DMA (direct memory access) system and method of multi-core network processor - Google Patents
Message processing DMA (direct memory access) system and method of multi-core network processor Download PDFInfo
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- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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Abstract
The invention provides a message processing DMA (direct memory access) system and a message processing DMA method of a multi-core network processor, belonging to the technical field of network communication. The message is sent to the hardware forwarding module through the Ethernet interface module, the message is analyzed by the hardware forwarding module, the user-defined mode can be supported for shunting, a processor core ID for processing the message is generated at the same time, after the processor core corresponding to the CPU processor system receives a request, the received message is stored in a DDR3/4 memory through a DMA mode, after the whole message is received, signal processing is carried out, a new data message is generated after the processing is finished, and then the new data message is sent to the hardware forwarding module and the Ethernet interface module through the DMA mode to be sent out. After the DMA controller sends the data to the hardware forwarding module, the feedback message informs the CPU processor system, and then the CPU processor system releases the DDR space. The method can realize rapid data exchange and high-efficiency data access.
Description
Technical Field
The invention relates to the technical field of network communication, in particular to a message processing DMA (direct memory access) system and a message processing DMA method for multi-core network processing, which can realize high-efficiency off-chip storage and data reading of messages of a multi-core network processor chip.
Background
The multi-core network processor chip is a network processor based on a general processor core architecture, is widely applied to a plurality of network communication devices including a carrier-class Ethernet switch/router, an optical transmission platform, a data center and a broadband infrastructure, can also be applied to devices such as a baseband processing unit (BBU) and a small base station (SmallCell) of a 5G core network, and is a key component of a new generation of network communication system. The multi-core network processor combines the high-speed processing capability of hardware and the programmability of software, and can meet the requirements of users on bandwidth, delay and the like.
"a network processor instruction storage device and an instruction storage method (cn201210233710. x)" of zhongxing communication introduces methods such as instruction storage of a network processor based on a micro-engine structure, and "a controller (CN201210484096.4) applied to a DDR3 memory in a network processor" of china electrical department 32 introduces an optimization method of a DDR3 controller in a multi-core network processor, but does not study how to efficiently switch an ethernet message to a DDR3 by bypassing a general multi-core CPU.
Disclosure of Invention
The invention aims to provide a message processing DMA (direct memory access) system and a message processing DMA method of a multi-core network processor, which can realize message off-chip efficient storage and data reading of a multi-core network processor chip.
In order to achieve the purpose, the invention adopts the technical scheme that:
a message processing DMA system of a multi-core network processor comprises an Ethernet interface module, a hardware forwarding module, a DMA controller, a CPU processor system and a DDR3/4 memory;
the Ethernet interface module is used for receiving the Ethernet message and sending the Ethernet message to the hardware forwarding module; and receiving the message from the hardware forwarding module and sending the message;
the hardware forwarding module is used for analyzing the Ethernet message and sending the analyzed message to the DMA controller; the DMA controller receives the message, analyzes the message and sends the message to the Ethernet interface module;
the DMA controller is used for generating a processor core ID for message processing, sending a DMA request to the CPU processor system, receiving a DDR address sent by the CPU processor system and length information for determining a transfer data block, and writing a corresponding data message into a DDR3/4 memory; the system is also used for receiving data messages sent by the CPU processor system, assembling the data messages into a message format, sending the message format to the hardware forwarding module, and sending a DMA feedback completion mark to the CPU processor system;
the CPU processor system comprises a plurality of processor cores, wherein one processor core is used for distributing a DDR space in a DDR3/4 memory to be used as a management idle pointer and adopting a linked list for management; the other processor cores are used for responding to the DMA request in a polling mode, after the DMA request sent to the corresponding processor core is polled, the corresponding processor core reads the DDR space to obtain an idle pointer, sends a DDR address to the DMA controller through the annular bus and determines length information of a data block to be transmitted, is also used for generating a new data message to be stored in the DDR space, reads a data message and corresponding address information from the corresponding DDR space, and sends the data message and the corresponding address information to the DMA controller through the annular bus;
the DDR3/4 memory is used for storing data messages in a set format.
Further, the data storage format of the DDR3/4 memory is { next ptr, eop, pkt _ len, pkt _ data }, where next ptr represents a next pointer, eop represents a message end, pkt _ len represents a message length, and pkt _ data represents message data.
A message processing method of a multi-core network processor comprises the following steps:
(1) the process of the DMA controller moving the data block to the memory is as follows:
(1a) after a multi-core network processor chip is powered on, one processor core of a CPU processor system allocates a DDR space as a management idle pointer and adopts a linked list for management;
(1b) the Ethernet interface module receives the message and sends the message to the hardware forwarding module, the hardware forwarding module analyzes the message and then sends the message to the DMA controller, and the DMA controller generates a processor core ID for processing the message and sends a DMA request to the CPU processor system;
(1c) the processor cores of the CPU processor system respond to the DMA request in a polling mode, after polling the DMA request sent to the corresponding processor cores, the corresponding processor cores read the DDR space to obtain an idle pointer, and send the DDR address and length information for determining a data block to be transmitted to the DMA controller;
(1d) after receiving the related information of the DDR address, the DMA controller stores the corresponding data in a DDR space in a form of a linked list and executes the burst length of one-time operation, wherein the burst length is configured according to the requirement;
(1e) the DMA controller sends operation ending information to a processor core corresponding to the CPU processor system;
(2) the process of the DMA controller sending out the memory read data block is as follows:
(2a) after the data processing of the CPU processor system is finished, generating a new data message, storing the new data message into a DDR space, reading the data message and corresponding address information from the DDR space, and sending the data message and the corresponding address information to a DMA controller;
(2b) the DMA controller receives the data message sent by the CPU processor system, assembles the data message into a message format and sends the message format out through the hardware forwarding module, after the sending is finished, a finishing mark is fed back to the CPU processor system, and the CPU processor system obtains mark information through a polling mode.
Further, the data storage format of the DDR space is { next ptr, eop, pkt _ len, pkt _ data }, where next ptr represents a next pointer, eop represents a message end symbol, pkt _ len represents a message length, and pkt _ data represents message data.
Further, in the step (1c), when the processor core issues the DDR address to the DMA controller, the data length is determined, if the data length is smaller than a set value, the DDR address is directly issued to the DMA controller and length information of a data block to be transferred is determined, if the data length is larger than the set value, a skip idle pointer is applied to the DDR space, and a next skip idle pointer is issued to the DMA controller in a mode of operating a register.
Further, the data messages in the DDR space are stored in a linked list mode by taking 2KB/4KB as a unit, each 2KB/4KB data message needs to have a next ptr and eop, and the next ptr and eop are stored at the initial position of the 2KB/4KB data message; the DMA controller performs insertion byte processing on the data message when storing corresponding data to a DDR space in a linked list mode, and the specific processing process is as follows: inserting a 32-bit space into the data message at an interval of 2KB/4KB, wherein 27 bits are next ptr, 1bit is eop, and 4 bits are free spaces; wherein, the next ptr represents the next pointer, and eop represents the end of message.
Compared with the prior art, the invention has the following advantages:
(1) the invention supports configurable message storage granularity, and 2KB or 4KB can be used;
(2) the invention supports the CPU to apply a DDR message memory space pointer to the DMA controller;
(3) the size of the pointer DDR storage space and the size of the message DDR storage space can be configured.
Drawings
FIG. 1 is a schematic diagram of the overall structure of a system according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating bit width insertion structure according to an embodiment of the present invention;
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Referring to fig. 1, a message processing DMA system of a multi-core network processor includes an ethernet interface module, a hardware forwarding module, a DMA controller, a CPU processor system, and a DDR3/4 memory;
the Ethernet interface module is used for receiving the Ethernet message and sending the Ethernet message to the hardware forwarding module; and receiving the message from the hardware forwarding module and sending the message;
the hardware forwarding module is used for analyzing the Ethernet message and sending the analyzed message to the DMA controller; the DMA controller receives the message, analyzes the message and sends the message to the Ethernet interface module;
the DMA controller is used for generating a processor core ID for message processing, sending a DMA request to the CPU processor system, receiving a DDR address sent by the CPU processor system and length information for determining a transfer data block, and writing a corresponding data message into a DDR3/4 memory; the system is also used for receiving data messages sent by the CPU processor system, assembling the data messages into a message format, sending the message format to the hardware forwarding module, and sending a DMA feedback completion mark to the CPU processor system;
the CPU processor system comprises a plurality of processor cores (16A 53 cores are arranged in the embodiment), wherein the processor Core A53Core 0 is used for allocating a DDR space in a DDR3/4 memory as a management idle pointer and adopting a linked list for management; the other processor cores are used for responding to the DMA request in a polling mode, after the DMA request sent to the corresponding processor core is polled, the corresponding processor core reads the DDR space to obtain an idle pointer, sends a DDR address to the DMA controller through the annular bus and determines length information of a data block to be transmitted, is also used for generating a new data message to be stored in the DDR space, reads a data message and corresponding address information from the corresponding DDR space, and sends the data message and the corresponding address information to the DMA controller through the annular bus;
the DDR3/4 memory is used for storing data messages in a set format. The data storage format of the DDR3/4 memory is { next ptr, eop, pkt _ len, pkt _ data }, where the next ptr represents a next pointer, eop represents a message end character, pkt _ len represents a message length, and pkt _ data represents message data.
A message processing method of a multi-core network processor comprises the following steps:
(1) the process of the DMA controller moving the data block to the memory is as follows:
(1a) after the multi-Core network processor chip is powered on, a processor Core A53Core 0 of the CPU processor system allocates a DDR space as a management idle pointer and adopts a linked list for management;
(1b) the Ethernet interface module receives the message and sends the message to the hardware forwarding module, the hardware forwarding module analyzes the message and then sends the message to the DMA controller, and the DMA controller generates a processor core ID for processing the message and sends a DMA request to the CPU processor system;
(1c) the processor cores of the CPU processor system respond to the DMA request in a polling mode, after polling the DMA request sent to the corresponding processor cores, the corresponding processor cores read the DDR space to obtain a free pointer, and send the DDR address and determine the length information of the data block to be transmitted to the DMA controller through the annular bus; when the processor core issues the DDR address to the DMA controller, judging the data length, if the data length is smaller than a set value, directly issuing the DDR address to the DMA controller and determining length information of a transmission data block, if the data length is larger than the set value, applying for a jump idle pointer to a DDR space, and issuing a jump idle pointer to the DMA controller in a mode of operating a register;
(1d) after receiving the related information of the DDR address, the DMA controller stores corresponding data into a DDR space in a form of a linked list through a ring bus, and executes the burst length of one-time operation, wherein the burst length can be configured;
referring to FIG. 2, the DMA controller is required to perform insert byte processing on off-chip stored messages, and since the messages are stored in a DDR in a linked list form by taking 2KB/4KB as a unit, each 2KB/4KB message needs to have a next ptr and eop. Next ptr and eop are stored at the beginning of a 2KB/4KB message. Therefore, 32 bits (the next ptr needs 27 bits, eop needs 1bit, and 4bit free space) are inserted into the input message at intervals of 2KB/4KB, and the next ptr and eop are reserved and inserted. And judging the position of the 32-bit space to be inserted by counting, counting the byte number of the off-chip message, and inserting the 32-bit space when counting 4K-4 or 2K-4 bytes. For the first inserted 32bit of a message, the 32bit needs to be inserted after pkt _ len, so that the module can correctly identify the queue number and whether the message is an off-chip storage message when uniformly processing the on-chip and off-chip messages. After 32 bits are inserted, the data bit width of 64 bits is changed into 96 bits, and the data is also converted into 1024 bits and aligned. In the figure, sop represents a message start symbol, eop represents a message end symbol, queue _ NO represents which queue the current input message belongs to, and internal _ flag represents whether the message is an off-chip storage message.
(1e) The DMA controller sends operation ending information to a processor core corresponding to the CPU processor system;
(2) the process of the DMA controller sending out the memory read data block is as follows:
(2a) after the data processing of the CPU processor system is finished, generating a new data message, storing the new data message into a DDR space, reading the data message and corresponding address information from the DDR space, and sending the data message and the corresponding address information to the DMA controller through a ring bus;
(2b) the DMA controller receives the data message sent by the CPU processor system, assembles the data message into a message format and sends the message format out through the hardware forwarding module, after the sending is finished, a finishing mark is fed back to the CPU processor system, and the CPU processor system obtains mark information through a polling mode.
Claims (6)
1. A message processing DMA system of a multi-core network processor is characterized by comprising an Ethernet interface module, a hardware forwarding module, a DMA controller, a CPU processor system and a DDR3/4 memory;
the Ethernet interface module is used for receiving the Ethernet message and sending the Ethernet message to the hardware forwarding module; and receiving the message from the hardware forwarding module and sending the message;
the hardware forwarding module is used for analyzing the Ethernet message and sending the analyzed message to the DMA controller; the DMA controller receives the message, analyzes the message and sends the message to the Ethernet interface module;
the DMA controller is used for generating a processor core ID for message processing, sending a DMA request to the CPU processor system, receiving a DDR address sent by the CPU processor system and length information for determining a transfer data block, and writing a corresponding data message into a DDR3/4 memory; the system is also used for receiving data messages sent by the CPU processor system, assembling the data messages into a message format, sending the message format to the hardware forwarding module, and sending a DMA feedback completion mark to the CPU processor system;
the CPU processor system comprises a plurality of processor cores, wherein one processor core is used for distributing a DDR space in a DDR3/4 memory to be used as a management idle pointer and adopting a linked list for management; the other processor cores are used for responding to the DMA request in a polling mode, after the DMA request sent to the corresponding processor core is polled, the corresponding processor core reads the DDR space to obtain an idle pointer, sends a DDR address to the DMA controller through the annular bus and determines length information of a data block to be transmitted, is also used for generating a new data message to be stored in the DDR space, reads a data message and corresponding address information from the corresponding DDR space, and sends the data message and the corresponding address information to the DMA controller through the annular bus;
the DDR3/4 memory is used for storing data messages in a set format.
2. The message processing DMA system of claim 1, wherein the DDR3/4 memory has a data storage format of { next ptr, eop, pkt _ len, pkt _ data }, where next ptr represents a next pointer, eop represents a message end, pkt _ len represents a message length, and pkt _ data represents message data.
3. A message processing method of a multi-core network processor is characterized by comprising the following steps:
(1) the process of the DMA controller moving the data block to the memory is as follows:
(1a) after a multi-core network processor chip is powered on, one processor core of a CPU processor system allocates a DDR space as a management idle pointer and adopts a linked list for management;
(1b) the Ethernet interface module receives the message and sends the message to the hardware forwarding module, the hardware forwarding module analyzes the message and then sends the message to the DMA controller, and the DMA controller generates a processor core ID for processing the message and sends a DMA request to the CPU processor system;
(1c) the processor cores of the CPU processor system respond to the DMA request in a polling mode, after polling the DMA request sent to the corresponding processor cores, the corresponding processor cores read the DDR space to obtain an idle pointer, and send the DDR address and length information for determining a data block to be transmitted to the DMA controller;
(1d) after receiving the related information of the DDR address, the DMA controller stores the corresponding data in a DDR space in a form of a linked list and executes the burst length of one-time operation, wherein the burst length is configured according to the requirement;
(1e) the DMA controller sends operation ending information to a processor core corresponding to the CPU processor system;
(2) the process of the DMA controller sending out the memory read data block is as follows:
(2a) after the data processing of the CPU processor system is finished, generating a new data message, storing the new data message into a DDR space, reading the data message and corresponding address information from the DDR space, and sending the data message and the corresponding address information to a DMA controller;
(2b) the DMA controller receives the data message sent by the CPU processor system, assembles the data message into a message format and sends the message format out through the hardware forwarding module, after the sending is finished, a finished mark is fed back to the CPU processor system, and the CPU processor system obtains mark information through a polling mode.
4. The message processing method of claim 3, wherein the data storage format of the DDR space is { next ptr, eop, pkt _ len, pkt _ data }, the next ptr represents a next pointer, eop represents a message end, pkt _ len represents a message length, and pkt _ data represents message data.
5. The message processing method of claim 3, wherein in step (1c), when the processor core issues the DDR address to the DMA controller, the data length is determined, if the data length is smaller than a set value, the DDR address is directly issued to the DMA controller and length information of a data block to be transferred is determined, if the data length is larger than the set value, a skip idle pointer is applied to the DDR space, and a next skip idle pointer is issued to the DMA controller by operating a register.
6. The message processing method of the multi-core network processor as claimed in claim 3, wherein the data message in the DDR space is stored in a linked list form with 2KB/4KB as a unit, each 2KB/4KB data message needs to have a next ptr and eop, and the next ptr and eop are stored at the initial position of the 2KB/4KB data message; the DMA controller performs insertion byte processing on the data message when storing corresponding data to a DDR space in a linked list mode, and the specific processing process is as follows: inserting a 32-bit space into the data message at an interval of 2KB/4KB, wherein 27 bits are next ptr, 1bit is eop, and 4 bits are free spaces; wherein, the next ptr represents the next pointer, and eop represents the end of message.
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