CN103955586A - Low-overhead fault tolerance circuit applied to low power consumption digital signal processing system - Google Patents
Low-overhead fault tolerance circuit applied to low power consumption digital signal processing system Download PDFInfo
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Abstract
The invention belongs to the technical field of low power consumption integrated circuit design, in particular to a low-overhead fault tolerance circuit applied to a low power consumption digital signal processing system.The circuit employs a two-stage fault tolerance structure, wherein the first stage employs an on-line time sequence monitoring mechanism to detect a soft fault and then selects output via a simple correction mechanism, and the second stage employs a mean filtering concept and comprises a predictor based on smooth filtering and an arbiter to realize fault detection and correction.Compared with the traditional single-stage fault tolerance circuit based on predication, the fault detection and correction capability of the two-stage fault tolerance circuit can be greatly improved.A fault tolerance technology is combined with a voltage over-scaling technology, performance of the system can be kept in a tolerant scope, and further voltage reduction is allowed, so that the power consumption of the system is greatly reduced.The circuit is simple in structure, low in overhead and high in correction capability, and is especially suitable for being applied to the low power consumption digital signal processing system based on the VOS (voltage over-scaling) technology.
Description
Technical field
The invention belongs to low power consumption integrated circuit technical field, be specifically related to a kind of low expense fault tolerable circuit that is applied to low power consumption digital signal processing system.
Background technology
Along with integrated circuit technique fast development, characteristic dimension is constantly dwindled, and chip integration is deferred to mole (Moore) law and improved constantly.In the process improving rapidly in integrated circuit technique development and integrated level, the subject matter that people pay close attention to is always how to improve the operating rate of chip, dwindles chip area and cost, and for the consideration of circuit power consumption often in relatively less important position.But fast development and the market demand due to mobile device, portable electronic, communication and other consumption electronic product markets makes this situation that some basic changes occur in recent years.In a lot of applications, reduce the of paramount importance problem that power consumption has become Design of Digital System.
The market demand of low-power consumption has been impelled the generation of a lot of Low-power Technology, and the conventional Low-power Technology of industry has gated clock, gate voltage and the design of multivoltage territory etc. at present.Recent study personnel have proposed voltage and have crossed zoom technology (VOS:Voltage Over Scaling), its principle is to reduce artificially voltage to reduce power consumption, because causing critical path, lower voltage occurs that sequential breaks rules, now again by adding fault tolerable circuit technology to carry out error correction simultaneously; Finally, Circuits System can bring with the sacrifice of certain signal to noise ratio (S/N ratio) the reduction greatly of power consumption.
Existing VOS fault tolerable circuit technology comprises: difference channel error correction, the error correction circuit based on prediction, the error correcting technique based on low precision stand-by circuit and self-adaptation mistake cancellation technology etc.These technology often only have one-level, and error correcting capability is limited.The present invention combines shadow register technology and the error correcting technique based on prediction, has proposed a kind of novel two-stage fault-tolerant architecture, can greatly improve error correcting capability, thereby voltage and power consumption are further reduced.
Summary of the invention
The object of the present invention is to provide a kind of low expense fault tolerable circuit that is applied to low power consumption digital signal processing system, to improve the error-detection error-correction ability of digital information processing system, thereby allow supply voltage further to reduce, finally realize low-power consumption.
The low expense fault tolerable circuit that is applied to low power consumption digital signal processing system that the present invention proposes, its one-piece construction block diagram as shown in Figure 1.This fault tolerable circuit consists of two-stage fault tolerable circuit (being two-stage EDC error detection and correction circuit); First order fault tolerable circuit, the soft error (soft-error) or the time delay mistake (delay-error) that for detection of sequential does not meet, cause, if made mistakes, utilize previous output valve to correct the currency of makeing mistakes; Second level fault tolerable circuit, utilizes the correlativity of exporting, and according to the value of having exported, produces the predicted value to current output, and detects wrong and correct a mistake by this predicted value.
First order fault tolerable circuit of the present invention, as shown in Figure 2, consists of the data selector of sequential error monitoring module and alternative; Wherein, sequential error monitoring module utilizes the time delay of shadow register technology for detection critical path and inferior critical path whether to surpass the clock period of system, if exceeded, think and occur sequential mistake, and this error propagation is gone down, at last output terminal, by selector switch, select previous right value to export as the estimation of current improper value.Wherein, shadow register technology breaks rules for detection of sequential, and Fig. 3 has provided the detection schematic diagram of a bit-errors, when former register and shadow register result, thinks when different and occurs sequential mistake.
In the present invention, described sequential error monitoring module, consists of shadow register and rub-out signal propagation circuit; Shadow register by a time delay clock of certain hour drive, need a certain combinational logic path ends of monitoring to be connected to the data input pin of shadow register; The output of shadow register and the output of former register contrast by an XOR gate, if different, think that sequential makes mistakes, this error signal is propagated by a propagation chain, propagate chain by or door and former clock-driven register form, propagation progression is consistent with the pipeline series of former data path; The error signal of afterbody is selected current output by alternative data selector, if made mistakes, selects an output as the prediction to currency.
The second level of the present invention fault tolerable circuit, as shown in Figure 1, consists of the data selector of fallout predictor, moderator and alternative; The input of fallout predictor is front p value of currency; Fallout predictor output is as the prediction to currency, and moderator, according to the predicted value of currency and currency, is exported an arbitrating signals, and this arbitrating signals, as the control signal of the data selector of alternative, is selected final output.
In the present invention, the schematic diagram of moderator as shown in Figure 4, by subtracter, ask absolute value logic and comparer to form, by subtracter, predicted value and the currency of fallout predictor output are done to subtraction, the absolute value of the difference that comparer obtains subtracter and the threshold of setting in advance; If the absolute value of difference surpasses threshold value, think that currency is wrong, signal is selected in now moderator output, controls alternative data selector and selects the predicted value of fallout predictor as final output; If the absolute value of difference is less than threshold value, think that currency does not have mistake, signal is selected in moderator output, controls alternative data selector and selects currency as final output; The threshold value of comparer will be determined according to application scenarios.
The course of work of this system is as follows: first first order fault tolerable circuit detects the sequential mistake of critical path online, and if there is mistake, the output terminal by this error propagation to streamline, selects previous right value as output by alternative data selector; Then second level fault tolerable circuit, the principle based on smothing filtering, utilizes p output valve above to predict current output valve, if predicted value and currency deviation are excessive, thinks that currency makes mistakes, and selects predicted value as output.
Traditional fault tolerable circuit technology that is applied to VOS generally adopts single-stage error correction, error correcting capability is limited, if for example only adopt the first order fault tolerable circuit in Fig. 1, although can correct some mistakes, but when shadow register also occurs that sequential breaks rules, judge by accident, error correction effect there will be decline significantly; The fault-tolerant circuit structure of two-stage that the present invention proposes can well address this problem, and the detection principle of two-stage circuit is not identical, mix to use and can guarantee in first order error correcting capability decline situation, the fault-tolerant effect of integrated circuit is not affected substantially, thereby circuit voltage is further reduced, realize more low-power consumption.
Accompanying drawing explanation
Fig. 1 is two-stage fault tolerable circuit structural diagrams of the present invention.
Fig. 2 is sequential error monitoring module diagram in first order fault tolerable circuit.
Fig. 3 is shadow register technology diagram.
Fig. 4 is moderator structural diagrams in the fault tolerable circuit of the second level.
Fig. 5 is that sequential monitoring module is given an example.
Fig. 6 is that shadow register working waveform figure is.
Embodiment
First analyze the critical path distribution situation of original digital signal disposal system, according to the distribution of critical path, design the monitoring chain of sequential mistake and propagate chain.Fig. 2 has provided sequential error monitoring chain generally, during practical application, will design as the case may be this module.Fig. 5 has provided the design example of a sequential monitoring module, supposes that the critical path of the data path of primary circuit system is
, its time delay is
, the path that is only second to critical path is successively
,
,
, its time delay is respectively
,
,
; Design fault-tolerant ability is
, and
,
, i.e. fault-tolerant design only allows
,
,
make mistakes in path, sequential error monitoring module now can design according to shown in Fig. 5, notices that second level combinational logic does not need the path of monitoring, therefore do not need shadow register, only needs a register propagate errors signal.
When reducing supply voltage, the maximum delay of critical path can surpass the clock period, Fig. 6 has provided shadow register work wave schematic diagram in this case, can see in first clock period, combinational logic had completed calculating before former clock clk1 rising edge, therefore former register and shadow register are adopted identical value, illustrate and do not have sequential mistake to occur; And at second period, combinational logic is after former clock clk1 rising edge, before time delay Δ t clock clk2 rising edge, complete calculating, therefore former register is adopted improper value, and shadow register is adopted right value, the difference of the two causes circuit the 3rd clock period, Error signal to be set high, and illustrates and now occurs sequential mistake.
Because error propagation progression is consistent with pipeline series, therefore rub-out signal can follow misdata to propagate together, and together arrive final output terminal, now rub-out signal selects previous right value as output valve now by selector switch, thereby realizes the error checking and correction (ECC) of the first order.
The work thought of second level fault tolerable circuit is by a low-pass filter, utilizes the correlativity of output data, detects the data of sharply saltus step, and is filtered out.As shown in Figure 1, the main data selector by fallout predictor, moderator and alternative forms; The input of predictor module is front p value of currency, fallout predictor output is as the prediction to currency, and moderator, according to the predicted value of currency and currency, is exported an arbitrating signals, this arbitrating signals, as the control signal of the data selector of alternative, is selected final output.Wherein the schematic diagram of moderator as shown in Figure 4, by subtracter, ask absolute value logic and comparer to form, predicted value and the currency of fallout predictor output are done subtraction, by the absolute value of difference and the threshold of setting in advance, if the absolute value of difference surpasses threshold value, think that currency is wrong, signal is selected in now moderator output, controls alternative data selector and selects the predicted value of fallout predictor as final output; If the absolute value of difference is less than threshold value, think that currency does not have mistake, signal is selected in moderator output, controls alternative data selector and selects currency as final output.
Being designed with at 2 and should be noted that of second level fault tolerable circuit: first is, selection as the low-pass filter exponent number p of fallout predictor, be not that exponent number is the bigger the better, because exponent number causes more greatly the probability that occurs improper value in p the value for prediction to increase, prediction accuracy is declined, therefore need to draw optimized exponent number by emulation.Second point is the selection of comparator threshold, determined after fallout predictor exponent number, need definite threshold, different application scenarios threshold value settings is different, its method is in error-free situation, and this fault tolerable circuit structure is carried out to emulation, and it is poor that currency and predicted value are done, take absolute value and export, the maximal value of absolute value is threshold value so.
Claims (3)
1. a low expense fault tolerable circuit that is applied to low power consumption digital signal processing system, is characterized in that: by two-stage fault tolerable circuit, be that two-stage EDC error detection and correction circuit forms; First order fault tolerable circuit, the soft error or the time delay mistake that for detection of sequential does not meet, cause, and utilize previous output valve to correct the currency of makeing mistakes; Second level fault tolerable circuit, utilizes the correlativity of exporting, and according to the value of having exported, produces the predicted value to current output, and detects wrong and correct a mistake by this predicted value; Wherein:
Described first order fault tolerable circuit, consists of the data selector of sequential error monitoring module and alternative; Sequential error monitoring module utilizes the time delay of shadow register technology for detection critical path and inferior critical path whether to surpass the clock period of system, if exceeded, think and occur sequential mistake, and this error propagation is gone down, at last output terminal, by selector switch, select previous right value to export as the estimation of current improper value;
Described second level fault tolerable circuit, consists of the data selector of fallout predictor, moderator and alternative; The input of fallout predictor is front p value of currency; Fallout predictor output is as the prediction to currency, and moderator, according to the predicted value of currency and currency, is exported an arbitrating signals, and this arbitrating signals, as the control signal of the data selector of alternative, is selected final output.
2. the low expense fault tolerable circuit that is applied to low power consumption digital signal processing system according to claim 1, is characterized in that: described sequential error monitoring module, consists of shadow register and rub-out signal propagation circuit; Shadow register by a time delay clock of certain hour drive, need a certain combinational logic path ends of monitoring to be connected to the data input pin of shadow register; The output of shadow register and the output of former register contrast by an XOR gate, if different, think that sequential makes mistakes, this error signal is propagated by a propagation chain, propagate chain by or door and former clock-driven register form, propagation progression is consistent with the pipeline series of former data path; The error signal of afterbody is selected current output by alternative data selector, if made mistakes, selects an output as the prediction to currency.
3. the low expense fault tolerable circuit that is applied to low power consumption digital signal processing system according to claim 2, it is characterized in that: the moderator in the fault tolerable circuit of the described second level by subtracter, ask absolute value logic and comparer to form, by subtracter, predicted value and the currency of fallout predictor output are done to subtraction, the absolute value of the difference that comparer obtains subtracter and the threshold of setting in advance; If the absolute value of difference surpasses threshold value, think that currency is wrong, signal is selected in now moderator output, controls alternative data selector and selects the predicted value of fallout predictor as final output; If the absolute value of difference is less than threshold value, think that currency does not have mistake, signal is selected in moderator output, controls alternative data selector and selects currency as final output.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109032564A (en) * | 2018-08-16 | 2018-12-18 | 电子科技大学 | A kind of cordic algorithm realization circuit of high stability |
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| US6606356B1 (en) * | 1997-06-13 | 2003-08-12 | Center For Advanced Science And Technology Incubation, Ltd. | Asynchronous digital system, asynchronous data path circuit, asynchronous digital signal processing circuit and asynchronous digital signal processing method |
| JP2001043259A (en) * | 1999-07-30 | 2001-02-16 | Toyooki Kogyo Co Ltd | Method for preparing power consumption while using computer system and computer readable recording medium storing program for realizing the method |
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| CN109032564B (en) * | 2018-08-16 | 2022-12-02 | 电子科技大学 | High-stability CORDIC algorithm implementation circuit |
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