CN103811338B - A kind of semiconductor device and preparation method thereof - Google Patents
A kind of semiconductor device and preparation method thereof Download PDFInfo
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- CN103811338B CN103811338B CN201210445686.6A CN201210445686A CN103811338B CN 103811338 B CN103811338 B CN 103811338B CN 201210445686 A CN201210445686 A CN 201210445686A CN 103811338 B CN103811338 B CN 103811338B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 109
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 91
- 238000000034 method Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 13
- 230000003647 oxidation Effects 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 238000000059 patterning Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 150000004767 nitrides Chemical group 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 14
- 239000011248 coating agent Substances 0.000 description 12
- 238000000576 coating method Methods 0.000 description 12
- 238000001020 plasma etching Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 239000012212 insulator Substances 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 230000001590 oxidative effect Effects 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to a kind of semiconductor device and preparation method thereof, described method includes: provide Semiconductor substrate, support substrate that substrate includes stacking gradually, oxide insulating layer, semiconductor material layer；Substrate is formed hard mask layer；Patterned hard mask layer；The sidewall of described hard mask layer is formed clearance wall；Etching semiconductor material layer, forms first grid region；The sidewall of oxidation semiconductor material layer, to form the gate oxide layers in first grid region；Deposit the second semiconductor material layer, to form first gate electrode；Aoxidize the top of the second semiconductor material layer；Pattern remaining hard mask layer, to form fin pattern；Etching semiconductor material layer, to form the first fin, the second fin and second grid region；Second fin is formed gate oxide, the first fin is formed the gate oxide layers in second grid region；Deposit the 3rd semiconductor material layer, form second grid electrode.The method of the invention is more prone to control.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of semiconductor device and preparation method thereof.
Background technology
Improving mainly by constantly reducing the size of IC-components to improve its speed of performance of integrated circuits
Realize.At present, due in pursuing high device density, high-performance and low cost semi-conductor industry have advanced to nanometer skill
Art process node, has resulted in three dimensional design such as FinFET from the challenge manufactured with design aspect
(FinFET) development.Use extend from the substrate that formed by such as etching away a part of silicon layer thin vertically " fin " (or
Fin structure) manufacture typical FinFET.The raceway groove of FinFET is formed in described vertical fin, upper at described fin
Square one-tenth all around gate, and control raceway groove by grid from both sides.It addition, in recess source/drain electrode (S/D) part of FinFET
In, utilize selective growth strain gauge material to can be used for improving carrier mobility.
The quiescent dissipation caused due to short-channel effect (short channel effects) in semiconductor device at present
Sharply increase, become the subject matter of super large-scale integration (Very Large Scale Integration, VLSI).?
After processing technique, the adjustment of threshold voltage (threshold voltage, Vth) becomes and overcomes the requisite technology of the problems referred to above
Means.
Prior art control in the device of (Vth-controllable) at numerous threshold voltages, 4-terminal-fin field
Effect transistor (4-terminal-FinFET), is also called DG-FinFET, described DG-FinFET and has 4 terminals, such as Fig. 1
Shown in source and drain S/D, and grid G 1 and grid G 2, described DG-FinFET device can be converted to from state of activation flexibly
Holding state, it is therefore desirable to integrated 3T and 4T FinFETs thus realize better performance.
Wherein, prior art has two kinds of DG-FinFET, respectively there is asymmetric gate oxide and asymmetric grid
Two kinds of oxide (The asymmetric gate oxide), Fig. 1 show the DG-with asymmetric gate oxide
FinFET, wherein said gate oxide Tox1Thickness and described Tox2Thickness identical, and the asymmetric grid oxygen shown in Fig. 2
In the DG-FinFET of compound (The asymmetric gate oxide), described gate oxide Tox1Thickness and described Tox2
Thickness and differ, wherein said driving gate oxide level (drive gate Tox) Tox1Thickness less, threshold voltage
Control gate oxide skin(coating) (Vth-control gate Tox) Tox2Thickness relatively big, better control over threshold voltage with this
(threshold voltage, Vth), eliminates short-channel effect further.Fig. 3-4 is for currently form asymmetric gate oxide
Method, by light shield etch on the right of grid on FinFET, form the integrated structure of 3T and 4TFinFETs.
Although the threshold voltage of device can be controlled at present by DG-FinFET device, eliminate or reduce short channel effect
Should, but it is difficult to when forming asymmetric gate oxide control this technical process, poor accuracy, cause yield of devices and performance
Reduction, it is therefore desirable to improve to eliminate the problems referred to above to said method.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will enter in detailed description of the invention part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme required for protection
Key feature and essential features, more do not mean that the protection domain attempting to determine technical scheme required for protection.
The invention provides the preparation method of a kind of semiconductor device, including:
There is provided Semiconductor substrate, support substrate that described substrate includes stacking gradually, oxide insulating layer, semi-conducting material
Layer；
Form hard mask layer over the substrate；
Pattern described hard mask layer, with semiconductor material layer described in exposed portion；
The sidewall of described hard mask layer is formed clearance wall；
Semiconductor material layer described in described hard mask layer and described clearance wall as mask etch, to expose described quasiconductor
The sidewall of material layer and described oxide insulating layer, form first grid region；
The sidewall of the described semiconductor material layer that oxidation is exposed, to form the gate oxide layers in first grid region；
Depositing the second semiconductor material layer on the described oxide insulating layer exposed, then planarization etch-back, make
Described second semiconductor material layer is concordant with described hard mask layer, to form first gate electrode；
Aoxidize the top of described second semiconductor material layer, to form oxide, as dielectric layer；
Pattern remaining described hard mask layer, to form fin pattern；
Semiconductor material layer described in described hard mask layer as mask etch, to form the be positioned at below described clearance wall
One fin, it is positioned at the second fin below described fin pattern and second grid region；
Aoxidize the sidewall of described semiconductor material layer, to form gate oxide on described second fin, described first
The gate oxide layers in second grid region is formed on fin；
Substrate deposits the 3rd semiconductor material layer, to cover described second grid region and the described dielectric layer of part,
Form second grid electrode.
As preferably, the thickness of the gate oxide that described first fin is formed is different.
As preferably, on described first fin, the thickness of the gate oxide layers in described first grid region is more than described the
The gate oxide layers of two area of grid.
As preferably, the thickness of the gate oxide that described second fin is formed is identical.
As preferably, described hard mask layer is nitride layer.
As preferably, described hard mask layer is SiN layer.
As preferably, described clearance wall is oxide.
As preferably, with described hard mask layer and described clearance wall as mask, reactive ion is selected to etch described quasiconductor
Material layer, to form first grid region.
As preferably, described second semiconductor material layer is polysilicon layer.
As preferably, the method patterning remaining described hard mask layer is:
Described hard mask layer is formed patterning photoresist layer, forms fin pattern, with described photoresist layer as mask
Etch described hard mask layer；As preferably, with described hard mask layer as mask, reactive ion is selected to etch described semi-conducting material
Layer, then peels off described photoresist layer, to form described first fin and the second fin.
As preferably, described 3rd semiconductor material layer is polysilicon layer.
As preferably, the forming method of described second grid electrode is:
Substrate deposit the 3rd semiconductor material layer and planarizes, patterning described 3rd semiconductor material layer, with dew
Go out described dielectric layer, form second grid electrode, further, substrate deposits the 3rd semiconductor material layer and planarizes, so
The rear photoresist layer forming patterning, the 3rd semiconductor material layer described in described photoresist layer as mask etch, peel off described
Photoresist layer, to form second grid electrode.
As preferably, described semiconductor device is the integrated morphology of 4 terminals FinFET and standard FinFET.
Present invention also offers a kind of semiconductor device using said method to manufacture.Prepare the invention provides one
4 terminals FinFET and the method for the transistor of the integrated morphology of standard FinFET, during preparation 4 terminals FinFET, pass through
First latter two steps forms gate oxide level, forms the asymmetric gate oxide level that thickness is different, described relatively thin grid
Pole oxide is as driving gate oxide level (drive gate Tox), and thicker gate oxide is as threshold voltage control
Gate oxide level (Vth-control gate Tox), better controls over threshold voltage (threshold with this
Voltage, Vth), eliminate short-channel effect further, improve device performance.The method of the invention is prepared asymmetric simultaneously
It is more prone to during gate oxide level control, improves the yield of device further.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Shown in the drawings of this
Bright embodiment and description thereof, be used for explaining assembly of the invention and principle.In the accompanying drawings,
Fig. 1-2 is the plan structure schematic diagram in prior art with symmetrical and asymmetric gate oxide FinFETs；
Fig. 3-4 is the cut-away view preparing asymmetric gate oxide FinFETs in prior art；
Fig. 5-15 prepares the cut-away view of asymmetric gate oxide FinFETs for the present invention；
Figure 16 is to prepare semiconductor device technology schematic flow sheet in the present invention.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without these details one or more
Implement.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not entered
Line description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate of the present invention half
Conductor device and preparation method thereof.Obviously, the execution of the present invention is not limited to the spy that the technical staff of semiconductor applications is familiar with
Different details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these describe in detail, the present invention can also have
Other embodiments.
Should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
Exemplary embodiment according to the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also
It is intended to include plural form.Additionally, it should be understood that, when using term " to comprise " in this manual and/or " including "
Time, it indicates and there is described feature, entirety, step, operation, element and/or assembly, but does not precludes the presence or addition of one or many
Other features individual, entirety, step, operation, element, assembly and/or combinations thereof.
Now, the exemplary embodiment according to the present invention it is more fully described with reference to the accompanying drawings.But, these exemplary realities
Execute example to implement with multiple different form, and should not be construed to be limited solely to the embodiments set forth herein.Should
It is understood by, it is provided that these embodiments are so that disclosure of the invention is thorough and complete, and by these exemplary enforcement
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness in layer and region is exaggerated
Degree, and make to be presented with like reference characters identical element, thus description of them will be omitted.
Below in conjunction with Fig. 5-15, the preparation method of semiconductor device of the present invention is described further, institute of the present invention
Stating semiconductor device is the FinFET (FinFETs) with differing heights fin based on mixed substrates:
With reference to Fig. 5, it is provided that Semiconductor substrate, described Semiconductor substrate can be at least in the following material being previously mentioned
Kind: on silicon-on-insulator (SOI), insulator on stacking silicon (SSOI), insulator on stacking SiGe (S-SiGeOI), insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc., can also form other active devices in the semiconductor substrate.
Preferred silicon-on-insulator (SOI) in the present invention, described silicon-on-insulator (SOI) includes being followed successively by support substrate from the bottom up
201, oxide insulating layer 202 and semiconductor material layer 203, the semiconductor material layer at wherein said top be monocrystalline silicon layer,
Polysilicon layer, SiC or SiGe.The most described SOI substrate passes through direct wafer bonding (direct wafer
Bonding) formed.
Owing to SOI is made into below device active region having oxide insulating layer 202, this oxide insulating layer 202 is embedding
In semiconductor base layer, so that device has more excellent performance, but it is not limited to above-mentioned example.
As the most preferably, the most described support substrate and described semiconductor material layer are Si layer.
With continued reference to Fig. 5, form hard mask layer over the substrate；
Specifically, at described silicon-on-insulator (SOI) upper deposition hard mask layer 204, described hard mask layer is nitride layer,
Being preferably SiN, the deposition process of described hard mask layer can select chemical vapor deposition (CVD) method, physical vapor deposition (PVD)
Low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and the choosing that method or ald (ALD) method etc. are formed
Select the one in epitaxial growth (SEG).
With reference to Fig. 6, pattern described hard mask layer, to remove the described hard mask layer of part, quasiconductor described in exposed portion
Material layer；
Specifically, form the mask layer of patterning, such as photoresist layer over the substrate, etch described hard mask layer,
Can select hard mask layer described in dry etching or wet etching, preferably reactive ion etching in the present invention, etching is described
Hard mask layer is to described semiconductor material layer, to remove the described hard mask layer of part.
Then on the sidewall of described hard mask layer, form clearance wall, to protect described semiconductor material layer, form first
Area of grid；Specifically, spacer material layer, the most preferably oxide, such as SiO are formed over the substrate2
Deng material, then overall etch (Blanket etch), only retain the spacer material layer on described hard mask layer sidewall, formed
Hard mask layer clearance wall 205.
The deposition process of wherein said spacer material layer can select ability common method, such as chemical gaseous phase deposition
(CVD) low-pressure chemical vapor deposition that method, physical vapor deposition (PVD) method or ald (ALD) method etc. are formed
(LPCVD), laser ablation deposition (LAD) and selective epitaxy grow the one in (SEG).Wherein said engraving method can also
Select method commonly used in the art, do not repeat them here.
With reference to Fig. 7, semiconductor material layer described in described hard mask layer and described clearance wall as mask etch, to expose
State the sidewall of semiconductor material layer and described oxide insulating layer, form first grid region；
Specifically, with described hard mask layer and described clearance wall as mask, select reaction ionic etching method etching described
Semi-conducting material material layer is to described oxide insulating layer, to form first grid region.
Dry etching can be selected in the specific embodiment of the invention, reactive ion etching (RIE), ion beam milling, etc.
Plasma.Carrying out dry etching preferably by one or more RIE step, the most described reactive ion etches
(RIE) etch-rate faster and good each can be obtained by controlling reacting gas, air pressure, flow and radio-frequency power
Anisotropy, it is possible to the condition realizing described purpose may be incorporated for the present invention.
The conduct etching atmosphere in N2 can be selected the most in the present invention, it is also possible to be simultaneously introduced other a small amount of gas example
Such as CF4、CO2、O2, described etching pressure can be 50-200mTorr, preferably 100-150mTorr, and power is 200-600W,
The most described etching period is 5-80s, more preferably 10-60s, selects bigger gas flow in the present invention simultaneously,
As preferably, the flow at N2 of the present invention is 30-300sccm, more preferably 50-100sccm.
With reference to Fig. 8, the sidewall of the described semiconductor material layer that oxidation is exposed, to form the gate oxide in first grid region
Layer；
Specifically, the sidewall of semiconductor material layer described in high-temperature oxydation, form oxide, and then form described first grid
The oxide skin(coating) in region, control oxidizing condition is to form thicker oxide skin(coating) in this step, asymmetric to ultimately form
Gate oxide level.Increase the temperature of described oxidation in this step, extend the time of described oxidation, to form sufficiently thick oxygen
Compound layer, as preferably, described oxidizing temperature is more than 1200 DEG C, and described oxidization time is 10-600s, more preferably 180-
240s, forms the gate oxide level that thickness is bigger, in this step as threshold voltage control gate oxide skin(coating) (Vth-
Control gateTox), in order to preferably adjust the threshold voltage vt h of described device, reduce short-channel effect further.
With reference to Fig. 9, the described oxide insulating layer exposed deposits the second semiconductor material layer, then planarize and return
Etching, makes described second semiconductor material layer concordant with described hard mask layer, to form first gate electrode；
Specifically, on described oxide insulating layer, deposition growing the second semiconductor material layer 207, as preferably, described
Second semiconductor material layer selects the material identical with described semiconductor material layer, and such as silicon, polysilicon, SiC or SiGe, more excellent
Electing polysilicon as, described polysilicon layer can use low-pressure chemical vapor phase deposition (LPCVD).Deposit described semiconductor material layer
After, also include a planarisation step and the step of etch-back (etch back), to ensure described second semiconductor material layer and institute
State hard mask layer and there is same height, to obtain even curface, preferred chemical-mechanical planarization in the present invention.
With reference to Figure 10, aoxidize described second semiconductor material layer, to form oxide, as dielectric layer 208；
Specifically, aoxidizing described second semiconductor material layer, to form oxide, described oxide is in subsequent steps
As dielectric layer, the most described oxidizing temperature is more than 1200 DEG C, and described oxidization time is 10-400s, but not office
It is limited to described condition.
With reference to Figure 11-12, pattern remaining described hard mask layer, to form fin pattern；
Specifically, described hard mask layer is formed patterning photoresist layer, forms fin pattern, with described photoresist layer
For hard mask layer described in mask etch, described pattern is transferred to described hard mask layer, selects dry etching in the present invention,
In one embodiment, described dry etching can select CF4、CHF3, additionally plus N2、CO2、O2In one as etching atmosphere,
Wherein gas flow is CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, described etching pressure is
30-150mTorr, etching period is 5-120s, preferably 5-60s, more preferably 5-30s.
With reference to Figure 13, semiconductor material layer described in described hard mask layer as mask etch, it is positioned at described gap to be formed
The first fin below wall, it is positioned at the second fin below described fin pattern and second grid region；
Specifically, semiconductor material layer described in described hard mask layer as mask etch, it is positioned at described clearance wall to be formed
Following the first fin 10, it is positioned at the second fin 20 below described fin pattern, and is positioned at described first fin 10 and institute
State the second grid region between the second fin 20.
Dry etching can be selected in the specific embodiment of the invention, reactive ion etching (RIE), ion beam milling, etc.
Plasma.Carrying out dry etching preferably by one or more RIE step, the most described reactive ion etches
(RIE) etch-rate faster and good each can be obtained by controlling reacting gas, air pressure, flow and radio-frequency power
Anisotropy, it is possible to the condition realizing described purpose may be incorporated for the present invention.
Oxide skin(coating) thicker in described first grid region it has been initially formed in the present invention in step above,
It is subsequently formed in described second grid region and forms oxide skin(coating) relatively thin on the first fin.
With reference to Figure 14, aoxidize the sidewall of described semiconductor material layer, to form gate oxide on described second fin
210, described first fin is formed the gate oxide layers 209 in second grid region；
Specifically, aoxidize the sidewall of described semiconductor material layer, including described first fin 10 right side wall and
The two side of the second fin, controls oxidizing condition in this step and controls to form thin oxide skin(coating) 209 on described first fin
Thickness less than forming the oxide skin(coating) 206 of thickness on described first fin, described thin oxide skin(coating) 209 is used for forming driving grid
Pole oxide skin(coating) (drive gate Tox), forms asymmetric gate oxide level on described first fin, in order to more preferably
Ground adjusts the threshold voltage vt h of described device, reduces short-channel effect further；And the oxidation formed on described second fin
The thickness of layer 210 is identical, the most identical with the thickness of described thin oxide skin(coating) 209.
Control relatively low oxidizing temperature and shorter oxidization time in this step, with shape on real presently described first fin
Becoming asymmetric gate oxide level, specifically, described oxidizing temperature is 900-1200 DEG C, and described oxidization time is 10-300s,
More preferably 80-140s.
With reference to Figure 15, substrate deposits the 3rd semiconductor material layer, to cover described second grid region and part institute
Give an account of electric layer, form second grid electrode.
Specifically, substrate deposit the 3rd semiconductor material layer and planarize, then forming the photoresist layer of patterning,
3rd semiconductor material layer described in described photoresist layer as mask etch, to expose described dielectric layer, peels off described photoresist
Layer, to form second grid electrode, as preferably, described 3rd semiconductor material layer selects and the second semiconductor material layer, institute
State the material that semiconductor material layer is identical, such as silicon, polysilicon, SiC or SiGe, more preferably polysilicon.
The described dielectric layer that preceding step is formed in this step can be as the dielectric layer of described second grid.
Present invention also offers a kind of semiconductor device using said method to manufacture, described device is preparation 4 terminals
FinFET and the integrated morphology of standard FinFET, wherein said first fin contains the gate oxide level of different-thickness, shape
Become 4 terminals FinFET, and be positioned at right side for standard FinFET.
The invention provides a kind of side preparing 4 terminals FinFET and the transistor of the integrated morphology of standard FinFET
Method, during preparation 4 terminals FinFET, forms gate oxide level by first latter two steps, forms thickness different not
Symmetrical gate oxide level, described relatively thin gate oxide as driving gate oxide level (drive gate Tox),
Thicker gate oxide, as threshold voltage control gate oxide skin(coating) (Vth-control gate Tox), comes more preferably with this
Ground controls threshold voltage (thresholdvoltage, Vth), eliminates short-channel effect further, improves device performance.The most originally
Invent and be more prone to when described method prepares asymmetric gate oxide level control, improve the yield of device further.
Figure 16 is the process chart that the present invention prepares semiconductor device, comprises the following steps:
Step 201 provide support substrate that Semiconductor substrate, described substrate include stacking gradually, oxide insulating layer, half
Conductor material layer；
Step 202 forms hard mask layer over the substrate；
Step 203 patterns described hard mask layer, with semiconductor material layer described in exposed portion；
Step 204 forms clearance wall on the sidewall of described hard mask layer；
Step 205 is semiconductor material layer described in described hard mask layer and described clearance wall as mask etch, to expose
State the sidewall of semiconductor material layer and described oxide insulating layer, form first grid region；
The sidewall of the described semiconductor material layer that step 206 oxidation is exposed, to form the gate oxide in first grid region
Layer；
Step 207 deposits the second semiconductor material layer on the described oxide insulating layer exposed, and then planarizes and returns
Etching, makes described second semiconductor material layer concordant with described hard mask layer, to form first gate electrode；
Step 208 aoxidizes the top of described second semiconductor material layer, to form oxide, as dielectric layer；
Step 209 patterns remaining described hard mask layer, to form fin pattern；
Step 210 is semiconductor material layer described in described hard mask layer as mask etch, is positioned at described clearance wall to be formed
Following the first fin, it is positioned at the second fin below described fin pattern and second grid region；
Step 211 aoxidizes the sidewall of described semiconductor material layer, to form gate oxide on described second fin, in institute
State the gate oxide layers forming second grid region on the first fin；
Step 212 deposits the 3rd semiconductor material layer on substrate, described to cover described second grid region and part
Dielectric layer, forms second grid electrode.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and descriptive purpose, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member, it is understood that the invention is not limited in above-described embodiment, can also make more kinds of according to the teachings of the present invention
Variants and modifications, within these variants and modifications all fall within scope of the present invention.Protection scope of the present invention by
The appended claims and equivalent scope thereof are defined.
Claims (15)
1. a preparation method for semiconductor device, including:
There is provided Semiconductor substrate, support substrate that described substrate includes stacking gradually, oxide insulating layer, semiconductor material layer；
Form hard mask layer over the substrate；
Pattern described hard mask layer, with semiconductor material layer described in exposed portion；
The sidewall of described hard mask layer is formed clearance wall；
Semiconductor material layer described in described hard mask layer and described clearance wall as mask etch, to expose described semi-conducting material
The sidewall of layer and described oxide insulating layer, form first grid region；
The sidewall of the described semiconductor material layer that oxidation is exposed, to form the gate oxide layers in first grid region；
The described oxide insulating layer exposed deposits the second semiconductor material layer, then planarization etch-back, makes described
Second semiconductor material layer is concordant with described hard mask layer, to form first gate electrode；
Aoxidize the top of described second semiconductor material layer, to form oxide, as dielectric layer；
Pattern remaining described hard mask layer, to form fin pattern；
Semiconductor material layer described in described hard mask layer as mask etch, is positioned at the first fin below described clearance wall to be formed
Sheet, it is positioned at the second fin below described fin pattern and second grid region；
Aoxidize the sidewall of described semiconductor material layer, to form gate oxide on described second fin, at described first fin
The gate oxide layers in upper formation second grid region；
Substrate deposits the 3rd semiconductor material layer, to cover described second grid region and the described dielectric layer of part, is formed
Second grid electrode；
On described first fin, the thickness of the gate oxide layers in described first grid region is more than described second grid region
Gate oxide layers.
Method the most according to claim 1, it is characterised in that the thickness of the gate oxide formed on described first fin is not
With.
Method the most according to claim 1, it is characterised in that the thickness phase of the gate oxide formed on described second fin
With.
Method the most according to claim 1, it is characterised in that described hard mask layer is nitride layer.
Method the most according to claim 4, it is characterised in that described hard mask layer is SiN layer.
Method the most according to claim 1, it is characterised in that described clearance wall is oxide.
Method the most according to claim 1, it is characterised in that with described hard mask layer and described clearance wall as mask, choosing
Described semiconductor material layer is etched, to form first grid region with reactive ion.
Method the most according to claim 1, it is characterised in that described second semiconductor material layer is polysilicon layer.
Method the most according to claim 1, it is characterised in that the method patterning remaining described hard mask layer is:
Described hard mask layer is formed patterning photoresist layer, forms fin pattern, with described photoresist layer as mask etch
Described hard mask layer.
Method the most according to claim 9, it is characterised in that with described hard mask layer as mask, selects reactive ion erosion
Carve described semiconductor material layer, then peel off described photoresist layer, to form described first fin and the second fin.
11. methods according to claim 1, it is characterised in that described 3rd semiconductor material layer is polysilicon layer.
12. methods according to claim 1, it is characterised in that the forming method of described second grid electrode is:
Substrate deposit the 3rd semiconductor material layer and planarizes, patterning described 3rd semiconductor material layer, to expose
Give an account of electric layer, form second grid electrode.
13. methods according to claim 12, it is characterised in that deposit the 3rd semiconductor material layer smooth on substrate
Change, then form the photoresist layer of patterning, the 3rd semiconductor material layer described in described photoresist layer as mask etch, peel off
Described photoresist layer, to form second grid electrode.
14. methods according to claim 1, it is characterised in that described semiconductor device is 4 terminals FinFET and standard
The integrated morphology of FinFET.
15. 1 kinds use the semiconductor device that the described method of one of claim 1-14 manufactures.
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| CN101183686A (en) * | 2006-11-13 | 2008-05-21 | 国际商业机器公司 | Asymmetric multi-gated transistor and method for forming |
| CN101443912A (en) * | 2005-08-03 | 2009-05-27 | 国际商业机器公司 | Fin-type field effect transistor |
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| US8263446B2 (en) * | 2010-09-13 | 2012-09-11 | International Business Machines Corporation | Asymmetric FinFET devices |
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| US6800885B1 (en) * | 2003-03-12 | 2004-10-05 | Advance Micro Devices, Inc. | Asymmetrical double gate or all-around gate MOSFET devices and methods for making same |
| CN101443912A (en) * | 2005-08-03 | 2009-05-27 | 国际商业机器公司 | Fin-type field effect transistor |
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