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CN103426924A - Groove-type power MOSFET and manufacturing method thereof - Google Patents

Groove-type power MOSFET and manufacturing method thereof Download PDF

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Publication number
CN103426924A
CN103426924A CN2012101471436A CN201210147143A CN103426924A CN 103426924 A CN103426924 A CN 103426924A CN 2012101471436 A CN2012101471436 A CN 2012101471436A CN 201210147143 A CN201210147143 A CN 201210147143A CN 103426924 A CN103426924 A CN 103426924A
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China
Prior art keywords
drift region
groove
type power
preparation
doping content
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CN2012101471436A
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Inventor
周宏伟
阮孟波
吴宗宪
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Wuxi CSMC Semiconductor Co Ltd
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Wuxi CSMC Semiconductor Co Ltd
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Priority to CN2012101471436A priority Critical patent/CN103426924A/en
Priority to PCT/CN2012/076562 priority patent/WO2013170511A1/en
Publication of CN103426924A publication Critical patent/CN103426924A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention provides a groove-type power MOSFET and a manufacturing method thereof, and belongs to the technical field of a groove-type power MOSFET. The manufacturing method includes the steps that a semi-conductor substrate is provided, a first drift region grows and forms on the substrate, the first drift region is constructed and etched to form a second groove, a semi-conductor layer is formed in the second groove in an epitaxial growth mode so that a second drift region filling the bottom of the second groove partially can be formed, the doping concentration of the second drift region is higher than that of the first drift region, and a grid groove structure is formed in the second groove above the second drift region. The process of the manufacturing method is simple and reliable, and the on resistance of the groove-type power MOSFET formed in the method is small.

Description

Groove type power MOS FET and preparation method thereof
Technical field
The invention belongs to groove type power MOS FET(metal-oxide semiconductor fieldeffect transistor) technical field, the drift layer related under a kind of gate groove structure forms groove type power MOS FET reduced this regional resistivity and preparation method thereof by independent epitaxial process.
Background technology
Groove type power MOS FET is a kind of common power-type device, and it is one of high-current switch main flow device, is widely used in, in the high-voltage great-current situation, for example, being applied in synchronous rectification.And the conducting resistance of groove type power MOS FET is one of its very important parameter, for example, in the synchronous rectification application, conducting resistance is less, and energy conversion efficiency is higher.Therefore, the conducting resistance that reduces groove type power MOS FET is constantly pursued in this area.
Generally comprise drift (drift) district in groove type power MOS FET, the size of its resistance is very large on the whole conducting resistance impact of groove type power MOS FET.Therefore, reduce the conducting resistance that the resistance of drift region when break-over of device is conducive to reduce groove type power MOS FET.
U.S. Patent number is that US7202525B2, name are called in the patent of " Trench MOSFET with Trench Tip Implants ", also proposed to reduce the method for the resistance of drift region, be that groove end (Trench Tip) structure in drift layer forms by Implantation, and reduce its resistivity by ion implantation doping.But, in the preparation method and structure thereof of this patent, groove end (Trench Tip) is to form by the ion implantation doping composition, and be subject to the restriction of ion implantation technology method characteristic, the degree of depth of Implantation is limited, and particularly, when injecting the larger foreign atom of radius and quality, be difficult to form the groove end of high-dopant concentration.Therefore, this structure is limited aspect the conducting resistance that reduces drift region.
Summary of the invention
The object of the invention is to, reduce the conducting resistance of groove type power MOS FET.
For realizing above purpose or other purposes, the invention provides following technical scheme.
According to an aspect of of the present present invention, a kind of groove type power MOS FET is provided, at least comprise gate groove and drift layer, described drift layer comprises the second drift region under described gate groove structure and the first drift region outside described the second drift region, described the second drift region by independent epitaxial process, form so that the doping content of described the second drift region higher than the doping content of described the first drift region.
According to the groove type power MOS FET of one embodiment of the invention, wherein, the scope doping content scope of the doping content of described the second drift region is 1 * 10 15Ion/cm 3To 1 * 10 18Ion/cm 3.
Preferably, the thickness range of described the second drift region is 3 microns to 20 microns.
According to the groove type power MOS FET of one embodiment of the invention, wherein, the conduction type of described the second drift region is identical with the conduction type of described the first drift region.
According to another aspect of the present invention, the preparation method of a kind of groove type power MOS FET is provided, it comprises the following steps:
Semiconductor substrate is provided;
Form the first drift region at described Grown;
Described the first drift region patterned etch is formed to the second groove;
In described the second groove, the epitaxial growth semiconductor layer is filled the second drift region of described the second channel bottom with forming section ground, and the doping content of described the second drift region is higher than the doping content of described the first drift region; And
Form the gate groove structure above described the second drift region, in described the second groove.
According to the preparation method of one embodiment of the invention, wherein, form the step of described the second drift region, comprise step:
In described the second groove, the semiconductor layer of described the second groove is filled in epitaxial growth; And
Semiconductor layer in described the second groove is returned to etching to form described the second drift region.
According to the preparation method of further embodiment of this invention, wherein, the doping content scope of described the second drift region is 1 * 10 15Ion/cm 3To 1 * 10 18Ion/cm 3.
In the preparation method of described arbitrary embodiment before, preferably, the doping content of described the second drift region is normal distribution at the central axial line be parallel on the direction of described semiconductor substrate surface, based on described the second groove.
In the preparation method of described arbitrary embodiment before, preferably, the thickness range of described the second drift region is 3 microns to 20 microns; The thickness of described the second drift region is less than the thickness of described the first drift region.
Wherein, the conduction type of described the second drift region is identical with the conduction type of described the first drift region.
In the preparation method of described arbitrary embodiment before, preferably, the doping content scope of described the first drift region is 1 * 10 14Ion/cm 3To 1 * 10 17Atom/cm 3.
In the preparation method of described arbitrary embodiment before, preferably, the thickness range of described the first drift region is 3 microns to 40 microns.
In the preparation method of described arbitrary embodiment before, preferably, described the first drift region forms by epitaxial growth on described Semiconductor substrate.
Technique effect of the present invention is, the second drift region of gate groove structure below forms by independent epitaxial growth technology, it can form the zone of high-dopant concentration, low-resistivity, and, its thickness, doping content do not allow to be subject to process technology limit, therefore, can effectively reduce the conducting resistance of this groove type power MOS FET.In addition, its preparation method process is based on maturation process, simple and reliable.
The accompanying drawing explanation
From following detailed description by reference to the accompanying drawings, will make above and other purpose of the present invention and advantage more fully clear, wherein, same or analogous key element adopts identical label to mean.
Fig. 1 is the method flow schematic diagram for preparing groove type power MOS FET provided according to one embodiment of the invention.
Fig. 2 to Fig. 9 is the structural change schematic diagram corresponding to method flow shown in Fig. 1, and wherein, Fig. 9 is the cross section structure schematic diagram of the groove type power MOS FET that provides according to one embodiment of the invention.
Embodiment
What below introduce is some in a plurality of possibility embodiment of the present invention, aims to provide basic understanding of the present invention, is not intended to confirm key of the present invention or conclusive key element or limits claimed scope.Easily understand, according to technical scheme of the present invention, do not changing under connotation of the present invention other implementations that one of ordinary skill in the art can propose mutually to replace.Therefore, following embodiment and accompanying drawing are only the exemplary illustrations to technical scheme of the present invention, and should not be considered as of the present invention all or be considered as restriction or the restriction to technical solution of the present invention.
In the accompanying drawings, for the sake of clarity, exaggerated layer and regional thickness, and the shape facility such as mellow and full grade caused due to etching does not illustrate in the accompanying drawings.
In this paper describes, use directional terminology (such as " on ", D score, " back side ", " laterally " etc.) and the various structure embodiment that describe of similar terms mean the direction shown in accompanying drawing or the direction that can be understood by those skilled in the art.These directional terminology are used for relative description and clarification, rather than the orientation of any embodiment will be limited to concrete direction or orientation.
Below take groove type power NMOSFET and describe as preparation method and the structure thereof of example to groove type power MOS FET of the present invention.
The method flow schematic diagram for preparing groove type power MOS FET provided according to one embodiment of the invention is provided.Fig. 2, to the structural change schematic diagram Figure 9 shows that corresponding to method flow shown in Fig. 1, therefore, by the method shown in Fig. 1, finally forms the groove type power MOS FET 30 of the embodiment of the present invention as shown in Figure 9.In following Fig. 2 to Fig. 9, definition is the z coordinate direction perpendicular to the direction of semiconductor substrate surface, it is also the depth direction of groove, and the positive direction of z coordinate is for pointing to the direction of groove opening, and the negative direction of z coordinate is for pointing to the direction that is used to form the one side (being the back side of Semiconductor substrate) of drain electrode on Semiconductor substrate; The direction that definition is parallel to semiconductor substrate surface is the x coordinate direction.Below in conjunction with Fig. 2 to Fig. 9, the method for preparing groove type power MOS FET embodiment illustrated in fig. 9 is elaborated, and groove type power MOS FET cellular construction embodiment illustrated in fig. 9 is described simultaneously.
At first, step S110, provide N type semiconductor substrate 310.
Consult Fig. 2, Semiconductor substrate 310 can be selected the wafer (wafer) that adopts N-type highly doped, it is also the N-single crystal wafers, Semiconductor substrate 310 is finally in this embodiment between drift layer and drain electrode, it can be used for forming the drain terminal electrode, therefore, the doping content of Semiconductor substrate 310 is 1 * 10 19Ion/cm 3To 5 * 10 19Ion/cm 3Interior selection is for example 2.5 * 10 19Ion/cm 3.
Further, step S120, epitaxial growth n type semiconductor layer 320 on this Semiconductor substrate, and on semiconductor layer 320, grow oxide layer 391 and silicon nitride layer 392.
Consult Fig. 3, in this embodiment, epitaxially grown semiconductor layer 320 is the identical conduction type with Semiconductor substrate 310, and it is N-type, and still, its doping content will be lower than the doping content of Semiconductor substrate 310.Semiconductor layer 320 is used for forming the drift layer (i.e. the first drift region 320a) of groove type power MOS FET in final part, therefore, it selects relatively low doping content to guarantee that groove type power MOS FET's punctures the requirement of (BV) voltage performance.In this embodiment, the doping content scope of semiconductor layer 320 is 1 * 10 14Ion/cm 3To 1 * 10 17Ion/cm 3, for example be chosen as 5.9 * 10 15Ion/cm 3.Because its doping content is lower, can be easily (the second drift region 340 relatively formed thereafter) by the epitaxy technique formation of growing, but, the concrete growing method of semiconductor layer 320 is not restrictive, and any other membrane deposition method that can form the semiconductor layer of basic same performance can be applied to the present invention.The concrete thickness range of semiconductor layer 320 is 3 microns to 40 microns, for example, and 6 microns.After semiconductor layer 320 growth, mulched ground growth oxide layer 391 and silicon nitride layer 392 successively thereon, oxide layer 391 is as liner (PAD) oxide layer, and silicon nitride layer 392 is as the trench etching mask layer.It will be appreciated that, be not limited to the silicon nitride layer of the embodiment of the present invention as the concrete material category of trench etching mask layer.
Further, step S130, form groove 331 to semiconductor layer 320 patterned etch.
Consult Fig. 4, on oxide layer 391 and silicon nitride layer 392 at first composition form hole to expose the semiconductor layer part of wanting etching, the shape of the groove that the shape wish in this hole forms determines, thereby completed the composition of groove 331.Then make mask layer with silicon nitride layer 392, etching semiconductor layer 320 forms groove 331 downwards, and remaining semiconductor layer 320 will be mainly used in forming the first drift region 320a of drift layer.The concrete degree of depth of groove 331 is not more than the thickness of semiconductor layer 320, like this, prevents from being etched to Semiconductor substrate 310, by controlling the process conditions such as etch rate, time, can control the degree of depth of the groove 331 of etching formation.
Further, step S140, the semiconductor layer 340 of epitaxial growth high-dopant concentration in groove 331.
Consult Fig. 5, epitaxial growth technology (technique of the epitaxial growth semiconductor layer 320 before being different from) by other one or many forms semiconductor layer 340, semiconductor layer 340 is used for forming the second drift region (340a) of groove type power MOS FET, for the resistance that reduces the second drift region to reduce conducting resistance, the doping content of semiconductor layer 340 is higher than the doping content of semiconductor layer 320, in this embodiment, the doping content scope of semiconductor layer 340 is 1 * 10 15Ion/cm 3To 1 * 10 18Ion/cm 3, and its doped chemical is in particular As(arsenic), P(phosphorus) or Sb(antimony).In addition, the doping content of semiconductor layer 340 is not probably to distribute equably with a certain value in above-mentioned scope, but change the ground non-uniform doping in the certain limit value, for example, on the x direction, centered by the central axial line of groove 331, the doping content of semiconductor layer 340 is near normal distribution (the central axial line position, doping content is relatively the highest).
After epitaxial growth semiconductor layer 340, the smooth technique of available chemical machinery (CMP) makes flattening wafer surface and removes oxide layer 391 and silicon nitride layer 392 as shown in Figure 4.
Further, step S150, composition returns etching semiconductor layer 340 to form the second drift region 340a.
Consult Fig. 6, particularly, silicon oxide layer 393 is as the etch mask layer of this time etching process, and its thickness can be for example 1000 to 8000 dusts.After returning etched portions semiconductor layer 340, the part semiconductor layer 340 that remains in groove 331 bottoms also can be called the extension drift region as the second drift region 340a().The degree of depth of returning etching can determine the thickness of the second drift region 340a, and in this embodiment, the thickness range of the second drift region 340a is 3 microns to 20 microns, and for example, 5 microns, its thickness is generally less than the thickness of the first drift region 320a.
The second drift region formed with respect to the ion implantation doping of prior art, as described in background technology, its thickness condition must be limited by the degree of depth of Implantation, particularly to the atomic radiuses such as As, Ph, Sb and quality larger doped chemical all, its degree of depth less, not obvious to the conducting resistance effect that improves drift layer.While adopting above process process to form the second drift region 340a, its thickness and doping content all are not subject to the ion implantation technology condition restriction, easily form high-dopant concentration, the second darker drift region 340a of thickness, therefore, can very effectively reduce groove type power MOS FET(30) conducting resistance.
, returning after etching finishes, the bottom of groove 331 is originally filled by the second drift region 340a simultaneously, and the channel shaped of the second drift region 340a upper section becomes groove 332, and groove 332 is interior will be used to form groove type power MOS FET(30) the gate groove structure.
Further, step S160, remove mask oxide layer 393.Consult Fig. 7, mask oxide layer 393 removal that is etched.
Further, step S170, the interior formation gate groove of groove 332 structure above the second drift region 340a.
Consult Fig. 8, groove 332 forms the gate groove structure interior can the preparation, the gate groove structure comprises gate dielectric layer 352 and gate electrode 351, gate dielectric layer 352 for example can form sacrifice layer by first wet-oxygen oxidation, remove after this sacrifice layer dry-oxygen oxidation again forms, gate electrode 351 is highly doped polysilicon, and resistivity is low.It should be noted that, concrete structure of gate groove structure and preparation method thereof is not subject to the restriction of the embodiment of the present invention.
Simultaneously, the first drift region 320a top has also formed the 362He source region, contact zone 370 of body layer 361, low-resistivity, and the conduction type of body layer 361 and contact zone 362 is the P type, be also the doping of P type, and it is different from the conduction type (N-type) of drift layer; The conduction type in source region 370 is N-type, and its doping content is relatively high.
Further, step S180, continue formation source electrode, drain electrode, until preparation forms groove type power MOS FET 30.
Consult Fig. 9, continue to form the drain electrode 383 at dielectric layer 381, source (Source) electrode 382 and Semiconductor substrate 310 back sides.
So far, the groove type power MOS FET 30 of embodiment basically forms as shown in Figure 9.Above preparation method's process uncomplicated, and the technical maturities such as the etching of deep trench, epitaxial growth filling, simple and reliable on technique.
Although above embodiment only be take groove type power NMOSFET 30 and described as example, those skilled in the art are according to above enlightenment and instruction, and the method step based on similar, can prepare and form groove type power PMOSFET.
Consult the groove type power MOS FET 30 shown in Fig. 9, the drift layer part of its gate groove structure below, be also the second drift region 340a, is to form by independent epitaxy technique growth, it can form zone highly doped, low-resistivity relatively, thereby effectively reduces its conducting resistance.By being 68V to operating voltage, groove type power NMOSFET emulation shows, the on-resistance per unit of this device can reduce (in the situation of Vgs=10V) more than 13%; And the second drift region 340a does not affect the performance parameters such as the puncture voltage of groove type power NMOSFET and turn-on threshold voltage.
Above example has mainly illustrated the preparation method of groove type power MOS FET of the present invention and the groove type power MOS FET of prepared formation thereof.Although only the some of them embodiments of the present invention are described, those of ordinary skills should understand, and the present invention can be within not departing from its purport and scope implements with many other forms.Therefore, the example of showing and execution mode are regarded as illustrative and not restrictive, in the situation that do not break away from spirit of the present invention as defined as appended each claim and scope, the present invention may be contained various modifications and replacement.

Claims (13)

1. a groove type power MOS FET, at least comprise gate groove and drift layer, it is characterized in that, described drift layer comprises the second drift region under described gate groove structure and the first drift region outside described the second drift region, described the second drift region by independent epitaxial process, form so that the doping content of described the second drift region higher than the doping content of described the first drift region.
2. groove type power MOS FET as claimed in claim 1, is characterized in that, the scope doping content scope of the doping content of described the second drift region is 1 * 10 15Ion/cm 3To 1 * 10 18Ion/cm 3.
3. groove type power MOS FET as claimed in claim 1 or 2, is characterized in that, the thickness range of described the second drift region is 3 microns to 20 microns.
4. groove type power MOS FET as claimed in claim 1, is characterized in that, the conduction type of described the second drift region is identical with the conduction type of described the first drift region.
5. the preparation method of a groove type power MOS FET, is characterized in that, comprises the following steps:
Semiconductor substrate is provided;
Form the first drift region at described Grown;
Described the first drift region patterned etch is formed to the second groove;
In described the second groove, the epitaxial growth semiconductor layer is filled the second drift region of described the second channel bottom with forming section ground, and, make the doping content of the doping content of described the second drift region higher than described the first drift region; And
Form the gate groove structure above described the second drift region, in described the second groove.
6. preparation method as claimed in claim 5, is characterized in that, forms the step of described the second drift region, comprises step:
In described the second groove, the semiconductor layer of described the second groove is filled in epitaxial growth; And
Semiconductor layer in described the second groove is returned to etching to form described the second drift region.
7. preparation method as described as claim 5 or 6, is characterized in that, the doping content scope of described the second drift region is 1 * 10 15Ion/cm 3To 1 * 10 18Ion/cm 3.
8. preparation method as claimed in claim 7, is characterized in that, the doping content of described the second drift region is normal distribution at the central axial line be parallel on the direction of described semiconductor substrate surface, based on described the second groove.
9. preparation method as described as claim 5 or 6, is characterized in that, the thickness range of described the second drift region is 3 microns to 20 microns.
10. preparation method as described as claim 5 or 6, is characterized in that, the conduction type of described the second drift region is identical with the conduction type of described the first drift region.
11. preparation method as claimed in claim 10, is characterized in that, the doping content scope of described the first drift region is 1 * 10 14Ion/cm 3To 1 * 10 17Ion/cm 3.
12. preparation method as claimed in claim 10, is characterized in that, the thickness range of described the first drift region is 3 microns to 40 microns.
13. preparation method as described as claim 5 or 6, is characterized in that, described the first drift region forms by epitaxial growth on described Semiconductor substrate.
CN2012101471436A 2012-05-14 2012-05-14 Groove-type power MOSFET and manufacturing method thereof Pending CN103426924A (en)

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CN2012101471436A CN103426924A (en) 2012-05-14 2012-05-14 Groove-type power MOSFET and manufacturing method thereof
PCT/CN2012/076562 WO2013170511A1 (en) 2012-05-14 2012-06-07 Trench-type power mosfet and preparation method therefor

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CN103928346A (en) * 2014-04-21 2014-07-16 西安电子科技大学 Method for preparing UMOSFET device with N-type heavy doping drift layer table top formed through epitaxial growth

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CN102254796A (en) * 2010-05-20 2011-11-23 上海华虹Nec电子有限公司 Method for forming alternative arrangement of P-type and N-type semiconductor thin layers

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US5929481A (en) * 1996-07-19 1999-07-27 Siliconix Incorporated High density trench DMOS transistor with trench bottom implant
US20060038223A1 (en) * 2001-07-03 2006-02-23 Siliconix Incorporated Trench MOSFET having drain-drift region comprising stack of implanted regions
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CN101752225A (en) * 2008-12-04 2010-06-23 上海华虹Nec电子有限公司 Multistage etching and filling method of ultra-deep groove
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CN103928346A (en) * 2014-04-21 2014-07-16 西安电子科技大学 Method for preparing UMOSFET device with N-type heavy doping drift layer table top formed through epitaxial growth
CN103928346B (en) * 2014-04-21 2016-08-24 西安电子科技大学 It is epitaxially-formed the UMOSFET device preparation method of N-type heavy doping drift layer table top

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