CN103399607B - The high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit - Google Patents

Abstract

The present invention relates to power management techniques.The invention solves existing low pressure difference linear voltage regulator mostly to increase circuit complexity, lower the problem that load capacity and increase output voltage noise etc. are cost solution output voltage generation due to voltage spikes, provide a kind of high PSR low pressure difference linear voltage regulator of integrated slew rate enhancing circuit, its technical scheme can be summarized as: compared with existing LDO, add slew rate enhancing circuit and building-out capacitor, and the normal phase input end of error amplifier is connected with reference voltage source, inverting input is connected with resistive feedback circuit, output terminal is connected with the input end of slew rate enhancing circuit, the output terminal of slew rate enhancing circuit is connected with the grid of Correctional tube, one end of building-out capacitor is connected with the inverting input of error amplifier, the other end of building-out capacitor is connected with output terminal.The invention has the beneficial effects as follows, improve transient response, be applicable to low pressure difference linear voltage regulator.

Description

High PSR low dropout regulator integrated with slew rate enhancement circuit

Technical Field

The invention relates to a power supply management technology, in particular to a technology of a low dropout linear regulator.

Background

The low dropout regulator (LDO) is an important circuit in the field of power management, and has the advantages of low output noise, low cost, simple structure, low power consumption and the like. With the continuous improvement of the power supply requirement of the electronic system, the traditional LDO can not meet the requirements of people on indexes such as chip noise, power supply rejection, transient performance and the like. Therefore, research on high-performance LDOs has become a research hotspot in the field of power management.

As shown in fig. 1, a typical LDO circuit generally comprises a reference voltage source Vref, an error amplifier, a power voltage input terminal VDD, a tuning tube Mp, and a resistance feedback circuit, wherein a positive input terminal of the error amplifier is connected to the resistance feedback circuit, a negative input terminal of the error amplifier is connected to the reference voltage source Vref, an output terminal of the error amplifier is connected to a gate of the tuning tube Mp, a drain of the tuning tube Mp is an output terminal, and is connected to the resistance feedback circuit, a source of the tuning tube Mp is connected to the power voltage input terminal VDD, specifically, the resistance feedback circuit comprises a first resistor R1 and a second resistor R2, one end of the first resistor R1 is connected to one end of the second resistor R2 and is connected to the positive input terminal of the error amplifier, the other end of the first resistor R1 is connected to the output terminal, the other end of the second resistor is connected to a ground, the tuning tube Mp generally employs a MOS transistor, such as a PMOS transistor, when in use, a, the off-chip capacitor CL is connected in parallel with the load, and the principle is that the stable voltage generated by the band-gap reference source and the negative feedback control loop obtain the output voltage which is basically not changed along with the environment. In order to improve the load capacity, the area of the general adjusting tube Mp is large, so that a parasitic capacitor of dozens of pF is formed on the gate of the adjusting tube Mp, and meanwhile, in order to improve the power consumption of the LDO, the static working current is small, so that the charging and discharging of the gate of the adjusting tube Mp are slow, when the output current jumps, the output voltage generates large overshoot and undershoot voltage spikes, and meanwhile, the voltage recovery stability time is long. Some documents propose corresponding solutions to this problem, for example, in documents "Mohammad Al-layout, Hoi leave and Raul per z. a Transient-enhanced Low-precision Current Low-drift With Buffer Impedance adaptation. ieee jour nal OF SOLID-STATE CIRCUITS, vol.42, No.8, AUGUST 2007", which add a Transient enhancement circuit between the error amplifier and the tuning tube, but increase the complexity OF system compensation, and can only improve the slew rate OF the LDO to a certain extent, while the power supply rejection capability at high frequencies is not greatly improved.

In recent years, many high power supply rejection ratio LDO solutions have appeared in the paper, but most of them come at the cost of increased circuit complexity, reduced load capability, and increased output voltage noise, and many of them do not get much improvement in the high frequency band, especially above 1 MHz.

Disclosure of Invention

The invention aims to overcome the defect that the output voltage generates a voltage peak at the cost of increasing circuit complexity, reducing load capacity, increasing output voltage noise and the like of the conventional low dropout linear regulator, and provides a high-PSR low dropout linear regulator integrated with a slew rate enhancement circuit.

The invention solves the technical problem, adopts the technical scheme that the high PSR low-dropout linear voltage regulator integrated with a slew rate enhancement circuit comprises a reference voltage source, an error amplifier, a power voltage input end, an adjusting tube and a resistance feedback circuit, and is characterized by further comprising the slew rate enhancement circuit and a compensating capacitor, wherein the positive phase input end of the error amplifier is connected with the reference voltage source, the negative phase input end of the error amplifier is connected with the resistance feedback circuit, the output end of the error amplifier is connected with the input end of the slew rate enhancement circuit, the output end of the slew rate enhancement circuit is connected with the grid electrode of the adjusting tube, the drain electrode of the adjusting tube is the output end and is connected with the resistance feedback circuit, the source electrode of the adjusting tube is connected with the power voltage input end, one end of the compensating capacitor is connected with the negative phase input end of the.

Specifically, the error amplifier is an amplifier with a-3 dB bandwidth larger than 2 MHz.

Further, the error amplifier comprises a bias voltage input end, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube, wherein the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the second PMOS tube is connected with the drain electrode of the second PMOS tube, the drain electrode of the first PMOS tube is connected with the grid electrode of the fourth NMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the third PMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, the drain electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube, the grid electrode of the fifth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the grid electrode of the first NMOS tube is the inverse phase input end of the error amplifier, and the source is connected with the, the grid electrode of the second NMOS tube is a positive phase input end of the error amplifier, the source electrode of the second NMOS tube is connected with the drain electrode of the third NMOS tube, the source electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected with a power voltage input end, the source electrodes of the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube are all connected with the ground, and the grid electrode of the third NMOS tube is connected with a bias voltage input end so as to generate tail current.

Specifically, the slew rate enhancement circuit comprises a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor, wherein the fifth PMOS transistor and the sixth NMOS transistor form a first inverter, the seventh PMOS transistor and the seventh NMOS transistor form a second inverter, an input end of the first inverter is connected to an output end of the error amplifier, an output end of the first inverter is connected to a drain of the sixth PMOS transistor and an input end of the second inverter, a gate of the sixth PMOS transistor is connected to a drain thereof and to an input end of the second inverter, an output end of the second inverter is connected to a gate of the eighth NMOS transistor, a drain thereof, and a gate of the ninth NMOS transistor, the gate of the eighth NMOS transistor is connected to a gate of the ninth NMOS transistor, and a gate of the eighth POMS transistor is connected to the drain thereof and to a gate of the adjusting transistor.

Specifically, the resistance feedback circuit comprises a first resistor and a second resistor, one end of the first resistor is connected with one end of the second resistor and is connected with the inverting input end of the error amplifier, the other end of the first resistor is connected with the output end, and the other end of the second resistor is connected with the ground wire.

Still further, the adjusting tube is a PMOS tube.

The off-chip capacitor is characterized by further comprising an off-chip capacitor, wherein one end of the off-chip capacitor is connected with the output end, the other end of the off-chip capacitor is connected with the ground wire, the parasitic resistance of the off-chip capacitor is smaller than 10m omega, and the capacitance value of the off-chip capacitor is larger than 2.2 uF.

The high PSR low dropout regulator of the integrated slew rate enhancement circuit has the advantages that the slew rate is enhanced through the integrated slew rate enhancement circuit, transient response is improved, and meanwhile, the power supply suppression capability is enhanced, especially under high frequency.

Drawings

Fig. 1 is a system block diagram of a conventional LDO.

FIG. 2 is a system block diagram of the high PSR low dropout regulator with an integrated slew rate enhancement circuit of the present invention.

Fig. 3 is a circuit diagram of the high PSR low dropout regulator with the slew rate enhancement circuit integrated therein according to an embodiment of the present invention.

FIG. 4 is a graph of the gain phase of the output load 200mA with 2V supply voltage in accordance with the present invention.

FIG. 5 is a graph of the gain phase of the output load 0A with a power supply voltage of 2V according to an embodiment of the present invention.

FIG. 6 is a transient characteristic diagram of the embodiment of the present invention in which the power supply voltage 2V output load 1us jumps from 0A to 200mA and then from 200mA to 0A.

Fig. 7 is a transient characteristic diagram of the power supply voltage 1us jumping from 2V to 3.3V under the output load 200mA in the embodiment of the present invention.

Fig. 8 is a characteristic diagram of power supply rejection ratio under different output loads according to the embodiment of the present invention.

Wherein Vref is reference voltage source, VDD is power voltage, Mp is adjusting tube, Cm is compensating capacitor, Va is bias voltage, MA is₁Is a first PMOS transistor, MA₂Is a second PMOS transistor, MA₃Is a third PMOS transistor, MA₄Is a fourth PMOS transistor, MA₅Is a first NMOS transistor, MA₆Is a second NMOS transistor, MA₇Is a third NMOS transistor, MA₈Is a fourth NMOS transistor, MA₉Is a fifth NMOS transistor, MB₁Is a fifth PMOS transistor, MB₂Is a sixth PMOS transistor, MB₃Is a seventh PMOS transistor, MB₄Is an eighth PMOS transistor, MB₅Is a sixth NMOS transistor, MB₆Is a seventh NMOS transistor, MB₇Is an eighth NMOS transistor, MB₈The ninth NMOS transistor, R1 is the first resistor, R2 is the second resistor, CL is the off-chip capacitor, and RL is the load.

Detailed Description

The technical solution of the present invention is described in detail below with reference to the embodiments and the accompanying drawings.

The system block diagram of the high PSR low dropout linear regulator of the integrated slew rate enhancement circuit of the present invention is shown in FIG. 2. The invention discloses a high PSR low-dropout linear voltage regulator integrated with a slew rate enhancement circuit, which comprises a reference voltage source Vref, an error amplifier, a power voltage input end, an adjusting tube Mp, a resistance feedback circuit, a slew rate enhancement circuit and a compensating capacitor Cm, wherein the positive phase input end of the error amplifier is connected with the reference voltage source Vref, the negative phase input end of the error amplifier is connected with the resistance feedback circuit, the output end of the error amplifier is connected with the input end of the slew rate enhancement circuit, the output end of the slew rate enhancement circuit is connected with the grid electrode of the adjusting tube Mp, the drain electrode of the adjusting tube Mp is the output end and is connected with the resistance feedback circuit, the source electrode of the adjusting tube Mp is connected with the power voltage input end, one end of the compensating capacitor Cm is connected with the negative phase input end of the error.

Examples

The system block diagram of the high PSR low dropout regulator integrated with the slew rate enhancement circuit according to the embodiment of the present invention is shown in fig. 2, and the circuit schematic diagram is shown in fig. 3. The high PSR low dropout regulator of the integrated slew rate enhancement circuit comprises a reference voltage source Vref, an error amplifier, a power voltage input end, an adjusting tube Mp, a resistance feedback circuit, a slew rate enhancement circuit and a compensating capacitor Cm, wherein the positive phase input end of the error amplifier is connected with the reference voltage source Vref, the negative phase input end of the error amplifier is connected with the resistance feedback circuit, the output end of the error amplifier is connected with the input end of the slew rate enhancement circuit, the output end of the slew rate enhancement circuit is connected with the grid electrode of the adjusting tube Mp, the drain electrode of the adjusting tube Mp is the output end and is connected with the resistance feedback circuit, the source electrode of the adjusting tube Mp is connected with the power voltage input end, one end of the compensating capacitor Cm is connected with the negative phase input end of the error amplifier, the other end of the compensating capacitor Cm is connected with the output end, in the present example, the adjusting tube.

The error amplifier in this example is an amplifier with-3 dB bandwidth greater than 2MHz, and comprises a bias voltage input end, a first PMOS tube MA₁And a second PMOS tube MA₂And the third PMOS tube MA₃And the fourth PMOS tube MA₄The first NMOS transistor MA₅And a second NMOS transistor MA₆And a third NMOS transistor MA₇And the fourth NMOS tube MA₈And a fifth NMOS transistor MA₉Wherein, the first PMOS tube MA₁Gate of and second PMOS transistor MA₂Is connected to the gate of the second PMOS transistor MA₂Is connected with its own drain electrode, a first PMOS transistor MA₁Drain electrode of (1) and fourth NMOS transistor MA₈Is connected to the gate of the fourth NMOS transistor MA₈Is connected with its own drain electrode, and a second PMOS transistor MA₂Gate of and the first NMOS transistor MA₅Drain electrode of (1) a third PMOS transistor MA₃Is connected with its own drain electrode and with the second NMOS transistor MA₆Drain electrode of (1) a fourth PMOS transistor MA₄Of a grid electrodeAnd a third PMOS transistor MA₃Is connected with the grid electrode of the first NMOS tube MA₉Is connected to the gate of the fifth NMOS transistor MA₉Is connected with its own drain, a first NMOS transistor MA₅The grid of the first NMOS transistor is the inverting input end of the error amplifier, the source and the third NMOS transistor MA₇Drain electrode of (1) a second NMOS transistor MA₆The grid of the first NMOS transistor is the positive phase input end of the error amplifier, the source and the third NMOS transistor MA₇Is connected to the drain of the first PMOS transistor MA₁And a second PMOS tube MA₂And the third PMOS tube MA₃And a fourth PMOS transistor MA₄Is connected with the power supply voltage input end, and a third NMOS transistor MA₇And the fourth NMOS tube MA₈And a fifth NMOS transistor MA₉All source stages of (3) are connected to ground, and a third NMOS transistor MA₇Is connected to a bias voltage input terminal for inputting a bias voltage Va to generate a tail current. In order to make the error amplifier not introduce a low-frequency pole, the output resistance Ro of the error amplifier cannot be too large, and the tail current of the error amplifier should take a relatively moderate value and the low-frequency gain A of the error amplifier should take a relatively moderate value in consideration of reducing static power consumption and increasing slew rate_EA50dB, and an output pole of 3M Hz.

The slew rate enhancement circuit in this example comprises a fifth PMOS transistor MB₁Sixth PMOS transistor MB₂Seventh PMOS transistor MB₃Eighth PMOS transistor MB₄And a sixth NMOS transistor MB₅And a seventh NMOS transistor MB₆And the eighth NMOS transistor MB₇And a ninth NMOS transistor MB₈Wherein, the fifth PMOS tube MB₁And a sixth NMOS transistor MB₅Form a first inverter, a seventh PMOS transistor MB₃And a seventh NMOS transistor MB₆A second phase inverter is formed, the input end of the first phase inverter is connected with the output end of the error amplifier, and the output end of the first phase inverter is connected with a sixth PMOS tube MB₂A sixth PMOS transistor MB having a drain connected to the input terminal of the second inverter₂A gate connected to the drain of the NMOS transistor and connected to the input terminal of the second inverter, and an output terminal of the second inverter connected to the eighth NMOS transistor MB₇Grid, drain and ninth NMOS transistor MB₈Gate connected, eighth NMOS transistor MB₇Grid and ninth NMOS transistor MB₈Grid connection, eighth POMS tube MB₄The grid is connected with the drain electrode of the adjusting tube and is connected with the grid of the adjusting tube Mp.

The resistor feedback circuit in this example includes a first resistor R1 and a second resistor R2, one end of the first resistor R1 is connected to one end of the second resistor R2 and to the inverting input terminal of the error amplifier, the other end of the first resistor R1 is connected to the output terminal, and the other end of the second resistor R2 is connected to ground.

When the off-chip capacitor CL is used, the load RL is bridged between the output end and the ground wire, the off-chip capacitor CL is connected with the load RL in parallel, namely one end of the off-chip capacitor CL is connected with the output end, the other end of the off-chip capacitor CL is connected with the ground wire, the parasitic resistance of the off-chip capacitor CL is less than 10m omega, and the capacitance value of the off-chip capacitor CL is more than 2.2 uF.

The key point of the invention is that the slew rate enhancement circuit has the function of rapidly changing the grid input of the adjusting tube Mp when the load changes, so that the output voltage is adjusted to be stable in a very short time.

Under stable conditions, the eighth PMOS transistor MB₄Mirror load RL current, while biasing the ninth NMOS transistor MB₈Eighth NMOS transistor MB₇Ninth NMOS transistor MB of mirror image₈Current, ratio 1: k, eighth NMOS transistor MB₇Fixing the grid voltage; due to the eighth NMOS tube MB₇The gate voltage is fixed, so the input voltage of the second inverter is also fixed; sixth PMOS tube MB₂Mirror image seventh PMOS tube MB₃And the sixth PMOS transistor MB₂Diode connected so that the output pole of the first inverter operates at very high frequencies; the output end of the first inverter is connected with the input end of the second inverter, and the voltage of the input end of the second inverter is fixed, namely the voltage of the output end of the first inverter is fixed, so that the voltage of the input end of the first inverter is fixed.

When the load jumps from light load to heavy load, the output voltage has undershoot voltage, the undershoot voltage is amplified by the error amplifier, the input end of the first phase inverter is quickly charged, the input voltage of the first phase inverter is increased, and therefore the first phase inverter quickly discharges for the capacitor of the output end and flows through the sixth PMOS pipe MB₂Will increase, the input voltage of the second inverter will decrease rapidly, the second inverter charges the output capacitor rapidly, and the ninth NMOS transistor MB₈Gate voltage increases, ninth NMOS transistor MB₈And a larger current flows to discharge for the grid electrode of the adjusting tube, and finally the system is stable. When the load jumps from heavy load to light load, the output voltage has an overshoot voltage, the input end of the first phase inverter is quickly discharged and the input voltage of the first phase inverter is reduced through the amplification of the error amplifier, so that the first phase inverter quickly charges the capacitor at the output end and flows through the sixth PMOS transistor MB₂Will decrease, the input voltage of the second inverter will increase rapidly, the second inverter will discharge the output capacitance rapidly, and the ninth NMOS transistor MB₈Gate voltage is reduced, eighth PMOS transistor MB₄And a larger current flows to charge the grid electrode of the adjusting tube, and finally the system is stable.

The slew rate enhancement circuit greatly improves the transient response speed and effectively reduces the peak of the output voltage.

For the slew rate enhancement circuit: the output end of the first phase inverter is connected with a sixth PMOS tube MB in a diode connection mode₂So that the zero pole point of the output end of the first inverter operates at a very high frequency; the output end of the second phase inverter is connected with an eighth NMOS tube MB in a diode connection mode₇So that the zero pole point of the output end of the second inverter works under the extremely high frequency; eighth PMOS transistor MB₄In the diode connection mode, the gate of the adjusting tube Mp introduces a high-frequency pole. Therefore, the slew rate enhancement circuit does not introduce redundant low-frequency poles, and the whole system has three poles and one compensation zero in 10 MHz.

The three poles are respectively as follows:

$P1=\frac{1}{\mathrm{CL}*\mathrm{Rout}}$

$P2=\frac{1}{R_P*C_P}$

$P3=\frac{1}{C_O*R_O}$

p1 is an output pole corresponding to the output end, P2 is Rp and Cp corresponding to the gate pole of the adjusting tube Mp, P3 is Ro and Co corresponding to the output pole of the error amplifier, Resr is the parasitic resistance of the off-chip capacitor, Rp is the parasitic resistance of the gate of the adjusting tube, Cp is the parasitic capacitance of the gate of the adjusting tube, Co is the load capacitance of the error amplifier, Ro is the output resistance of the error amplifier, Rout is the output equivalent resistance of the LDO, Rout =1/(gdsp + GL), gdsp is the output equivalent conductance of the adjusting tube Mp, and GL is the reciprocal of the load resistance RL.

The compensation capacitor Cm and the first resistor R1 and the second resistor R2 in the resistor feedback circuit generate a pair of zero poles, and the zero points are as follows:

$\mathrm{Zm}=\frac{1}{\mathrm{Cm}*R_1}$

the poles are:

$\mathrm{Pm}=\frac{1}{\mathrm{Cm}*R_1//R_2}$

and (3) stability analysis:

the output pole P1 of the output end is used as a main pole, the load capacitance is more than 2.2uF, in order not to introduce a low-frequency zero and influence the system stability, and the series parasitic resistance Resr of the off-chip capacitor CL is less than 10m omega.

The gate of the adjusting tube Mp introduces a secondary pole P₂Due to the eighth PMOS transistor MB₄In the form of a diode connection, then:

<math> <mrow> <mi>Rp</mi> <mo>&ap;</mo> <mfrac> <mn>1</mn> <mrow> <mi>gmb</mi> <mn>4</mn> </mrow> </mfrac> </mrow> </math>

<math> <mrow> <msub> <mi>P</mi> <mn>2</mn> </msub> <mo>&ap;</mo> <mfrac> <mrow> <mi>gmb</mi> <mn>4</mn> </mrow> <mi>Cp</mi> </mfrac> </mrow> </math>

wherein gmb4 is the eighth PMOS tube MB₄Transconductance. Design the eighth PMOS transistor MB₄The width-to-length ratio makes gmb4 large enough to push the secondary pole P2 to more than 100 times the primary pole P1, ensuring system stability.

Because the output resistance Ro of the error amplifier is small and the load capacitance Co is also small, the pole P is generated₃Will operate at high frequencies.

Compensation capacitor Cm and first resistor R in resistor feedback circuit₁A second resistor R₂Generating a pair of zero poles, Zm and Pm, and designing a first resistor R₁And a second resistor R₂Such that zero Zm compensates for the error amplifier output pole P₃And simultaneously, the generated pole Pm is enabled to work at a very high frequency. The introduction of the compensation capacitor Cm improves the stability of the system very well.

The high PSR low dropout linear regulator of the integrated slew rate enhancement circuit also has high power supply rejection capability, the slew rate enhancement circuit can improve the gain of the whole loop, and the low dropout linear regulator under low frequency is in direct proportion to the power supply rejection capability and the open loop gain, thereby improving the power supply rejection ratio under low frequency.

Low frequency open loop gain Aol is as follows:

<math> <mrow> <mi>Aol</mi> <mo>=</mo> <mfrac> <mrow> <mi>&beta;</mi> <mo>*</mo> <msub> <mi>A</mi> <mi>EA</mi> </msub> <mo>*</mo> <mi>Gm</mi> <mo>*</mo> <mi>gmp</mi> </mrow> <mrow> <mi>gmb</mi> <mn>4</mn> <mo>*</mo> <mrow> <mo>(</mo> <mi>gdsp</mi> <mo>+</mo> <mi>GL</mi> <mo>)</mo> </mrow> </mrow> </mfrac> <mo>=</mo> <mfrac> <mrow> <mi>&beta;</mi> <mo>*</mo> <msub> <mi>A</mi> <mi>EA</mi> </msub> <mo>*</mo> <mi>Gm</mi> <mo>*</mo> <mi>gmp</mi> <mo>*</mo> <mi>Rout</mi> </mrow> <mrow> <mi>gmb</mi> <mn>4</mn> </mrow> </mfrac> </mrow> </math>

wherein,for feedback factor, gmp is transconductance of the adjusting tube Mp, gmb4 is an eighth PMOS tube MB₄Gm is the equivalent transconductance of the slew rate enhancement circuit, A_EAFor error amplifier gain, Rout is output equivalent resistance, gdsp is workThe output admittance of the rate tube Mp, GL is the inverse of the load resistance. .

Since error amplifier output pole P1 is compensated for by the zero generated by compensation capacitor Cm, error amplifier output pole P1 and compensation capacitor Cm do not affect PSR. By calculation, the high-frequency small-signal output voltage v_outAnd a high-frequency small-signal input power supply voltage v_inThe ratio of (A) to (B) is as follows:

<math> <mrow> <mfrac> <msub> <mi>v</mi> <mi>out</mi> </msub> <msub> <mi>v</mi> <mi>in</mi> </msub> </mfrac> <mo>&ap;</mo> <mfrac> <mrow> <mi>gdsp</mi> <mrow> <mo>(</mo> <mi>gmb</mi> <mn>4</mn> <mo>+</mo> <mi>sCp</mi> <mo>)</mo> </mrow> </mrow> <mrow> <mrow> <mo>(</mo> <mi>sCL</mi> <mo>+</mo> <mi>gdsp</mi> <mo>+</mo> <mi>GL</mi> <mo>)</mo> </mrow> <mrow> <mo>(</mo> <mi>sCp</mi> <mo>+</mo> <mi>gmb</mi> <mn>4</mn> <mo>)</mo> </mrow> <mo>+</mo> <mi>Aol</mi> <mo>*</mo> <mi>gmb</mi> <mn>4</mn> <mo>*</mo> <mrow> <mo>(</mo> <mi>gdspGL</mi> <mo>)</mo> </mrow> </mrow> </mfrac> </mrow> </math>

the PSR transfer function has a zero at frequencyThe zero will cause the system PSR to decrease, however soon two poles are created, the first pole canceling the weakening of the PSR by the zero and the second pole causing the system PSR to increase. The equivalent inductance of the load capacitance at higher frequencies will cause the overall system PSR to decrease.

As shown in fig. 4, a gain phase plot of 200mA output load is shown for a supply voltage of 2V. A is the phase curve and B is the gain curve. When the load is 200mA, the phase margin is 75.26 degrees, and the system is stable.

As shown in fig. 5, a gain phase plot of the power supply voltage 2V output load 0A is shown. A is the phase curve and B is the gain curve. At a load of 0A, the phase margin is 77.15 °, and the system is stable.

The structure of the document mentioned in the background art is redesigned by using the same process library, the same power consumption, the same load RL and the off-chip capacitor CL as in the present invention, and fig. 6 and 7 compare the load regulation rate and the linear regulation rate of the LDO of the structure and the LDO of the present invention.

As shown in fig. 6, the transient characteristic diagram is shown in which the output load 1us jumps from 0A to 200mA and then from 200mA to 0A for the supply voltage 2V. A is the change curve OF the output voltage OF the LDO along With the load in the document (Mohammad Al-Shuukh, Hoi mean and Raul Perez. ATransient-Enhanced Low-Quiescent Current Low-drop Regulator With buffer impedance attention, IEEE JOURNAL SOOF-STATE CIRCUITS, VOL.42, NO.8, AUGUST 2007), B is the change curve voltage OF the output voltage OF the LDO along With the load, and C is the transient change OF the load.

In the documents in the background art, when the output voltage of the LDO jumps from 0A to 200mA in 1us of load, the output voltage can be stabilized after 50us, and the undershoot peak value is 96.2mV, when the output voltage jumps from 200mA to 0A in 1us of load, the output voltage is stabilized within 5us, the overshoot peak value is 30.2mV, and the load regulation rate is 0.33 mV/mA.

When the load 1us jumps from 0A to 200mA, the output voltage of the LDO can be stable within 5us, the undershoot peak value is 2.9mV, when the load 1us jumps from 200mA to 0A, the output voltage can be stable within 5us, and the overshoot peak value is 2.7 mV.

Fig. 7 is a transient characteristic diagram of the power supply voltage 1us jumping from 2V to 3.3V under the output load 200 mA. A is the change curve of the output voltage of the LDO along with the input voltage in the documents of the background art, B is the change curve voltage of the output voltage of the LDO along with the input voltage, and C is the transient change of the input voltage.

When the input voltage 1us of the LDO in the document provided by the background technology jumps from 2V to 3.3V, the output voltage is stabilized after 50us, and the maximum peak value is 66.6 mV; when the power supply voltage 1us jumps from 3.3V to 2V, the output voltage is stabilized after 10us, and the maximum peak value is 26.8 mV. The linear adjustment rate was 1.38%.

When the input voltage 1us of the LDO jumps from 2V to 3.3V, the output voltage is stable within 2us, and the maximum peak value is 0.694 mV; when the power supply voltage 1us jumps from 3.3V to 2V, the output voltage is stable within 2us, and the maximum voltage difference is 0.9 mV. The linear regulation rate of the low dropout linear regulator is 0.053%, which is far better than that of the LDO in the background technology, and the linear regulation rate is greatly improved.

Fig. 8 shows the power supply rejection ratios of 1mA, 10mA, 100mA, and 200mA for the output loads, respectively. Wherein A is a power supply rejection ratio curve of 1mA, B is a power supply rejection ratio curve of 10mA, C is a power supply rejection ratio curve of 100mA, and D is a power supply rejection ratio curve of 200 mA.

When the output load is 1mA, the low-frequency PSR is-72.82 dB, the low-frequency PSR is-69.65 dB at 100kHz, the low-frequency PSR is-69.16 dB at 1MHz, and the low-frequency PSR is-89.41 dB at 10 MHz; when the output load is 10mA, the low-frequency PSR is-73.73 dB, the low-frequency PSR is-69.09 dB at 100kHz, the low-frequency PSR is-55.596 dB at 1MHz, and the low-frequency PSR is-69.28 dB at 10 MHz; when the output load is 100mA, the low-frequency PSR is-68.08 dB, the low-frequency PSR is-67.64 dB at 100kHz, the low-frequency PSR is-61.34 dB at 1MHz, and the low-frequency PSR is-57.84 dB at 10 MHz; the low frequency PSR is-59.29 dB at an output load of 200mA, is-59.39 dB at 100kHz, is-68.13 dB at 1MHz and is-56.8 dB at 10 MHz. The PSR curves at different loads were in accordance with theoretical analysis. When the frequency is 10MHz, the minimum power supply rejection ratio is-56.8 dB, and the invention effectively improves the power supply rejection ratio, especially the power supply rejection ratio under high frequency.

It will be appreciated by those of ordinary skill in the art that the examples set forth herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited examples and embodiments. The above examples are only intended to illustrate the technical solutions of the present invention. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the present invention as defined in the claims.

Claims (6)

1. The high PSR low-dropout linear voltage regulator is characterized by further comprising a slew rate enhancement circuit and a compensation capacitor, wherein the positive phase input end of the error amplifier is connected with the reference voltage source, the negative phase input end of the error amplifier is connected with the resistance feedback circuit, the output end of the error amplifier is connected with the input end of the slew rate enhancement circuit, the output end of the slew rate enhancement circuit is connected with the grid electrode of the adjustment tube, the drain electrode of the adjustment tube is the output end and is connected with the resistance feedback circuit, the source electrode of the adjustment tube is connected with the power voltage input end, one end of the compensation capacitor is connected with the negative phase input end of the error amplifier, and the other end of the compensation capacitor is connected with the drain electrode of the adjustment tube;

the slew rate enhancement circuit comprises a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube and a ninth NMOS tube, wherein the fifth PMOS tube and the sixth NMOS tube form a first phase inverter, the seventh PMOS tube and the seventh NMOS tube form a second phase inverter, the input end of the first phase inverter is connected with the output end of the error amplifier, the output end of the first phase inverter is connected with the drain electrode of the sixth PMOS tube and the input end of the second phase inverter, the grid electrode of the sixth PMOS tube is connected with the drain electrode and the input end of the second phase inverter, the source electrode of the sixth PMOS tube is connected with the input end of the power supply voltage, the output end of the second phase inverter is connected with the grid electrode of the eighth NMOS tube, the drain electrode and the grid electrode of the ninth NMOS tube, the grid electrode of the eighth NMOS tube is connected with the grid electrode of the ninth NMOS tube, the source electrode of the eighth NMOS tube is grounded, the grid electrode of the eighth POMS tube is connected, the source electrode of the eighth PMOS tube is connected with the power supply voltage input end, the source electrode of the ninth NMOS tube is grounded, and the drain electrode of the ninth NMOS tube is connected with the drain electrode of the eighth PMOS tube.

2. The integrated slew rate enhancement circuit high PSR low dropout regulator of claim 1, wherein the error amplifier is a-3 dB amplifier with a bandwidth greater than 2 MHz.

3. The high PSR low dropout regulator with an integrated slew rate enhancement circuit of claim 1, wherein the error amplifier comprises a bias voltage input terminal, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, wherein a gate of the first PMOS transistor is connected to a gate of the second PMOS transistor, a gate of the second PMOS transistor is connected to a drain of the second PMOS transistor, a drain of the first PMOS transistor is connected to a gate of the fourth NMOS transistor, a gate of the fourth NMOS transistor is connected to a drain of the fourth NMOS transistor, a gate of the second PMOS transistor is connected to a drain of the first NMOS transistor, a gate of the third PMOS transistor is connected to a drain of the third NMOS transistor and to a drain of the second NMOS transistor, a gate of the fourth PMOS transistor is connected to a gate of the third PMOS transistor, a drain of the fourth PMOS transistor is connected to a gate of the fifth NMOS transistor, and a drain of the fifth NMOS transistor is connected to a drain of the fifth NMOS transistor, the grid electrode of the first NMOS tube is the inverting input end of the error amplifier, the source electrode of the first NMOS tube is connected with the drain electrode of the third NMOS tube, the grid electrode of the second NMOS tube is the positive phase input end of the error amplifier, the source electrode of the second NMOS tube is connected with the drain electrode of the third NMOS tube, the source electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all connected with the power supply voltage input end, the source electrodes of the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube are all connected with the ground, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube, and the grid electrode of the third NMOS tube is connected with the bias voltage input end to generate tail current.

4. The integrated slew rate enhancement circuit high PSR low dropout regulator according to claim 1, wherein the resistor feedback circuit comprises a first resistor and a second resistor, one end of the first resistor is connected to one end of the second resistor and to the inverting input terminal of the error amplifier, the other end of the first resistor is connected to the drain of the tuning transistor, and the other end of the second resistor is connected to ground.

5. The integrated slew rate enhancement circuit high PSR low dropout regulator of claim 1 wherein the tuning transistor is a PMOS transistor.

6. The integrated slew rate enhancement circuit high PSR low dropout regulator according to claim 1, 2, 3, 4, or 5, further comprising an off-chip capacitor, one end of the off-chip capacitor being connected to the drain of the tuning transistor and the other end being connected to ground, wherein the off-chip capacitor has a parasitic resistance of less than 10m Ω and a capacitance of greater than 2.2 uF.