CN103262405B - The control system that can reconstruct in operation and for its method - Google Patents
The control system that can reconstruct in operation and for its method Download PDFInfo
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- CN103262405B CN103262405B CN201080069761.2A CN201080069761A CN103262405B CN 103262405 B CN103262405 B CN 103262405B CN 201080069761 A CN201080069761 A CN 201080069761A CN 103262405 B CN103262405 B CN 103262405B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/18—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
- G05B19/404—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by control arrangements for compensation, e.g. for backlash, overshoot, tool offset, tool wear, temperature, machine construction errors, load, inertia
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/34—Director, elements to supervisory
- G05B2219/34024—Fpga fieldprogrammable gate arrays
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Abstract
The present invention discloses a kind of control system that can be reconstructed in operation and the method for it.Control system comprises master controller according to an embodiment of the invention, and its order according to user generates the bit stream comprising reconfiguration information.First comprises from controller: the first dynamic restructuring module, and it is the field programmable gate array (FPGA) that is reconstructed according to described reconfiguration information and calculates controlling value; Static reconfiguration module, it is the FPGA according to described controlling value control objectives device operation; And control unit, its one or more according in the described reconfiguration information described first dynamic restructuring module of reconstruct and described static reconfiguration module.
Description
Technical field
The present invention relates to a kind of control system and the method for it, more specifically, relate to the control system that can reconstruct in operation and the method for it.
Background technology
Robot and similar device use servomotor to operate.By controlling the operation of servomotor and control device.
In general, master controller can be used and control to carry out operation from controller.Control signal is sent to each from controller by master controller, and eachly corresponds to control signal and control servomotor from controller.Master controller can be connected from controller with multiple, and eachly controls corresponding servomotor from controller.
Usually have feature board bag from controller, it is suitable for the operation of servomotor.But, be can only control corresponding servomotor from controller from the shortcoming of controller.In other words, when changing servomotor by another kind of model, also need to change from controller.
Summary of the invention
Technical problem
The invention provides a kind of control system and the method for it, this control system can by reconstruct FPGA(field programmable gate array in the operation of modifier control method) structure and keep the control of this device simultaneously and be reconstructed.
Technical scheme
One aspect of the present invention proposes a kind of control system that can be reconstructed in operation.Control system according to one embodiment of the invention comprises master controller, and its order according to user generates the bit stream comprising reconfiguration information.First comprises from controller: the first dynamic restructuring module, and it is the field programmable gate array (FPGA) that is reconstructed according to reconfiguration information and calculates controlling value; Static reconfiguration module, it is the FPGA according to described controlling value control objectives device operation; And control unit, it is one or more that it reconstructs in the first dynamic restructuring module and static reconfiguration module according to reconfiguration information.
Control unit can reconstruct the FPGA structure of dynamic restructuring module independent of the operation of static reconfiguration module.
Also the second dynamic restructuring module can be comprised from controller, it is for the FPGA that is reconstructed according to reconfiguration information and calculate controlling value, and when the capacity of reconfiguration information is greater than predetermined value, control unit can control the second dynamic restructuring module according to reconfiguration information to be made it be reconstructed and keeps the operation of the first dynamic restructuring module until complete reconstruct second dynamic restructuring module.
When completing reconstruct second dynamic restructuring module, control unit can stop the operation of the first dynamic restructuring module.
Master controller can comprise: reconstruct library storage unit, the function information of annexation between its door storing instruction first dynamic restructuring module or between the door of static reconfiguration module; Reconfiguration information combining unit, it is according to order abstraction function information and generate reconfiguration information by combining the function information that extracts; And entry administrative unit, it generates the bit stream comprising reconfiguration information.
Control system also can comprise from communication unit, its by bit stream to the first from controller, if and entry administrative unit generates reconstitution time information according to order, the i.e. time of transmission bit stream, from communication unit then each predetermined period or according to reconstitution time information when generate bit stream time by bit stream to the first from controller.
Control system also can comprise second from controller, and it is the controller from controller with first with identical configuration, and master controller generates bit stream, and it comprises with first from controller and the second reconfiguration information corresponding from each controller.
Master controller, first can be connected by the twin nuclei of network from controller from controller with second.
When changing destination apparatus, static reconfiguration module is the FPGA be reconstructed according to reconfiguration information.
Another aspect of the present invention proposes a kind of method operated with control objectives device for Reconfigurable Control system.Method according to one embodiment of the invention can comprise: the order according to user generates the bit stream comprising reconfiguration information; Reconstruct primary scene programmable gate array (FPGA), it is reconstructed according to reconfiguration information and calculates controlling value; Use the FPGA calculate control values of reconstruct; And described controlling value is transferred to the 2nd FPGA, the operation of its control objectives device.
The reconstruct of the one FPGA is independent of the operation of the 2nd FPGA.
The method also comprises reconstruct the 3rd FPGA, and it is reconstructed according to reconfiguration information when being greater than predetermined value when the capacity of reconfiguration information and calculating controlling value, and can keep the operation of a FPGA until complete reconstruct the 3rd FPGA.
The method also comprises when completing reconstruct the 3rd FPGA, stops the operation of a FPGA.
The generation of bit stream can comprise: according to order from the memory space abstraction function information of control system, the function information of annexation between the door that control system stores instruction the one FPGA or between the door of the 2nd FPGA; Reconfiguration information is generated by combining the function information that extracts; And generate the bit stream comprising reconfiguration information.
Accompanying drawing explanation
Fig. 1 shows control system.
Fig. 2 is the diagram of the bit stream example generated by the master controller of control system.
Fig. 3 is the calcspar that master controller concept structure is described.
Fig. 4 illustrates that master controller is the diagram of the example how generating reconfiguration information.
Fig. 5 is the calcspar of brief description composition first from the functional unit of controller.
Fig. 6 illustrates that control system is the flow chart how controlling servomotor operation.
Embodiment
Fig. 1 shows the control system that can be reconstructed in operation according to an embodiment of the invention.
With reference to Fig. 1, the control system according to one embodiment of the invention comprises master controller 101, first from controller 102 and second from controller 103.Although there are two from controller in Fig. 1, according to the control system of the embodiment of the present invention can have according to using specific environment of the present invention varying number from controller.In addition, at least one transducer being used for the acceleration, heat etc. detecting each servomotor and described each servomotor can be connected to each from controller.
Master controller 101 from input unit, as personal computer (not shown) receives operational order.Here, be operator scheme according to a kind of servomotor from the order received by input unit and indicate the signal of operational order.Master controller 101 can at least one reconfiguration information of received commands match, and the instruction of this reconfiguration information is arranged at each from the FPGA(field programmable gate array controller) reconstruct; And store this reconfiguration information.Such as, master controller 101 is by comprising the order received from input unit and the reconfiguration information of mating for this order and generating bit stream.
Such as, if by have shown in Fig. 1 two from controller 102,103 time, master controller 101 is by comprising first reconfiguration information corresponding from controller 102 with first and generating bit stream with second from least one corresponding the second reconfiguration information of controller 103.
Hereinafter, the structure of bit stream is described in detail with reference to Fig. 2.
Fig. 2 is the diagram of the structure example of the bit stream generated by the master controller of control system according to an embodiment of the invention.
Master controller 101 generates bit stream, and it comprises being used to indicate and is arranged at first from the reconfiguration information of controller 102 and second FPGA reconstruct from controller 103, to control to be connected to first respectively from controller 102 and second from the servomotor of controller 103.
Here, master controller 101 can allow reconfiguration information to be placed in bit stream from after identifying information, should be identify each information from controller from identifying information, thus eachly can extract relevant reconfiguration information easily from controller.
Such as in fig. 2, first from identifying information 210 and the first reconfiguration information 220 be with first from controller 102 corresponding from identifying information and reconfiguration information, and second from identifying information 230 and the second reconfiguration information 240 be with second from controller 103 corresponding from identifying information and reconfiguration information.First search package can be contained in first in the middle of bit stream from identifying information 210 from controller 102, identify first from identifying information 210 and the next one from the data between identifying information as the first reconfiguration information 220 and from this bitstream extraction first reconfiguration information 220.
Refer again to Fig. 1, master controller 101 periodically can produce multiple bit stream to respond the order received from input unit.
Such as, if the order instruction servomotor received from input unit repeats to run and stop step in interval on schedule, master controller 101 can generate a bit stream, and it comprises the reconfiguration information for carrying out servomotor operation; And a bit stream, it comprises the reconfiguration information for interval stopping servomotor operation on schedule.Hereinafter, the structure of master controller 101 is described in detail with reference to Fig. 3.
Fig. 3 is the calcspar that master controller concept structure is described.With reference to Fig. 3, master controller 101 comprises main-machine communication unit 310, reconfiguration information combining unit 320, reconstruct library storage unit 330, entry administrative unit 340 and from communication unit 350.
Main-machine communication unit 310 passes through the order of network reception user from input unit.Main-machine communication unit 310 by received command transfer to reconfiguration information combining unit 320.
Reconfiguration information combining unit 320 extracts one or more function information be stored in reconstruct library storage unit according to the order that receives from main-machine communication unit 310, and generates reconfiguration information by combining the function information that extracts.
Here, the function information information that can comprise about the FPGA from controller between door annexation and by various forms, showing as bit string according to an embodiment of the invention.In addition, FPGA can perform special function when being reconstructed according to this function information according to an embodiment of the invention.Below, the step generating reconfiguration information is described in detail with reference to Fig. 4.Here, generated reconfiguration information is transferred to entry administrative unit 340 by reconfiguration information combining unit 320.
Entry administrative unit 340 generates reconstitution time information and reconfiguration mode information based on the reconfiguration information received from reconfiguration information combining unit 320.
Here, reconstitution time information indicates and to be sent immediately by the bit stream comprising reconfiguration information or regularly to send bit stream from communication unit 350.
Whether reconfiguration mode information can indicate reception each of bit stream will reconstruct FPGA from controller.
Reconfiguration mode information is inserted reconfiguration information by entry administrative unit 340, generates and comprises each reconfiguration information and the bit stream from identifying information, and transferred to from communication unit 350 together with reconstitution time information by bit stream.
From communication unit 350 according to reconstitution time information by bit stream to the first from controller 102 or the second from controller 103.Specifically, will transmission bit stream immediately if reconstitution time information indicates, from communication unit 350 can immediately by bit stream to from controller, will by transmission period transmission bit stream if reconstitution time information indicates, from communication unit 350 can by each transmission period of specifying by bit stream to from communication unit 350.
Refer again to Fig. 1, master controller 101 by generated bit stream to the first from controller 102.Here, master controller 101 can be connected from controller 103 from controller 102 with second with first by twin nuclei.Specifically, if second not to receive from controller 103 and transfers to first from the bit stream of controller 102 through master controller 101, twin nuclei then can make master controller 101 again by generated bit stream to the second from controller 103.Therefore, according to one embodiment of present invention, even if when master controller 101, first disconnects from controller 102 and second from any network between controller 103, also can normal running be carried out.
First extracts reconfiguration information from controller 102 from the bit stream that master controller 101 receives, and also uses the FPGA of reconstruct to control servomotor according to described reconfiguration information reconstruct FPGA.Hereinafter, first is described in detail from the structure of controller 102 with reference to Fig. 5.
Fig. 4 illustrates that master controller is the diagram of the example how generating reconfiguration information.
With reference to Fig. 4, the reconfiguration information combining unit 320 of master controller 101 receives order from input unit.Reconfiguration information combining unit 320 extracts required function information according to received order from reconstruct memory cell 330.Reconstruct library storage unit 330 can store one or more function information, and the function information list needed for reconstruct FPGA can prestore according to each order that can receive from user by reconfiguration information combining unit 320.Correspondingly, once receive order, reconfiguration information combining unit 320 is searched for and is ordered the function information list matched, and extracts the function information be included in searched list, and generate reconfiguration information by binding function information from reconstruct library storage unit 330.
Such as, reconstruct library storage unit 330 can store the function information relevant with the algorithm treated by performing from controller, indicate the function information receiving the function of data from the transducer detecting servomotor, and instruction controls the function information of the function of real electrical machinery operation.Reconfiguration information combining unit 320 receives order 1 from input unit and searches for the function information list matched with order 1.Reconfiguration information combining unit 320 confirms that the function information be included in function information list is algorithm 1, and transducer input 1 and motor drive 2, and extracts each function information from reconstruct library storage unit 330.Reconfiguration information combining unit 320 generates the reconfiguration information 420 corresponding with ordering 1 by combining the function information that extracts.Reconfiguration information 420 can be transferred to entry administrative unit 340 by reconfiguration information combining unit 320.
Although master controller 101 is described as by making reconfiguration information combining unit 320 extract and binding function information and generate reconfiguration information, it also may be that reconfiguration information combining unit 320 has the reconfiguration information corresponding to each order that wherein prestores and when receiving particular command, transfers to entry administrative unit 340 by corresponding to the reconfiguration information of particular command.Correspondingly, master controller 101 also can not be extracted reconfiguration information by the particular step of binding function information and described reconfiguration information is transferred to entry administrative unit 340.
Fig. 5 is the calcspar of brief description composition first from the functional unit of controller.With reference to Fig. 5, first comprises control unit 510 and reconfiguration unit 520 from controller 102.
Control unit 510 receives bit stream from master controller 101, and from bitstream extraction reconfiguration information.Control unit 510 checks whether the reconfiguration mode information be included in reconfiguration information indicates the reconstruct of FPGA.If reconfiguration mode information does not indicate the reconstruct of FPGA, control unit 510 can not carry out the reconstruction step performing FPGA.If reconfiguration mode information indicates the reconstruct of FPGA, control unit 510 can be reconstructed according to the gate array architecture of reconfiguration information to reconfiguration unit 520.Such as, if reconfiguration information shows that the data in FPGA structure receive from the transducer detecting servomotor, calculate received data according to pre-defined algorithm and control servomotor according to result of calculation, control unit 510 control reconfiguration unit 520 are according to reconfiguration information reconstruct FPGA.
Here, although above-mentioned control unit 510 is determined to be reconstructed according to reconfiguration mode information, to the relevant reconfiguration information corresponding from controller, control unit 510 can determine that FPGA is the need of being reconstructed according to whether comprising in bit stream according to another embodiment of the present invention.
Reconfiguration unit 520 comprises static reconfiguration module 523, the first dynamic restructuring module 526 and the second dynamic restructuring module 529 that are made up of FPGA.The static reconfiguration module 523 controlling servomotor operation can control servomotor and carry out rotation acceleration, reverse rotation acceleration, stopping etc. according to the signal received from dynamic reconstructed module (i.e. the first dynamic restructuring module 526 and the second dynamic restructuring module 529).Because static reconfiguration module 523 directly controls the operation of servomotor, when first from the operation of controller 102 positive control servomotor, be not reconstructed.But when using another kind of device to replace servomotor, static reconfiguration module 523 can be reconstructed.Particularly, when user provides order to control the another kind of device for replacing by input unit, master controller 101 may correspond in this order by the bit stream of reconfiguration information that comprises for reconstructing static reconfiguration unit 523 extremely, and such as first from the control unit 510 of controller 102.Then, control unit 510 according to the gate array architecture of the reconfiguration information reconstruct static reconfiguration unit 523 comprised in the bitstream, thus can control the another kind of device for replacing.
In addition, the first dynamic restructuring module 526 makes FPGA be reconstructed according to the control of control unit 510, but independent of the operation of static reconfiguration module 523.That is, whether no matter static reconfiguration module 523 is current controls servomotor or is reconstructed, and all can be reconstructed the first dynamic restructuring module 526.
Such as, dynamic restructuring module 526 receives the rotary speed of servomotor from the transducer detecting servomotor rotary speed, and can work as rotary speed when exceeding command speed, calculates according to the pre-defined algorithm for servomotor rotary speed.Controlling value as result of calculation can be transferred to static reconfiguration module 523 by dynamic restructuring module 523.In addition, static reconfiguration module 523 can adjust rotary speed to value according to controlling value.
Reconstruct in the example of the first dynamic restructuring module 526 at another, assuming that the control overflow of servomotor is received data from first sensor, the second transducer and the 3rd transducer successively and calculated by the first algorithm, and generated the bit stream being used for this control by master controller 101.In this case, control unit 510 can receive the first bit stream from master controller 101.Here, the first bit stream comprises instruction FPGA structure for receiving data from first sensor and being carried out the reconfiguration information that calculates by the first predetermined algorithm.Then, control unit 510 controls the first dynamic restructuring module 526 and is reconstructed FPGA structure according to reconfiguration information.Here, static reconfiguration module 523 can continue to control servomotor.After completing reconstruct, the first dynamic restructuring module 526 receives data export controlling value according to FPGA structure from first sensor, and this controlling value is the value calculated by the first algorithm.Controlling value is sent to static reconfiguration module 523 by the first dynamic restructuring module 526.Static reconfiguration module 523 continues according to controlling value to control servomotor.
Afterwards, control unit 510 can receive the second bit stream from master controller 101.Here, the second bit stream comprises instruction FPGA structure for receiving data from the second transducer and being carried out the reconfiguration information that calculates by the first algorithm.Then, after the above step, the first dynamic restructuring module 526 is reconstructed the FPGA structure allowing to receive data from the second transducer.In addition, static reconfiguration module 523 continues to control servomotor according to controlling value.
Afterwards, control unit 510 can receive the 3rd bit stream from master controller 101.Here, the 3rd bit stream comprises instruction FPGA structure for receiving data from the 3rd transducer and being carried out the reconfiguration information that calculates by the first algorithm.Then, after the above step, the first dynamic restructuring module 526 is reconstructed the FPGA structure allowing to receive data from the 3rd transducer.In addition, static reconfiguration module 523 continues to control servomotor according to controlling value.
Correspondingly, data can be received from first, second, and third transducer successively.
If receive data from each transducer successively, routine operation controller then needs the module for each transducer, thus receives data from each respective sensor, and therefore it inevitably has enough large circuit.But first keeps using a dynamic restructuring module 526 to receive data from transducer successively during the control of servomotor from controller 510 in use static reconfiguration module 523, thus controls servomotor.Correspondingly, the size of this control system can be less than routine operation controller relatively.
Here, the function of static reconfiguration module 523 and the first dynamic restructuring module 526 is not limited in content described herein.In other words, the function of static reconfiguration module 523 and the first dynamic restructuring module 526 reconfiguration information of bit stream that can receive according to control unit 510 and changing.
Second dynamic restructuring module 529 has the configuration identical with the first dynamic restructuring module 526, and is reconstructed by the reconstruction step identical with the first dynamic restructuring module 526.
In another embodiment of the present invention, control unit 510 can be reconstructed according to the FPGA structure of the capacity of the reconfiguration information from bitstream extraction to the first dynamic restructuring module 526 or the second dynamic restructuring module 529.
Such as, run if suppose that the first dynamic restructuring module 526 is current, control unit 510 is reconstructed according to the FPGA of reconfiguration information to current off-duty second dynamic restructuring module 529 when the capacity of reconfiguration information is greater than predetermined volumes.After reconstruct completes, the completed reconstruct settling signal of notice reconstruct is sent to control unit 510 by the second dynamic restructuring module 529.Once receive reconstruct settling signal, the operation of request shut-down operation stops request being sent to current the first dynamic restructuring module 526 run by control unit 510.First dynamic restructuring module 526 stops request shut-down operation according to operation.Here, wherein according to reconfiguration information, the second dynamic restructuring module 529 that FPGA structure is reconstructed is calculated and result of calculation is sent to static reconfiguration module 523.Then, when receiving result of calculation from the second dynamic restructuring module 529, static reconfiguration module 523 can control servomotor.
Although whether above-mentioned control unit 510 is greater than predetermined value for the capacity of the reconfiguration information determining the bit stream received from master controller 101, but can also be in another embodiment, that the entry administrative unit 340 of master controller 101 determines whether the capacity of reconfiguration information is greater than predetermined value and determines that corresponding information is inserted in the title of reconfiguration information by with this.Here, control unit 510 can check information in the title of reconfiguration information and carry out the reconstruction step of the first dynamic restructuring module 526 or the second dynamic restructuring module 529.
Fig. 6 illustrates that control system is the flow chart how controlling servomotor operation.
With reference to Fig. 6, in step 610, master controller 101 receives order from input unit.
In step 620, master controller 101 is according to the bit stream of order generation for controlling servomotor received in step 610.Here, master controller 101 generates and comprises the bit stream of instruction from the reconfiguration information of controller FPGA structure, thus controls servomotor according to order.Generated bit stream is sent to first from controller 102 by master controller 101.
In act 630, first from controller 102 from received bitstream extraction reconfiguration information.Here, after extraction reconfiguration information, bit stream can be sent to second from controller 103 from controller 102 by first.After step 630 can by with first from the mode that controller 102 is identical operate receive bit stream second from controller 103.
In step 640, first from controller 102 according to the structure of reconfiguration information to reconfiguration unit, namely FPGA module is reconstructed.Here, if the first dynamic restructuring module 526 of the current positive control servomotor in multiple dynamic restructuring module is reconstructed according to reconfiguration information, so when first needs to stop controlling servomotor from controller 102, first can reconstruct the second dynamic restructuring module 529 from controller 102.Once the reconstruct of the second dynamic restructuring module 529 completes, first can by using the second dynamic restructuring module 529 and static reconfiguration module 523 stop the operation of the first dynamic restructuring module 526 and control servomotor from controller 102.In addition, first static reconfiguration module 523, first dynamic restructuring module 526 and the second dynamic restructuring module 529 can be reconstructed independently according to reconfiguration information from controller 102.Namely, when reconfiguration information only shows the structure of the first dynamic restructuring module 526 or the second dynamic restructuring module 529, when static reconfiguration module 523 controls servomotor, first can reconstruct the first dynamic restructuring module 526 or the second dynamic restructuring module 529 from controller 102.
In step 650, the first operation being controlled servomotor from controller 102 by the reconfiguration unit being used in step 640 reconstruct.
Although the control system described controls servomotor, be understood that and be applicable to the reconfiguration information of other devices and other devices of controlling except servomotor by configuration.
So far, according to specific embodiment, invention has been described, but except described embodiment, also has other embodiments many in the claims in the present invention.It should be understood that those of ordinary skill in the art can show the present invention with the form changed under the prerequisite not departing from essential characteristic of the present invention.Correspondingly, the disclosed embodiments should be understood as that illustrative and nonrestrictive.Scope of the present invention should explanation by claims but not above and limiting, and any and all changes in equivalent scope all should be understood as that and comprise within the scope of the invention.
industrial applicability
Control system and the method for it control each device neatly by the input reconstruct gate array architecture according to user according to an embodiment of the invention.
Control system and the method for it also use the gate array of reconstruct to control this device by reconstruct gate array architecture and make the minimized in size of control device according to an embodiment of the invention.
Claims (8)
1. the control system that can be reconstructed in operation, described control system comprises:
Master controller, it is configured to generate according to the order of user the bit stream comprising reconfiguration information; And
First from controller,
Wherein, described first comprises from controller:
First dynamic restructuring module and the second dynamic restructuring module, both are the FPGA that is reconstructed according to described reconfiguration information and calculate controlling value;
Static reconfiguration module, it is the FPGA according to the described controlling value control objectives device operation calculated; And
Control unit, its one or more according in the reconstruct of described reconfiguration information described first dynamic restructuring module, the second dynamic restructuring module and described static reconfiguration module,
Wherein, when the capacity of described reconfiguration information is greater than predetermined value, described control unit controls described second dynamic restructuring module according to described reconfiguration information makes it be reconstructed, and keeps the operation of described first dynamic restructuring module until complete the described second dynamic restructuring module of reconstruct.
2. control system according to claim 1, wherein said control unit can reconstruct the FPGA structure of described first dynamic restructuring module and the second dynamic restructuring module independent of the operation of described static reconfiguration module.
3. control system according to claim 1, wherein, when completing the described second dynamic restructuring module of reconstruct, described control unit stops the operation of described first dynamic restructuring module.
4. the control system that can be reconstructed in operation, described control system comprises:
Master controller, it is configured to generate according to the order of user the bit stream comprising reconfiguration information; And
First from controller,
Wherein, described first comprises from controller:
First dynamic restructuring module, it is the FPGA that is reconstructed according to described reconfiguration information and calculates controlling value;
Static reconfiguration module, it is the FPGA according to the described controlling value control objectives device operation calculated; And
Control unit, its one or more according in the described reconfiguration information described first dynamic restructuring module of reconstruct and described static reconfiguration module, wherein said master controller comprises:
Reconstruct library storage unit, its store indicate described first dynamic restructuring module door between or described static reconfiguration module door between the function information of annexation;
Reconfiguration information combining unit, it extracts according to described order the described function information that stores and generates described reconfiguration information by combining the function information that extracts; And
Entry administrative unit, it generates the bit stream comprising described reconfiguration information.
5. control system according to claim 4, also comprises from communication unit, its by described bit stream to described first from controller,
Wherein, if described entry administrative unit generates reconstitution time information, namely transmit the time of described bit stream, described from communication unit then each predetermined period or when generating described bit stream according to described reconstitution time information by described bit stream to described first from controller.
6. control system according to claim 1, also comprises second from controller, and it is the controller from controller with described first with identical configuration,
Wherein said master controller generates described bit stream, and it comprises with described first from controller and the described second reconfiguration information corresponding from each controller.
7. control system according to claim 6, wherein said master controller, described first is connected from the twin nuclei of controller by network from controller with described second.
8. control system according to claim 1, wherein when changing described destination apparatus, described static reconfiguration module is the FPGA be reconstructed according to described reconfiguration information.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2010-0103627 | 2010-10-22 | ||
| KR1020100103627A KR101259133B1 (en) | 2009-11-11 | 2010-10-22 | Reconfigurable control system during operation and method there of |
| PCT/KR2010/007795 WO2012053687A1 (en) | 2010-10-22 | 2010-11-05 | Control system that is reconfigurable during operation, and method therefor |
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| CN103262405A CN103262405A (en) | 2013-08-21 |
| CN103262405B true CN103262405B (en) | 2016-03-23 |
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| CN (1) | CN103262405B (en) |
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| JP3555329B2 (en) * | 1996-04-26 | 2004-08-18 | ソニー株式会社 | Motor driver device |
| JP3486774B2 (en) * | 2000-03-13 | 2004-01-13 | 住友重機械工業株式会社 | Multi-axis control system |
| JP3832557B2 (en) * | 2000-05-02 | 2006-10-11 | 富士ゼロックス株式会社 | Circuit reconfiguration method and information processing system for programmable logic circuit |
| JP2001322078A (en) * | 2000-05-15 | 2001-11-20 | Sanyo Electric Co Ltd | Robot control device |
| JP2005275938A (en) * | 2004-03-25 | 2005-10-06 | Toshiba Corp | Controller system and controller for mechatronics apparatus |
| JP2007014092A (en) * | 2005-06-29 | 2007-01-18 | Digital Magic Kk | Motor control system |
| KR200409311Y1 (en) * | 2005-11-18 | 2006-02-24 | 엘지노텔 주식회사 | Apparatus of Downloading a FPGA in the Communication System |
| KR100762366B1 (en) * | 2005-12-30 | 2007-10-01 | 삼성중공업 주식회사 | System for controlling a robot by using a Field Programmable Gate Array device |
| KR100827787B1 (en) * | 2007-07-06 | 2008-05-07 | 한국전력공사 | Remote control system for robot that cleans and inspects insulators supporting power transmission line |
| KR100945884B1 (en) * | 2007-11-14 | 2010-03-05 | 삼성중공업 주식회사 | Embedded robot control system |
| JP5098936B2 (en) * | 2008-04-15 | 2012-12-12 | 株式会社安川電機 | Servo control device |
| JP5007838B2 (en) * | 2009-03-05 | 2012-08-22 | 富士ゼロックス株式会社 | Information processing apparatus and information processing program |
| JP5355152B2 (en) * | 2009-03-10 | 2013-11-27 | 三菱電機株式会社 | Dynamic reconfiguration device |
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| WO2012053687A1 (en) | 2012-04-26 |
| JP2014500644A (en) | 2014-01-09 |
| JP5646764B2 (en) | 2014-12-24 |
| CN103262405A (en) | 2013-08-21 |
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