CN102779194A - Code stream generation method and device of FPGA structure based on SOI - Google Patents
Code stream generation method and device of FPGA structure based on SOI Download PDFInfo
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Abstract
The invention discloses a code stream generation method of an FPGA structure based on SOI, which is characterized by comprising the following steps: reading the structure information of the FPGA chip and storing the structure information in a first data structure; reading a netlist file defined by a user, and respectively storing the netlist file in a second data structure and a third data structure according to the netlist file type; reading layout and wiring result information, and respectively storing the layout and wiring result information in a fourth data structure and a fifth data structure; judging whether the data in each data structure are matched, and if so, generating a code stream file; if not, the program is terminated and no code stream file is generated. Compared with the prior art, the code stream generation method can not only generate a code stream file of a full chip, but also realize any user-defined code stream structure.
Description
Technical field
The invention belongs to microelectronics technology, particularly a kind of code stream of the FPGA structure based on SOI generates method and apparatus.
Background technology
FPGA uses a kind of very widely programming device in the market; The appearance of FPGA makes special IC (Application Specific Integrated Circuits; Abbreviation ASIC) the listing cycle of product shortens greatly, and has saved a large amount of cost of development.
In addition, different FPGA inside chip exists than big-difference, and present FPGA code stream Core Generator all is based on certain fixedly FPGA structure; For example, commercial Xilinx is outside the FPGA code stream instrument of Altera and Lattice company; Also has DAGGER, PARBIT etc.But because chip there are differences, above-mentioned code stream Core Generator all can't be applied to the fpga chip structure based on SOI (Silicon On Insulator).
Summary of the invention
The present invention is in order to solve the problem that exists in the prior art, and the code stream that proposes a kind of FPGA structure based on SOI especially generates method and apparatus, generates based on the code stream of the FPGA of SOI in order to realizing.
Detailed technology scheme of the present invention is following:
A kind of code stream generation method of the FPGA structure based on SOI comprises following steps:
Read the fpga chip structural information, be stored in first data structure;
Read user-defined net meter file,, the information of said net meter file is stored in respectively in second and third data structure according to the classification of said net meter file;
Read layout, wiring object information, be stored in respectively in the 4th and the 5th data structure;
Judge whether the data in each data structure mate, like coupling, then generated code stream file; As do not match, then program stops, and does not produce ASCII stream file ASCII.
Wherein, said chip structure information comprises logical block information, cell distribution information and the interconnection resource information of chip.
Wherein, the classification of said net meter file is the connected mode of circuit logic unit information and said circuit logic unit.
Wherein, said as coupling then also comprises CRC check after the generated code stream file, judges whether ASCII stream file ASCII is correct, and the judged result mistake does not then produce ASCII stream file ASCII.
Wherein, saidly judge that whether the data in each data structure mate, and specifically comprise:
Judge that whether said net meter file is all by layout, wiring;
Judge whether the position and the said chip structure information of said layout, wiring object information coincide.
Wherein, said method realizes based on the C language.
A kind of code stream generating apparatus of the FPGA structure based on SOI comprises:
Read module is used for reading respectively FPGA structural information, the net meter file that is used to define and layout, wiring object information;
First memory is used to store the FPGA structural information;
Second memory and the 3rd storer are used for respectively the classification canned data according to said net meter file;
The 4th storer and the 5th storer are used for storage layout, wiring information respectively;
Judge module is used for judging whether coupling according to the data of each storer, like coupling, then generated code stream file; As do not match, then program stops, and does not produce ASCII stream file ASCII.
Wherein, said judge module comprises that first judges the submodule and the second judgement submodule;
Said first judges submodule, is used to judge that whether said net meter file is all by layout, wiring;
Whether said second judges submodule, judges the position and the structure of said layout, wiring object information, coincide with said chip structure information.
Can find out that from technique scheme with respect to prior art, code stream generation method of the present invention not only can produce the ASCII stream file ASCII of a full chip, and can realize the structure of Any user definition.
Description of drawings
Fig. 1 is the code stream product process figure of the embodiment of the invention.
Fig. 2 is the apparatus structure synoptic diagram of the embodiment of the invention.
Embodiment
For making the object of the invention, concrete scheme and advantage more clear, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.
With reference to Fig. 1, a kind of code stream generation method of the FPGA structure based on SOI comprises following steps:
Read the fpga chip structural information, be stored in first data structure; Wherein, said chip structure information comprises logical block information, cell distribution information and the interconnection resource information of chip.
Read user-defined net meter file, according to the classification of said net meter file, respectively with the information stores of said net meter file in second and third data structure; Wherein, said net meter file classification is the connected mode of circuit logic unit information and said circuit logic unit, and the connected mode that is about to said circuit logic unit information and said circuit logic unit is stored in respectively in second and third data structure;
Read layout, wiring object information, be stored in respectively in the 4th and the 5th data structure;
Judge whether the data in each data structure mate, like coupling, then generated code stream file; As do not match, then program stops, and does not produce ASCII stream file ASCII.
Above-mentionedly judge whether the data in each data structure mate, specifically, contrast logical block and connected mode and placement-and-routing's object information of said net meter file, judge whether all by layout, wiring; Contrast placement-and-routing's object information and said chip structure information judge whether position and the structure in placement-and-routing's object information all is the interior of chip.
Wherein, said method is based on the realization of C language.
Preferably, said as coupling then also comprises CRC check after the generated code stream file, judges whether ASCII stream file ASCII is correct, and the judged result mistake does not then produce ASCII stream file ASCII.
With reference to Fig. 2, a kind of code stream generating apparatus of the FPGA structure based on SOI, it comprises:
Read module is used for reading respectively FPGA structural information, the net meter file that is used to define and layout, wiring object information;
First memory is used to store the FPGA structural information;
Second memory and the 3rd storer are used for respectively the classification canned data according to said net meter file;
The 4th storer and the 5th storer are used for storage layout, wiring information respectively;
Judge module is used for judging whether coupling according to the data of each storer, like coupling, then generated code stream file; As do not match, then program stops, and does not produce ASCII stream file ASCII.
Preferably, said judge module comprises that first judges the submodule and the second judgement submodule;
Said first judges submodule, is used to judge that whether said net meter file is all by layout, wiring;
Whether said second judges submodule, judges the position and the structure of said layout, wiring object information, coincide with said chip structure information.
Code stream of the present invention generates method and apparatus not only can produce the ASCII stream file ASCII of a full chip, and can realize the structure of Any user definition.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All any modifications of within spirit of the present invention and principle, being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. code stream generation method based on the FPGA structure of SOI is characterized in that comprising following steps:
Read the fpga chip structural information, be stored in first data structure;
Read user-defined net meter file,, the information of said net meter file is stored in respectively in second and third data structure according to the classification of said net meter file;
Read layout, wiring object information, be stored in respectively in the 4th and the 5th data structure;
Judge whether the data in each data structure mate, like coupling, then generated code stream file; As do not match, then program stops, and does not produce ASCII stream file ASCII.
2. code stream generation method according to claim 1 is characterized in that, said chip structure information comprises logical block information, cell distribution information and the interconnection resource information of chip.
3. code stream generation method according to claim 1 is characterized in that, the classification of said net meter file is the connected mode of circuit logic unit information and said circuit logic unit.
4. code stream generation method according to claim 1 is characterized in that, said as coupling then also comprises CRC check after the generated code stream file, judges whether ASCII stream file ASCII is correct, and the judged result mistake does not then produce ASCII stream file ASCII.
5. according to the arbitrary described code stream generation method of claim 1 to 4, it is characterized in that, saidly judge that whether the data in each data structure mate, and specifically comprise:
Judge that whether said net meter file is all by layout, wiring;
Judge whether the position and the said chip structure information of said layout, wiring object information coincide.
6. according to the arbitrary described code stream generation method of claim 1 to 4, it is characterized in that said method realizes based on the C language.
7. code stream generating apparatus based on the FPGA structure of SOI is characterized in that comprising:
Read module is used for reading respectively FPGA structural information, the net meter file that is used to define and layout, wiring object information;
First memory is used to store the FPGA structural information;
Second memory and the 3rd storer are used for respectively the classification canned data according to said net meter file;
The 4th storer and the 5th storer are used for storage layout, wiring information respectively;
Judge module is used for judging whether coupling according to the data of each storer, like coupling, then generated code stream file; As do not match, then program stops, and does not produce ASCII stream file ASCII.
8. code stream generating apparatus according to claim 7 is characterized in that, said judge module comprises that first judges the submodule and the second judgement submodule;
Said first judges submodule, is used to judge that whether said net meter file is all by layout, wiring;
Whether said second judges submodule, judges the position and the structure of said layout, wiring object information, coincide with said chip structure information.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103164228A (en) * | 2013-03-29 | 2013-06-19 | 北京经纬恒润科技有限公司 | Method and device for generating field-programmable gate array (FPGA) procedure |
| CN106202121A (en) * | 2015-05-07 | 2016-12-07 | 阿里巴巴集团控股有限公司 | Data storage and the method and apparatus derived |
| CN111427731A (en) * | 2020-03-02 | 2020-07-17 | 中科亿海微电子科技（苏州）有限公司 | Test method and system for automatically splitting code stream and verifying code stream |
| CN112630632A (en) * | 2020-12-28 | 2021-04-09 | 中国科学院空天信息创新研究院 | Implementation method of on-line logic analyzer based on automatic signal pulling |
| CN114297969A (en) * | 2021-12-10 | 2022-04-08 | 广东高云半导体科技股份有限公司 | FPGA-based (field programmable Gate array-based) layout and wiring method and device for online logic analyzer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103164228A (en) * | 2013-03-29 | 2013-06-19 | 北京经纬恒润科技有限公司 | Method and device for generating field-programmable gate array (FPGA) procedure |
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| CN106202121B (en) * | 2015-05-07 | 2019-06-28 | 阿里巴巴集团控股有限公司 | Data storage and derived method and apparatus |
| CN111427731A (en) * | 2020-03-02 | 2020-07-17 | 中科亿海微电子科技（苏州）有限公司 | Test method and system for automatically splitting code stream and verifying code stream |
| CN111427731B (en) * | 2020-03-02 | 2023-08-15 | 中科亿海微电子科技（苏州）有限公司 | Automatic split code stream and verification code stream testing method and system |
| CN112630632A (en) * | 2020-12-28 | 2021-04-09 | 中国科学院空天信息创新研究院 | Implementation method of on-line logic analyzer based on automatic signal pulling |
| CN114297969A (en) * | 2021-12-10 | 2022-04-08 | 广东高云半导体科技股份有限公司 | FPGA-based (field programmable Gate array-based) layout and wiring method and device for online logic analyzer |
| CN114297969B (en) * | 2021-12-10 | 2024-05-14 | 广东高云半导体科技股份有限公司 | Layout wiring method and device of on-line logic analyzer based on FPGA |
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