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CN101740410A - Manufacturing process for a chip package structure - Google Patents

Manufacturing process for a chip package structure Download PDF

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Publication number
CN101740410A
CN101740410A CN200910008383A CN200910008383A CN101740410A CN 101740410 A CN101740410 A CN 101740410A CN 200910008383 A CN200910008383 A CN 200910008383A CN 200910008383 A CN200910008383 A CN 200910008383A CN 101740410 A CN101740410 A CN 101740410A
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CN
China
Prior art keywords
conductive layer
patterned
layer
chip
patterned conductive
Prior art date
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Granted
Application number
CN200910008383A
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Chinese (zh)
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CN101740410B (en
Inventor
沈更新
林峻莹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
Original Assignee
BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority claimed from US12/270,574 external-priority patent/US7851262B2/en
Application filed by BERMUDA CHIPMOS TECHNOLOGIES Co Ltd, Chipmos Technologies Inc filed Critical BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Publication of CN101740410A publication Critical patent/CN101740410A/en
Application granted granted Critical
Publication of CN101740410B publication Critical patent/CN101740410B/en
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Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

A manufacturing process for a chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer are provided, wherein the patterned solder resist layer is positioned on the patterned conductive layer. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are respectively disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. A package colloid is formed to encapsulate the patterned conductive layer, the chips and the bonding wires. Then, the package colloid, the patterned conductive layer and the patterned solder resist layer are separated. According to the invention, a chip package structure can be manufactured without using a core dielectric layer, and thus, the thickness of the manufacture chip package structure is smaller than that of a chip package structure of the prior art.

Description

The processing procedure of chip-packaging structure
Technical field
The invention relates to a kind of processing procedure of chip-packaging structure, and particularly relevant for a kind of processing procedure of thin chip-packaging structure.
Background technology
In semiconductor industry, (integrated circuits, processing procedure IC) mainly is divided into three phases to integrated circuit: the making of integrated circuit (IC) design, integrated circuit and the encapsulation of integrated circuit.
In the processing procedure of integrated circuit, chip system finishes via step such as wafer (wafer) making, circuit design and cut crystal.Wafer has an active face, and it is the surface that has a plurality of active elements formed thereon.After the integrated circuit in forming wafer, on the active face of wafer, form a plurality of connection pads, be electrically connected to carrier so that can see through connection pad by the formed chip of cut crystal.Carrier can be a lead frame or a wiring board.Chip engages (wire bonding) or flip chip bonding modes such as (flip chip bonding) via routing and is electrically connected to carrier (carrier), and the connection pad of its chips is electrically connected to the connection pad of carrier, to form a chip-packaging structure.
Generally speaking, existing wiring board processing procedure all must be used the core dielectric layer, and patterned line layer and pattern dielectric layer alternately are stacked on the core dielectric layer with fully-additive process (fully additive process), semi-additive process (semi-additiveprocess), subtractive process (subtractive process) or other methods that is fit to.By as can be known aforementioned, the thickness of core dielectric layer is the major part of the gross thickness of wiring board.Therefore, if can't reduce the thickness of core dielectric layer effectively, certainly will be unfavorable for reducing the gross thickness of chip-packaging structure.
Summary of the invention
The invention provides a kind of processing procedure of chip-packaging structure, it can make the chip-packaging structure of thinner thickness.
It is as described below that the present invention proposes a kind of processing procedure of chip-packaging structure.At first, provide a patterned conductive layer and a patterned anti-soldering layer patterned anti-soldering layer, patterned anti-soldering layer is disposed on the patterned conductive layer.Then, engage a plurality of chips to patterned conductive layer, so that chip is disposed at respectively on relative two surfaces of patterned conductive layer with patterned anti-soldering layer.Then, electrically connect chip to patterned conductive layer by many leads, its chips and lead are positioned at the same side of patterned conductive layer.Afterwards, form at least one packing colloid, to coat patterned conductive layer, chip and lead.Then, separate package colloid, patterned conductive layer and patterned anti-soldering layer are to form at least one packaging body.
In one embodiment of this invention, provide the method for patterned conductive layer and patterned anti-soldering layer as described below.At first, provide a conductive layer.Then, form a welding resisting layer on conductive layer.Then, patterned anti-soldering layer is to form patterned anti-soldering layer, and wherein patterned anti-soldering layer exposes the partially conductive layer.Afterwards, patterned conductive layer is to form patterned conductive layer.
In one embodiment of this invention, provide the method for patterned conductive layer and patterned anti-soldering layer as described below.At first, provide a welding resisting layer.Then, form a conductive layer on welding resisting layer.Then, patterned anti-soldering layer is to form patterned anti-soldering layer, and wherein patterned anti-soldering layer exposes the partially conductive layer.Afterwards, patterned conductive layer is to form patterned conductive layer.
In one embodiment of this invention, provide the method for patterned conductive layer and patterned anti-soldering layer as described below.At first, provide a conductive layer.Then, form a welding resisting layer on conductive layer.Afterwards, patterned conductive layer is to form patterned conductive layer.Then, patterned anti-soldering layer is to form patterned anti-soldering layer, and wherein patterned anti-soldering layer exposes partially patterned conductive layer.
In one embodiment of this invention, provide the method for patterned conductive layer and patterned anti-soldering layer as described below.At first, provide a welding resisting layer.Then, form a conductive layer on welding resisting layer.Then, patterned conductive layer is to form patterned conductive layer.Afterwards, patterned anti-soldering layer is to form patterned anti-soldering layer, and wherein patterned anti-soldering layer exposes partially patterned conductive layer.
In one embodiment of this invention, a plurality of chip mats and a plurality of pin are formed on the patterned conductive layer.
In one embodiment of this invention, a plurality of openings are formed on the patterned anti-soldering layer.
In one embodiment of this invention, the processing procedure of chip-packaging structure more is included in and forms an outer electrode in each opening, and outer electrode is electrically connected to patterned conductive layer through opening.
In one embodiment of this invention, the processing procedure of chip-packaging structure comprises that more formation one adhesion coating is between chip and patterned conductive layer.
In one embodiment of this invention, the adhesion coating between chip and patterned conductive layer is a B rank adhesion coating.
In one embodiment of this invention, B rank adhesion coating is pre-formed on a back side of chip.
In one embodiment of this invention, before chip adhered to patterned conductive layer, B rank adhesion coating was formed on the patterned conductive layer.
Based on above-mentioned, the processing procedure of chip-packaging structure of the present invention can need not used under the situation of core dielectric layer, produce chip-packaging structure, so the thickness of the prepared chip-packaging structure of processing procedure of chip-packaging structure of the present invention is less than the thickness of existing chip encapsulating structure.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Figure 1A to Fig. 1 G is the processing procedure profile of the chip-packaging structure of one embodiment of the invention.
The main element symbol description:
100,100 ': chip-packaging structure
110: conductive layer
110 ': patterned conductive layer
112: first surface
114: second surface
116: chip mat
118: pin
120: patterned anti-soldering layer
122: opening
130: chip
132: active face
134: the back side
136: connection pad
140: adhesion coating
150: lead
160,160 ': packing colloid
170: outer electrode
Embodiment
Embodiments of the invention can be with reference to the diagram of correspondence, and in diagram or identical the locating to mutually the same or similar of label in describing.
Figure 1A to Fig. 1 G is the processing procedure profile of the chip-packaging structure of one embodiment of the invention.Please refer to Figure 1A, a conductive layer 110 and a patterned anti-soldering layer 120 are provided, wherein conductive layer 110 has a relative first surface 112 and a second surface 114, and patterned anti-soldering layer 120 has a plurality of openings 122.In addition, patterned anti-soldering layer 120 is disposed on the first surface 112 of conductive layer 110, and opens the 122 part first surfaces 112 that expose conductive layer 110.In a preferred embodiment, can apply a brown (brown oxidation) processing procedure or a melanism (black oxidation) processing procedure to conductive layer 110, to increase the surface roughness of conductive layer 110.So, can promote the conjugation grade of conductive layer 110 and patterned anti-soldering layer 120.
In the present embodiment, the method that forms patterned anti-soldering layer 120 is for attaching a B rank glued membrane (B stagedfilm) on the first surface 112 of conductive layer 110, wherein B rank glued membrane also is a welding resisting layer, and the welding resisting layer of this solid-state shape can be patterned before or after being pasted to conductive layer 110 and forms patterned anti-soldering layer 120.In one embodiment, the generation type of patterned anti-soldering layer 120 comprises prior to coating one liquid anti-welding material on the first surface 112 of conductive layer 110 (for example liquid anti-welding material in B rank), to form a liquid anti-welding material layer, then, solidify and this liquid anti-welding material layer of patterning, to form patterned anti-soldering layer 120, curing mode can be by heating or irradiating ultraviolet light.
Then, please refer to Figure 1B, with exposure imaging and etched mode patterned conductive layer 110, to form a patterned conductive layer 110 ', wherein patterned conductive layer 110 ' has a plurality of chip mats 116 and a plurality of pins 118, and patterned anti-soldering layer 120 exposes the part first surface 112 of patterned conductive layer 110 '.It should be noted that the aforementioned formation patterned conductive layer 110 ' and the order of the patterning process of patterned anti-soldering layer 120 are not in order to limit the present invention.In a preferred embodiment, can carry out an electroplating process (platingprocess), on pin 118, to form an electroplated conductive layer (not illustrating).Aforementioned electroplated conductive layer can be a nickel/golden lamination or other metal levels that is fit to.
Then, please refer to Fig. 1 C, a plurality of chips 130 adhere to the second surface 114 of patterned conductive layer 110 ', and chip 130 is disposed at respectively on the chip mat 116.Then, form many leads 150, to connect pin 118 and chip 130, wherein each chip 130 has an active face 132, the back side 134 and an a plurality of connection pad 136 that is disposed on the active face 132 with respect to active face 132.Each chip 130 adheres to patterned conductive layer 110 ' by an adhesion coating 140 that is disposed between chip 130 and the patterned conductive layer 110 '.
In the present embodiment, lead 150 is to form in the mode that routing engages, and each lead 150 electrically connects a pin 118 and a connection pad 136.Lead 150 for example is golden lead.
In the present embodiment, adhesion coating 140 for example is a B rank adhesion coating.B rank adhesion coating can be 8008 or the 8008TH of ABLESTIK.In addition, B rank adhesion coating also can be 6200,6201 or 6202 or HITACHI Chemical CO. of ABLESTIK, the SA-200-6 that Ltd. provides, SA-200-10.In one embodiment of this invention, B rank adhesion coating 140 is formed on the back side of wafer.When wafer is cut, can form a plurality of chips 130, and chip 130 has the adhesion coating 140 that is positioned on its back side 134.Therefore, B rank adhesion coating 140 helps volume production.In addition, the generation type of B rank adhesion coating 140 comprises rotary coating, printing or other processing procedures that is fit to.Clearer and more definite, adhesion coating 140 is formed on the back side 134 of chip 130.Particularly, can provide a wafer earlier, it has a plurality of chips arranged into an array 130.Then, on the back side 134 of chip 130, form a second order adhesion coating, and by heating or the mode of irradiating ultraviolet light makes this second order adhesion coating partly solidified, to form B rank adhesion coating 140.In addition, adhere to patterned conductive layer 110 ' before at chip 130, B rank adhesion coating 140 can be pre-formed on patterned conductive layer 110 '.
In the present embodiment, after chip 130 adheres to patterned conductive layer 110 ', or after a packing colloid coating chip 130, B rank adhesion coating 140 is full solidification.In other embodiments, can carry out a curing process, make its full solidification B rank adhesion coating 140.
Then, please refer to Fig. 1 D, a packing colloid 160 coats patterned conductive layer 110 ', chip 130 and lead 150.The material of packing colloid 160 for example is epoxy resin (epoxy resin).Then, respectively at forming a plurality of outer electrodes 170 in the opening 122, to electrically connect patterned conductive layer 110 '.Outer electrode 170 for example is a soldered ball.
Please refer to Fig. 1 E, compared to Fig. 1 D is to form packing colloid 160 to coat patterned conductive layer 110 ', patterned anti-soldering layer 120, chip 130 and lead 150, and Fig. 1 E forms a plurality of packing colloids 160 ' to coat patterned conductive layer 110 ', patterned anti-soldering layer 120, chip 130 and lead 150.
Please refer to Fig. 1 F and Fig. 1 G, separable a plurality of chip-packaging structures 100 (shown in Fig. 1 F) or a plurality of chip-packaging structure 100 ' (shown in Fig. 1 G) of forming of structure among Fig. 1 D or Fig. 1 E, wherein the method for Fen Liing comprises punching press (punching) or cutting (sawing).
Shown in Fig. 1 F, the chip-packaging structure 100 of present embodiment mainly comprises a patterned conductive layer 110 ', a patterned anti-soldering layer 120, a chip 130, many leads 150 and a packing colloid 160.Patterned conductive layer 110 ' has a relative first surface 112 and a second surface 114.Patterned anti-soldering layer 120 is disposed at first surface 112.Patterned anti-soldering layer 120 exposes the first surface 112 of part.Chip 130 is disposed on the second surface 114 of patterned conductive layer 110 '.Lead 150 is electrically connected to chip 130 and patterned conductive layer 110 '.Packing colloid 160 coats patterned conductive layer 110 ', chip 130 and lead 150.
In sum, compared to the processing procedure of existing chip encapsulating structure, processing procedure of the present invention can make coreless dielectric layer and the less chip-packaging structure of thickness.Therefore, the present invention can reduce cost of manufacture and promote output.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.

Claims (12)

1. the processing procedure of a chip-packaging structure comprises:
One patterned conductive layer and a patterned anti-soldering layer are provided, and wherein this patterned anti-soldering layer is disposed on this patterned conductive layer;
Engage a plurality of chips to this patterned conductive layer, so that those chips are disposed at respectively on relative two surfaces of this patterned conductive layer with this patterned anti-soldering layer;
Electrically connect those chips to this patterned conductive layer by many leads, wherein those chips and those leads are positioned at the same side of this patterned conductive layer;
Form at least one packing colloid, to coat this patterned conductive layer, those chips and those leads; And
Separate this packing colloid, this patterned conductive layer and this patterned anti-soldering layer.
2. the processing procedure of chip-packaging structure as claimed in claim 1 is characterized in that, provides the method for this patterned conductive layer and this patterned anti-soldering layer to comprise:
One conductive layer is provided;
Form a welding resisting layer on this conductive layer;
This welding resisting layer of patterning is to form this patterned anti-soldering layer, and wherein this patterned anti-soldering layer exposes this conductive layer of part; And
This conductive layer of patterning is to form this patterned conductive layer.
3. the processing procedure of chip-packaging structure as claimed in claim 1 is characterized in that, provides the method for this patterned conductive layer and this patterned anti-soldering layer to comprise:
One welding resisting layer is provided;
Form a conductive layer on this welding resisting layer;
This welding resisting layer of patterning is to form this patterned anti-soldering layer, and wherein this patterned anti-soldering layer exposes this conductive layer of part; And
This conductive layer of patterning is to form this patterned conductive layer.
4. the processing procedure of chip-packaging structure as claimed in claim 1 is characterized in that, provides the method for this patterned conductive layer and this patterned anti-soldering layer to comprise:
One conductive layer is provided;
Form a welding resisting layer on this conductive layer;
This conductive layer of patterning is to form this patterned conductive layer; And
This welding resisting layer of patterning is to form this patterned anti-soldering layer, and wherein this patterned anti-soldering layer exposes this patterned conductive layer of part.
5. the processing procedure of chip-packaging structure as claimed in claim 1 is characterized in that, provides the method for this patterned conductive layer and this patterned anti-soldering layer to comprise:
One welding resisting layer is provided;
Form a conductive layer on this welding resisting layer;
This conductive layer of patterning is to form this patterned conductive layer; And
This welding resisting layer of patterning is to form this patterned anti-soldering layer, and wherein this patterned anti-soldering layer exposes this patterned conductive layer of part.
6. the processing procedure of chip-packaging structure as claimed in claim 1 is characterized in that, a plurality of chip mats and a plurality of pin are formed on this patterned conductive layer.
7. the processing procedure of chip-packaging structure as claimed in claim 1 is characterized in that, a plurality of openings are formed on this patterned anti-soldering layer.
8. the processing procedure of chip-packaging structure as claimed in claim 7 is characterized in that, more comprises:
In this opening respectively, form an outer electrode, and those outer electrodes see through those openings and are electrically connected to this patterned conductive layer.
9. the processing procedure of chip-packaging structure as claimed in claim 1 is characterized in that, more comprises:
Form an adhesion coating between those chips and this patterned conductive layer.
10. the processing procedure of chip-packaging structure as claimed in claim 9 is characterized in that, this adhesion coating between those chips and this patterned conductive layer is a B rank adhesion coating.
11. the processing procedure of chip-packaging structure as claimed in claim 10 is characterized in that, this B rank adhesion coating is pre-formed on a back side of this chip.
12. the processing procedure of chip-packaging structure as claimed in claim 10 is characterized in that, before this chip adhered to this patterned conductive layer, this B rank adhesion coating was formed on this patterned conductive layer.
CN2009100083836A 2008-11-13 2009-02-25 Manufacturing process for a chip package structure Active CN101740410B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/270,574 2008-11-13
US12/270,574 US7851262B2 (en) 2005-07-21 2008-11-13 Manufacturing process for a chip package structure

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CN101740410A true CN101740410A (en) 2010-06-16
CN101740410B CN101740410B (en) 2011-10-05

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CN103928410A (en) * 2013-01-11 2014-07-16 精材科技股份有限公司 Package structure and method for manufacturing thereof

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US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
CN100550364C (en) * 2007-10-30 2009-10-14 日月光半导体制造股份有限公司 Encapsulating structure and base plate for packaging thereof

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CN103928410A (en) * 2013-01-11 2014-07-16 精材科技股份有限公司 Package structure and method for manufacturing thereof
CN103928410B (en) * 2013-01-11 2017-01-04 精材科技股份有限公司 Encapsulating structure and preparation method thereof

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