CN101714407B - Row address reserved storage location trigger circuit and row address reserved storage location device - Google Patents
Row address reserved storage location trigger circuit and row address reserved storage location device Download PDFInfo
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- CN101714407B CN101714407B CN2009102117979A CN200910211797A CN101714407B CN 101714407 B CN101714407 B CN 101714407B CN 2009102117979 A CN2009102117979 A CN 2009102117979A CN 200910211797 A CN200910211797 A CN 200910211797A CN 101714407 B CN101714407 B CN 101714407B
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Abstract
The invention discloses a row address reserved storage location trigger circuit and a row address reserved storage location device. The trigger circuit is used for respectively triggering a corresponding storage location of a row address reserved storage location circuit when a first damage storage location or a second damage storage location accesses. The trigger circuit comprises a judging circuit, a first comparison circuit and a second comparison circuit, wherein the judging circuit generates a judging signal according to a relationship between the storage location to access and the row addresses of the first and the second damage storage locations so as to start the first or the second comparison circuit. When the first comparison circuit is started, the row addresses of the storage location to access and the first damage storage location are compared, and the corresponding storage location of the row address reserved storage location circuit is triggered if the row addresses are the same. When the second comparison circuit is started, the row addresses of the storage location to access and the second damage storage location are compared, and the corresponding storage location of the row address reserved storage location circuit is triggered if the row addresses are the same.
Description
Technical field
The present invention relates to the trigger circuit of a kind of row address reserved storage location (Redundant Column Selection Line), the trigger circuit of particularly relevant a kind of common row address reserved storage location device.
Background technology
Please refer to Fig. 1.Fig. 1 is the synoptic diagram of the row address reserved storage location device 100 of prior art.As shown in the figure, row address reserved storage location device 100 comprises row address reserved storage location circuit (Redundant Column Selection Line, RCSL) 110 and trigger circuit 120.Trigger circuit 120 comprise startup fuse group 121, comparator circuit 122 and row address fuse group (column fuse set) 123.
Row address reserved storage location device 100 is used for replacing dynamic RAM (Dynamic RandomAccess Memory, DRAM) the middle storage unit of damaging.For instance, if the storage unit of capable, the Y of X row are damaged in the dynamic RAM, during the storage unit of then capable as storage access X, Y row, trigger circuit 120 can replace the capable storage unit of X by triggering row address reserved storage location circuit 110.Thus, storer just can access not arrive the storage unit of damaging.Therefore, row address reserved storage location circuit 110 comprises delegation's storage unit, has the full line storage unit of a damaged memory unit in order to replacement.
In trigger circuit 120, row address fuse group 123 is used for storing the row address of damaged memory unit.As aforementioned, damaged memory unit is positioned at that X is capable, the Y row, just then row address fuse group 123 to store X capable.Starting fuse group 121 and be used for storing the signal that whether starts driving circuit 120, is to start driving circuit 120 if start fuse group 121 stored signal contents, then starts fuse group 121 and just can start comparator circuit 122; Otherwise,, then start fuse group 121 and just can not start comparator circuit 122 if start the stored signal content of fuse group 121 for not starting driving circuit 120.Comparator circuit 122 comprises one and starts end, a first input end, one second input end and an output terminal.The startup end of comparator circuit 122 is used for receiving the signal that starts fuse group 121 and starts according to this; The first input end of comparator circuit 122 is used for reception memorizer and desires the row address of the storage unit of access; Second input end of comparator circuit 122 is electrically connected at row address fuse group 123, is used for storing the row address (the said X of being is capable like this example) of damaged memory unit.When being that comparator circuit 122 starts; Comparator circuit 122 is understood the row address of the storage unit that compares access that storer is desired and the row address of the damaged memory unit that has write down; If both are identical; Represent that then storer desires the pairing row of storage unit of access, wherein contain the storage unit of damage, then comparator circuit 122 just can send a trigger pip and give row address reserved storage location circuit 110.When row address reserved storage location circuit 110 receives the trigger pip that comparator circuit 122 sent; Just can replace the capable storage unit of X voluntarily, and the storage unit that storer just can access be replaced to row address reserved storage location circuit 110 and can access to the storage unit of damaging.
The shortcoming of prior art is in storer, the storage unit that a damage is arranged in delegation's storage unit is arranged, and row address reserved storage location circuit just needs corresponding delegation's storage unit and replaces with the pairing full line storage unit of the storage unit that a damage will be arranged.In other words; If N the storage unit of damaging arranged respectively at different row; Then row address reserved storage location circuit 110 just needs the capable row address reserved storage location of N with corresponding replacement; Significantly slatterned thus other still can normal operation in the corresponding row of damaged memory unit is arranged storage unit and the number of row address reserved storage location circuit 110 needed storage unit is also bigger, cause unnecessary waste.
In addition; Because the row address reserved storage location device of prior art is when each dynamic RAM access data; Comparator circuit 122 all needs the row address of the storage unit of institute's access is contrasted; And the rapid speed of row address access is also more in the dynamic RAM, that is to say that comparator circuit 122 needs to carry out continually contrast, also quite power consumption for dynamic RAM thus.
Summary of the invention
The present invention provides a kind of trigger circuit of row address reserved storage location circuit.These trigger circuit comprise a decision circuitry, are used for producing one according to an access array address and judge signal; And a plurality of comparator circuits; Be used for receiving this judgement signal; And be electrically connected to this row address reserved storage location circuit jointly, wherein each comparator circuit judges that according to this signal and accessed row address selection property ground produce a trigger pip to this row address reserved storage location circuit.
The present invention more provides a kind of row address reserved storage location device.This row address reserved storage location device comprises a row address reserved storage location circuit, comprises one first row address reserved storage location; And one second row address reserved storage location; And trigger circuit; Be used for when a storage access one first damaged memory unit or one second damaged memory unit; Trigger this first row address reserved storage location of this row address reserved storage location circuit or this second row address reserved storage location of this row address reserved storage location circuit respectively and replace this first damaged memory unit or this second damaged memory unit; This first damaged memory unit has one first and damages row address and one first damage column address; This second damaged memory unit has one second and damages row address and one second damage column address; These trigger circuit comprise a decision circuitry, are used for producing one according to an access array address and judge signal; And one first comparator circuit and one second comparator circuit; Be used for receiving this judgement signal respectively; And be electrically connected to this row address reserved storage location circuit jointly, wherein this first and this second comparator circuit judge that according to this signal and accessed row address selection property ground generation one trigger pip are to this row address reserved storage location circuit.
Description of drawings
Through with reference to above stated specification and following accompanying drawing, technical characterictic of the present invention and advantage are able to obtain to understand fully.
Fig. 1 is the row address reserved storage location schematic representation of apparatus of prior art;
Fig. 2 is the row address reserved storage location schematic representation of apparatus of dynamic RAM of the present invention;
Fig. 3 is the synoptic diagram of an embodiment of decision circuitry;
Fig. 4 is the synoptic diagram of column address bit;
Fig. 5 is the synoptic diagram of row address reserved storage location circuit.
Wherein, Reference numeral
100,200 row address reserved storage location devices
110,220 reserved storage location circuit
120,210 trigger circuit
121,2222,2232 start the fuse group
122,222,223 comparator circuits
123,2221,2231 row address fuse groups
AND
1, AND
2The activation judge module
OR
1Logic gate
S
1, S
2, S
3, S
4Signal
221 decision circuitry
CMP
1, CMP
2Comparer
2211 multiplexers
I
1, I
2, I
3, I
4Input end
RA
3, RA
2, RA
1, RA
0The column address bit
The O output terminal
2212 column address fuse groups
Embodiment
Please refer to Fig. 2.Fig. 2 is the synoptic diagram of the row address reserved storage location device 200 of dynamic RAM of the present invention.As shown in the figure, row address reserved storage location device 200 comprises trigger circuit 210 and row address reserved storage location circuit 220.Trigger circuit 210 comprise decision circuitry 221, comparator circuit 222, comparator circuit 223 and logic gate OR
1Logic gate OR
1Be one or the door (OR gate).Comparator circuit 222 comprises activation judge module AND
1, comparator C MP
1, row address fuse group 2221 and start fuse group 2222.Comparator circuit 223 comprises phase inverter INV
1, activation judge module AND
2, comparator C MP
2, row address fuse group 2231 and start fuse group 2232.Activation judge module AND
1, AND
2For with door (AND gate).
In comparator circuit 222, activation judge module AND
1Comprise two input ends and an output terminal: output terminal, one second input end that a first input end is electrically connected at decision circuitry 221 are electrically connected at startup fuse group 2222, and output terminal is electrically connected at comparator C MP
1The startup end.Activation judge module AND1 will judge signal S
1With start fuse group 2222 stored data do with computing to start comparator C MP
1More particularly, when judging signal S
1When being logical one simultaneously, just can start comparator C MP with startup fuse group 2222 stored data
1When judging signal S
1When having one to be not logical one with startup fuse group 2222 stored data, comparator C MP
1Just can not be activated.Comparator C MP
1Comprise one and start end E, a first input end 1, one second input end 2 and an output terminal O.Comparator C MP
1Startup end E be electrically connected at activation judge module AND
1Output terminal, as activation judge module AND
1During output logic " 1 ", just can start comparator C MP
1Comparator C MP
1 First input end 1 be used for reception memorizer and desire the row address of the storage unit of access; Comparator C MP
1Second input end be electrically connected at row address fuse group 2221, be used for receiving the row address (for example P is capable) of damaged memory unit.At comparator C MP
1During startup, comparator C MP
1Understand the row address of the storage unit that compares access that storer is desired and the row address (P is capable) of the damaged memory unit that has write down; If both are identical; Represent that then storer desires the pairing row of storage unit of access, wherein contain the storage unit of damage, then comparator C MP
1Just can send a trigger pip S
2, through logic gate OR
1, send row address reserved storage location circuit 220 to.
In comparator circuit 223, phase inverter INV
1The output terminal that is electrically connected at decision circuitry 221 will be in order to will judge signal S
1Anti-phase, activation judge module AND
2Comprise two input ends and an output terminal: a first input end is electrically connected at phase inverter INV
1Output terminal, one second input end be electrically connected at and start fuse group 2232, output terminal is electrically connected at comparator C MP
2The startup end.Activation judge module AND
2To judge signal S
1Inversion signal with start fuse group 2232 stored data do with computing to start comparator C MP
2More particularly, when judging signal S
1For logical zero and when starting fuse group 2232 stored data and being logical one, just can start comparator C MP
2At remaining situation, comparator C MP
2Just can not be activated.Comparator C MP
2Comprise one and start end E, a first input end 1, one second input end 2 and an output terminal O.Comparator C MP
2Startup end E be electrically connected at the door AND
2Output terminal, as activation judge module AND
2During output logic " 1 ", just can start comparator C MP
2Comparator C MP
2 First input end 1 be used for reception memorizer and desire the row address of the storage unit of access; Comparator C MP
2Second input end be electrically connected at row address fuse group 2231, be used for receiving the row address (for example Q is capable) of damaged memory unit.At comparator C MP
2During startup, comparator C MP
2Understand the row address of the storage unit that compares access that storer is desired and the row address (Q is capable) of the damaged memory unit that has write down; If both are identical; Represent that then storer desires the pairing row of storage unit of access, wherein contain the storage unit of damage, then comparator C MP
2Just can send a trigger pip S
3, through logic gate OR
1, send row address reserved storage location circuit 220 to.
Logic gate OR
1With the trigger pip S that is received
2With S
3Carry out exclusive disjunction, and produce trigger pip S
4To send row address reserved storage location circuit 220 to.In other words, when producing trigger pip S
2Or S
3The time, row address reserved storage location circuit 220 all can receive trigger pip S
4
And the row address of the stored damaged memory unit of row address fuse group 2221 and 2231 can be (capable capable with Q like aforesaid P) inequality; That is to say; Comparator circuit 222 and 223 can compare the storage unit of different rows respectively, but still can use in the row address reserved storage location circuit 220 the row address reserved storage location with delegation jointly.For instance; If have a damaged memory unit be positioned at P capable the 15th row, another damaged memory unit be positioned at Q capable the 16th row; Then when dynamic RAM is desired the storage unit of capable the 15th row of access P, row address reserved storage location circuit 220 just can use in the row address reserved storage location of delegation the storage unit that replaces capable the 15th row of P corresponding to the row address reserved storage location of the 15th row; And when dynamic RAM was desired the storage unit of capable the 16th row of access Q, reserved storage location circuit 220 just can use with the row address reserved storage location corresponding to the 16th row in the row address reserved storage location of delegation and replace the storage unit that Q the capable the 16th is listed as.Thus, at such situation two every trade address reserved storage locations of need using up, the present invention only need use delegation's row address reserved storage location just can accomplish replacement, more can save the use of storage unit compared to prior art.
Please refer to Fig. 3.Fig. 3 is the synoptic diagram of an embodiment of decision circuitry 221.As shown in the figure, decision circuitry 221 can a multiplexer (multiplexer) 2211 and a column address fuse group 2212 implement.Multiplexer comprises four input end I
1, I
2, I
3, I
4, a control end C and an output terminal O.The input end I of multiplexer 2211
1～I
4Being used for receiving the bit separately of the column address of access memory cell that dynamic RAM is desired respectively, be example with four bits only in this embodiment, but other number bits also can be implemented.Column address fuse group 2212 is electrically connected at the control end C of multiplexer 2211, in order to provide one preset damage column address data to multiplexer 2211 with control multiplexer 2211 with one input end I
1～I
4On a column address bit be sent to its output terminal O, with output as judgement signal S
1RA in the diagram
3Higher bit (the 4th bit), the RA of expression column address
2Inferior higher bit (the 3rd bit), the RA of expression column address
1Inferior low bit (the 2nd bit), the RA of expression column address
0The lowest bit (the 1st bit) of expression column address.And column address fuse group 2212 is just controlled multiplexer 2211 with column address bit RA
3～RA
0In an output with as judgement signal S
1
Please refer to Fig. 4, and simultaneously with reference to figure 3.Fig. 4 is the synoptic diagram of column address bit.As shown in Figure 4, each row all has corresponding column address, and for instance, the column address of the 16th row is [1111], then column address bit RA
3Be " 1 ", column address bit RA
2Be " 1 ", column address bit RA
1Be " 1 ", column address bit RA
0Be " 1 "; The column address of the 15th row is [1110], then column address bit RA
3Be " 1 ", column address bit RA
2Be " 1 ", column address bit RA
1For " 1 ", column address bit RA0 are " 0 ".If the storage unit that the storage unit of capable the 16th row of P is damaged (damaged memory unit 1), capable the 15th row of Q in the dynamic RAM is damaged (damaged memory unit 2), then the column address fuse group 2212 input end I4 that can set multiplexer 2211 is electrically connected at output terminal O.Thus, judge signal S
1Just be column address bit RA
0, distinguish the storage unit that the 16th row and the 15th are listed as with this.When the storage unit of access that dynamic RAM is desired is positioned at the 16th row, then set drive signal S down in this
1Therefore be output as logical one, can starting storage unit that comparator circuit 222 comes comparison access that dynamic RAM is desired, whether to be positioned at P capable, if then transmit trigger pip S
1Give row address reserved storage location circuit 220 to replace this impairment unit; When the storage unit of access that dynamic RAM is desired is positioned at the 15th row, then set drive signal S down in this
1Therefore be output as logical zero, can starting storage unit that comparator circuit 223 comes comparison access that dynamic RAM is desired, whether to be positioned at Q capable, if then transmit trigger pip S
1Give row address reserved storage location circuit 220 with identical delegation but the storage unit of different lines replaces this impairment unit.
Please refer to Fig. 5.Fig. 5 is the synoptic diagram of row address reserved storage location circuit 220.As shown in the figure, row address reserved storage location circuit 220 can be the storage unit of a single row.In this embodiment; Have 16 row; Be that row address reserved storage location circuit 220 comprises 16 storage unit with delegation, and the 16th row storage unit can be used to replacing damaged storage unit 1 and the 15th row storage unit can be used to replacing damaged storage unit 2.Compared to prior art,, then need the row address reserved storage location of two row, and row address reserved storage location circuit 220 of the present invention only needs delegation, more can save the required cost of user if damaged memory unit 1,2 is positioned at different row.
In summary, row address reserved storage location device provided by the present invention can provide the storage unit with identical delegation to replace the damaged memory unit that is positioned at different rows, so can save the use of storage unit.In addition; Row address reserved storage location device provided by the present invention; Do not need each row address of when the dynamic RAM access memory cell, relatively desiring access memory cell whether to belong to the row address of damaged memory unit; So more can reduce consumption of electric, the user is provided bigger convenience.
Certainly; The present invention also can have other various embodiments; Under the situation that does not deviate from spirit of the present invention and essence thereof; Those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (16)
1. the trigger circuit of a row address reserved storage location circuit is characterized in that, these trigger circuit comprise:
One decision circuitry is used for producing one based on an access array address and judges signal; And
A plurality of comparison circuits; Be used for receiving this judgement signal; And be electrically connected to this row address reserved storage location circuit jointly; Wherein each comparison circuit judges that according to this signal and accessed row address choice ground produce a triggering signal to this row address reserved storage location circuit; Wherein, Each comparison circuit comprises: a row address fuse group is used to provide a preset row address data of damaging; One starts the fuse group, is used to provide an enabling signal; One activation judge module, this activation judge module produces an activation signal according to this enabling signal and this judgement signal; One comparison module, this comparison module optionally produces this triggering signal to this row address reserved storage location circuit according to this enable signal, this preset row address data and this accessed row address damaged.
2. trigger circuit according to claim 1 is characterized in that, after these a plurality of comparator circuits received and should judge signal, a comparator circuit produced this trigger pip to this row address reserved storage location circuit at the most.
3. trigger circuit according to claim 1; It is characterized in that; Other comprises a logic gate; Be electrically connected between these a plurality of comparator circuits and this row address reserved storage location circuit, this logic gate is used for this trigger pip that each comparator circuit produces is carried out computing, to trigger this row address reserved storage location circuit.
4. trigger circuit according to claim 1 is characterized in that, this decision circuitry comprises:
One column address fuse group is used to provide a preset column address data that damages; And
One selection circuit, this selection circuit should the judgement signal according to being somebody's turn to do the generation of preset damage column address data and this access array address.
5. trigger circuit according to claim 4; It is characterized in that; This selection circuit is a multiplexer, and this multiplexer optionally should be judged signal with the output of the bit addresses in this access array address to produce according to should presetly damaging column address data.
6. trigger circuit according to claim 4; It is characterized in that; This row address reserved storage location circuit is used in one first damaged memory unit or one second damaged memory unit that replace a storer; When this trigger pip of the output of one first comparator circuit in these a plurality of comparator circuits; One first row address reserved storage location of this row address reserved storage location circuit is triggered replacing this first damaged memory unit, and when this trigger pip of the output of one second comparator circuit in these a plurality of comparator circuits, one second row address reserved storage location of this row address reserved storage location circuit is triggered to replace this second damaged memory unit.
7. trigger circuit according to claim 6; It is characterized in that; This first damaged memory unit has one first and damages row address and one first damage column address; This second damaged memory unit has one second damage row address and one second and damages column address, and this preset column address data that damages is the bit with different data that is used for judging this first damage column address and this second damage column address.
8. based on the described circuits for triggering of claim 1, it is characterized in that, this activation judge module comprise one with the door, be electrically connected to this startup fuse group and this decision circuitry, in order to produce this enable signal.
9. a row address reserved storage location device is characterized in that, comprises:
One row address reserved storage location circuit comprises:
One first row address reserved storage location; And
One second row address reserved storage location; And
One trigger circuit; Be used for when a storage access one first damaged memory unit or one second damaged memory unit; Trigger this first row address reserved storage location of this row address reserved storage location circuit or this second row address reserved storage location of this row address reserved storage location circuit respectively and replace this first damaged memory unit or this second damaged memory unit; This first damaged memory unit has one first and damages row address and one first damage column address; This second damaged memory unit has one second and damages row address and one second damage column address, and these trigger circuit comprise:
One decision circuitry is used for producing one based on an access array address and judges signal; And
One first comparison circuit and one second comparison circuit; Be used for receiving this judgement signal respectively; And be electrically connected to this row address reserved storage location circuit jointly; Wherein this first and this second comparison circuit judge that according to this signal and accessed row address choice ground generation one triggering signal are to this row address reserved storage location circuit; Wherein, This first and this second comparison circuit all comprise: a row address fuse group is used to provide a preset row address data of damaging;
One starts the fuse group, is used to provide an enabling signal; One activation judge module, this activation judge module produces an activation signal according to this enabling signal and this judgement signal; One comparison module, this comparison module optionally produces this trigger pip to this row address reserved storage location circuit according to this enable signal, this preset row address data and this accessed row address damaged.
10. based on the described row address reserved storage location of claim 9 device, it is characterized in that, this first and this second comparison circuit receive should judge signal after, a comparison circuit produces this triggering signal to this row address reserved storage location circuit at the most.
11. row address reserved storage location device according to claim 9; It is characterized in that; Other comprises a logic gate; Be electrically connected at this first and this second comparator circuit and this row address reserved storage location circuit between, this logic gate be used for to this first and this trigger pip of producing of this second comparator circuit carry out computing, to trigger this row address reserved storage location circuit.
12. row address reserved storage location device according to claim 9 is characterized in that this decision circuitry comprises:
One column address fuse group is used to provide one and presets the damage column address data, and this preset column address data system that damages is used for distinguishing this first damage column address and this second damage column address; And
One selection circuit, this selection circuit should the judgement signal according to being somebody's turn to do the generation of preset damage column address data and this access array address.
13. row address reserved storage location device according to claim 12; It is characterized in that; This selection circuit is a multiplexer, and this multiplexer optionally should be judged signal with the output of the bit addresses in this access array address to produce according to should presetly damaging column address data.
14. row address reserved storage location device according to claim 12; It is characterized in that; When this this trigger pip of first comparator circuit output; This first row address reserved storage location of this row address reserved storage location circuit is triggered replacing this first damaged memory unit, and when this this trigger pip of second comparator circuit output, this second row address reserved storage location of this row address reserved storage location circuit is triggered to replace this second damaged memory unit.
15. based on the described row address reserved storage location of claim 9 device, it is characterized in that, this activation judge module comprise one with the door, be electrically connected to this startup fuse group and this decision circuitry, in order to produce this enable signal.
16. row address reserved storage location device according to claim 9 is characterized in that this second comparator circuit comprises a phase inverter in addition, the input end of this phase inverter is coupled to this decision circuitry; The output terminal of this phase inverter is coupled to this second comparator circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102117979A CN101714407B (en) | 2009-11-12 | 2009-11-12 | Row address reserved storage location trigger circuit and row address reserved storage location device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102117979A CN101714407B (en) | 2009-11-12 | 2009-11-12 | Row address reserved storage location trigger circuit and row address reserved storage location device |
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| CN101714407A CN101714407A (en) | 2010-05-26 |
| CN101714407B true CN101714407B (en) | 2012-08-08 |
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| CN102376346B (en) * | 2010-08-20 | 2014-02-12 | 华邦电子股份有限公司 | Dynamic random access memory unit and its data update method |
| CN104008780A (en) * | 2013-02-26 | 2014-08-27 | 中芯国际集成电路制造(上海)有限公司 | Repair method and device for memory cell |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6002623A (en) * | 1997-02-12 | 1999-12-14 | Micron Technology, Inc. | Semiconductor memory with test circuit |
| CN1308336A (en) * | 1999-11-11 | 2001-08-15 | 因芬尼昂技术股份公司 | Memory device |
| CN1537312A (en) * | 2001-03-30 | 2004-10-13 | ض� | Memory cell structural test |
-
2009
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6002623A (en) * | 1997-02-12 | 1999-12-14 | Micron Technology, Inc. | Semiconductor memory with test circuit |
| CN1308336A (en) * | 1999-11-11 | 2001-08-15 | 因芬尼昂技术股份公司 | Memory device |
| CN1537312A (en) * | 2001-03-30 | 2004-10-13 | ض� | Memory cell structural test |
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| CN101714407A (en) | 2010-05-26 |
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