CN101685836B

CN101685836B - Manufacture method of wafer level upright type diode packaging structure

Info

Publication number: CN101685836B
Application number: CN 200810161100
Authority: CN
Inventors: 汪秉龙; 萧松益; 陈政吉
Original assignee: Harvatek Corp
Current assignee: Harvatek Corp
Priority date: 2008-09-26
Filing date: 2008-09-26
Publication date: 2012-05-30
Anticipated expiration: 2028-09-26
Also published as: CN101685836A

Abstract

The invention relates to a manufacture method of a wafer level upright type diode packaging structure. The diode packaging structure comprises a semiconductor material layer I, a semiconductor material layer II, an insulating unit, a first conducting structure and a second conducting structure, wherein the semiconductor material layer II is connected to one surface of the semiconductor material layer I; the insulating unit is coated at the peripheries of the semiconductor material layer I and the semiconductor material layer II; the first conducting structure is formed on the surface of the semiconductor material layer I and one side edge of the insulating unit; and the second conducting structure is formed on the surface of the semiconductor material layer II and the other opposite side edge of the insulating unit. The semiconductor material layer I and the semiconductor material layer II are completely coated by the insulating unit, the first conducting structure and the second conducting structure. The invention reduces the material cost and the processing cost; and the diode packaging structure has shorter conducting path and better conducting characteristic.

Description

The manufacture method of the diode package structure of wafer level upright type

Technical field

The present invention relates to a kind of manufacture method of diode package structure, relate in particular to a kind of manufacture method of diode package structure of wafer level upright type.

Background technology

See also shown in Figure 1ly, it is the generalized section of known diode package structure.By knowing among the above-mentioned figure, known diode package structure has a P type semiconductor material layer P, a N type semiconductor material layer N, a plain conductor L and a packing colloid C.Wherein, This P type semiconductor material layer P and this N type semiconductor material layer N interconnect; This N type semiconductor material layer N directly is electrically connected on the circuit board D, and this P type semiconductor material layer P is electrically connected on this circuit board D through this plain conductor L and with the mode of routing.In addition, this packing colloid C is in order to coat this P type semiconductor material layer P, this N type semiconductor material layer N and this plain conductor L, and to accomplish known diode package structure, the known diode package structure of this kind uses as passive component.

Yet above-mentioned known diode package structure still has following technological deficiency and exists:

1, because known diode package structure also need carry out " metal routing " and reach " colloid encapsulation " twice manufacturing process, therefore cause " material cost " to reach the increase of " processing cost ".

2, because known diode package structure still needs to be connected with this circuit board D generation conduction through this plain conductor L, therefore the conductive path of known diode package structure is longer, and conductive characteristic is relatively poor.

Be with, by on can know that above-mentioned known diode package structure on reality is used, obviously has inconvenience and exists with technological deficiency.Therefore, the property improved of the above-mentioned technological deficiency of inventor's thoughts, and according to the correlation experience of being engaged in for many years in this respect, the concentrated observation and research, and cooperate the utilization of scientific principle, and propose a kind of reasonable in design and effectively improve the present invention of above-mentioned technological deficiency.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of manufacture method of diode package structure of wafer level upright type.The present invention encapsulates two interconnective P type semiconductor material layers and N type semiconductor material layer through the cooperation of at least one insulating barrier and at least two conductive structures, to accomplish a diode package structure; And this diode package structure directly produces with a circuit board through above-mentioned two conductive structures electrically connect at least; So that this diode package structure is arranged on this circuit board with upright mode electrically, so the present invention can produce a kind of diode package structure of wafer level upright type.

In order to solve the problems of the technologies described above; According to wherein a kind of scheme of the present invention; A kind of diode package structure of wafer level upright type is provided, and it comprises: one first type semiconductor material layer, one second type semiconductor material layer, an insulating barrier, one first conductive structure and one second conductive structure.Wherein, this second type semiconductor material layer is connected in a surface of this first type semiconductor material layer.This insulating barrier is optionally around around the part that coats this first type semiconductor material layer, around around this first type semiconductor material layer of coating or around around this first type semiconductor material layer of coating and around the part of this second type semiconductor material layer.This first conductive structure forms on the surface of this first type semiconductor material layer and on the surface of this insulating barrier.This second conductive structure forms on the surface of this second type semiconductor material layer.In addition, through this insulating barrier, this first conductive structure and this second type semiconductor material layer, so that this first type semiconductor material layer is all coated.

In order to solve the problems of the technologies described above; According to wherein a kind of scheme of the present invention; A kind of diode package structure of wafer level upright type is provided, and it comprises: one first type semiconductor material layer, one second type semiconductor material layer, an insulation unit, one first conductive structure and one second conductive structure.Wherein, this second type semiconductor material layer is connected in a surface of this first type semiconductor material layer.This insulation cell rings is wrapped cover this first type semiconductor material layer around and second type semiconductor material layer around.This first conductive structure forms on the surface of this first type semiconductor material layer and on the side of this insulation unit.This second conductive structure forms on the surface of this second type semiconductor material layer and on the other one opposite side of this insulation unit.In addition, this insulation unit have one be used for around coat this first type semiconductor material layer around and first insulating barrier and around the part of second type semiconductor material layer be used for around second insulating barriers that coat around all the other of second type semiconductor material layer.In addition, through this insulation unit, this first conductive structure and this second conductive structure, so that this first type semiconductor material layer and this second type semiconductor material layer are all coated.

In order to solve the problems of the technologies described above; According to wherein a kind of scheme of the present invention; A kind of manufacture method of diode package structure of wafer level upright type is provided; It comprises the following steps: at first, and a diode wafer is provided, and it has the second type, semiconductor material unit that one first type, semiconductor material unit and forms in this bottom, first type, semiconductor material unit; Then, a plurality of grooves that interlock each other and penetrate this first type, semiconductor material unit and the part second type, semiconductor material unit of shaping; Then, be shaped an insulation unit in said a plurality of grooves; Next, be shaped one first conductive unit on the surface of on the surface of this first type, semiconductor material unit and this insulation unit; Then, with this diode wafer upset, so that this second type, semiconductor material unit up; And then, be shaped one second conductive unit on the surface of this second type, semiconductor material unit; At last; Along said a plurality of grooves; Cut this second conductive unit, this second type, semiconductor material unit, this insulation unit and this first conductive unit in regular turn; Forming a plurality of second conductive structures, a plurality of insulating barrier and a plurality of first conductive structure respectively, and accomplish the making of the diode package structure of this wafer level upright type.

In order to solve the problems of the technologies described above; According to wherein a kind of scheme of the present invention; A kind of manufacture method of diode package structure of wafer level upright type is provided; It comprises the following steps: at first in regular turn, and a diode wafer is provided, and it has the second type, semiconductor material unit that one first type, semiconductor material unit and forms in this bottom, first type, semiconductor material unit; Then, a plurality of first grooves that interlock each other and penetrate this first type, semiconductor material unit and the part second type, semiconductor material unit of shaping; Then, be shaped one first insulation unit in said a plurality of first grooves; Next, be shaped one first conductive unit on the surface of on the surface of this first type, semiconductor material unit and this first insulation unit.

And then, with this diode wafer upset, so that this second type, semiconductor material unit up; Then, be shaped a plurality of penetrating components second type, semiconductor material unit and expose second groove of this first insulation unit; Next; Be shaped one second insulation unit in said a plurality of second grooves; So that this first insulation unit and this second insulation unit are connected together; And then make this first type, semiconductor material unit become a plurality of first type semiconductor material layer, make this second type, semiconductor material unit become a plurality of second type semiconductor material layer that are connected with said a plurality of first type semiconductor material layer respectively; Continue, be shaped one second conductive unit on the surface of on the surface of this second type, semiconductor material unit and this second insulation unit; At last; Along said a plurality of first grooves or said a plurality of second groove; Cut this second conductive unit, this second insulation unit, this first insulation unit and this first conductive unit in regular turn; Forming a plurality of second conductive structures, a plurality of second insulating barrier, a plurality of first insulating barrier and a plurality of first conductive structure respectively, and accomplish the making of the diode package structure of this wafer level upright type.

Therefore, the diode package structure of wafer level upright type of the present invention has the advantage existence:

1, because diode package structure of the present invention need not carry out " metal routing " and do not reach " colloid encapsulation " twice manufacturing process, and need not use " package substrate ", so the present invention can reduce " material cost " greatly and reaches " processing cost ".

2, " metal routing " is next to be electrically connected with circuit board generation because diode package structure of the present invention need not pass through; And change to come producing directly electric connection with this circuit board at least through above-mentioned two conductive structures; Therefore the conductive path of diode package structure of the present invention is shorter, and conductive characteristic is preferable.

3, because diode package structure of the present invention directly is shaped with the mode of cutting, the diode package structure that therefore completes does not need to carry out extra attrition process again.

Reach technology, means and the effect that predetermined purpose is taked in order further to understand the present invention; See also following about detailed description of the present invention and accompanying drawing; Believe the object of the invention, characteristic and characteristics; Go deep into and concrete understanding when getting one thus, yet accompanying drawing only provides reference and explanation usefulness, is not to be used for the present invention is limited.

Description of drawings

Fig. 1 is the generalized section of known diode package structure;

Fig. 2 is the flow chart of first embodiment of the manufacture method of the diode package structure of wafer level upright type of the present invention;

Fig. 2 A1 to Fig. 2 I1 is the making flow process generalized section of first embodiment of the manufacture method of the diode package structure of wafer level upright type of the present invention;

Fig. 2 I2 is the schematic perspective view of first embodiment of the diode package structure of wafer level upright type of the present invention;

Fig. 2 J be the diode package structure of wafer level upright type of first embodiment of the invention through the tin ball to be electrically connected at the generalized section on the circuit board;

Fig. 2 K be the diode package structure of wafer level upright type of first embodiment of the invention through tin cream to be electrically connected at the generalized section on the circuit board;

Fig. 3 A is the generalized section of second embodiment of the diode package structure of wafer level upright type of the present invention;

Fig. 3 B is the generalized section of the 3rd embodiment of the diode package structure of wafer level upright type of the present invention;

Fig. 3 C is the generalized section of the 4th embodiment of the diode package structure of wafer level upright type of the present invention;

Fig. 4 is the flow chart of the 5th embodiment of the manufacture method of the diode package structure of wafer level upright type of the present invention;

Fig. 4 A to Fig. 4 I1 is the making flow process generalized section of the 5th embodiment of the manufacture method of the diode package structure of wafer level upright type of the present invention;

Fig. 4 I2 is the schematic perspective view of the 5th embodiment of the diode package structure of wafer level upright type of the present invention;

Fig. 4 J be the diode package structure of wafer level upright type of fifth embodiment of the invention through the tin ball to be electrically connected at the generalized section on the circuit board;

Fig. 4 K be the diode package structure of wafer level upright type of fifth embodiment of the invention through tin cream to be electrically connected at the generalized section on the circuit board; And

Fig. 5 is the generalized section of the 6th embodiment of the diode package structure of wafer level upright type of the present invention.

Wherein, description of reference numerals is following:

[known]

P type semiconductor material layer P

N type semiconductor material layer N

Plain conductor L

Packing colloid C

[the present invention]

(first embodiment)

The diode wafer Wa first type, semiconductor material unit Pa

The second type, semiconductor material unit Na

Groove Ga

Insulation cell S a

The first conductive unit C1a projection bottom metal layer C11a

The first conductive layer C12a

The second conductive layer C13a

The second conductive unit C2a projection bottom metal layer C21a

The first conductive layer C22a

The second conductive layer C23a

The first type semiconductor material layer Pa '

The second type semiconductor material layer Na '

Insulating barrier Sa '

First conductive structure C1a ' projection bottom metal layer C11a '

The first conductive layer C12a '

The second conductive layer C13a '

Second conductive structure C2a ' projection bottom metal layer C21a '

The first conductive layer C22a '

The second conductive layer C23a '

Tin ball B

Tin cream B '

Circuit board P

(second embodiment)

First type semiconductor material layer Pb ' conductive welding disk Ab

First conductive structure C1b ' conductive structure Xb

Insulation system Yb

(the 3rd embodiment)

The first type semiconductor material layer Pc '

Insulating barrier Sc '

(the 4th embodiment)

The first type semiconductor material layer Pd '

Insulating barrier Sd '

(the 5th embodiment)

The diode wafer We first type, semiconductor material unit Pe

The second type, semiconductor material unit Ne

The first groove G1e

The second groove G2e

The first insulation cell S 1e

The second insulation cell S 2e

The first conductive unit C1e projection bottom metal layer C11e

The first conductive layer C12e

The second conductive layer C13e

The second conductive unit C2e projection bottom metal layer C21e

The first conductive layer C22e

The second conductive layer C23e

The first type semiconductor material layer Pe '

The second type semiconductor material layer Ne '

Insulation cell S e '

The first insulating barrier S1e '

The second insulating barrier S2e '

First conductive structure C1e ' projection bottom metal layer C11e '

The first conductive layer C12e '

The second conductive layer C13e '

Second conductive structure C2e ' projection bottom metal layer C21e '

The first conductive layer C22e '

The second conductive layer C23e '

Tin ball B

Tin cream B '

Circuit board P

(the 6th embodiment)

First type semiconductor material layer Pf ' conductive welding disk Af

First conductive structure C1f ' conductive structure Xf

Insulation system Yf

Embodiment

See also Fig. 2, Fig. 2 A1 to Fig. 2 I1, reach shown in Fig. 2 I2, wherein Fig. 2 is the flow chart of first embodiment of the manufacture method of the diode package structure of wafer level upright type of the present invention; Fig. 2 A1 to Fig. 2 I1 is the making flow process generalized section of first embodiment of the manufacture method of the diode package structure of wafer level upright type of the present invention; Fig. 2 I2 is the schematic perspective view of first embodiment of the diode package structure of wafer level upright type of the present invention.By knowing that first embodiment of the invention provides a kind of manufacture method of diode package structure of wafer level upright type among above-mentioned said a plurality of figure, it comprises the following steps:

Step S100 is: at first; Cooperate shown in Fig. 2, Fig. 2 A1 and Fig. 2 A2 (wherein Fig. 2 A1 is the cut-away section sketch map of Fig. 2 A2); A diode wafer Wa is provided, and it has the second type, semiconductor material unit Na that one first type, semiconductor material unit Pa and forms in this Pa bottom, first type, semiconductor material unit.Wherein, according to different design requirements, this first type, semiconductor material unit Pa can be a P type semiconductor material cell, and this second type, semiconductor material unit Na can be a N type semiconductor material cell; Perhaps, this first type, semiconductor material unit Pa can be a N type semiconductor material cell, and this second type, semiconductor material unit Na can be a P type semiconductor material cell.

Step S102 is: cooperate (wherein Fig. 2 B2 is the schematic top plan view of figure B1) shown in Fig. 2, figure B1 and Fig. 2 B2, a plurality of groove Ga that interlock each other and penetrate this first type, semiconductor material unit Pa and the part second type, semiconductor material unit Na are shaped.

Step S104 is: cooperate shown in Fig. 2 and Fig. 2 C, be shaped an insulation cell S a in said a plurality of groove Ga.For instance; Earlier a welding resisting layer being coated this first type, semiconductor material unit Pa upward reaches in said a plurality of groove Ga; And in regular turn through exposure, development, etched cooperation; To form the welding resisting layer that fully only is filled in said a plurality of groove Ga, this welding resisting layer is the above-mentioned insulation cell S a that forms in said a plurality of groove Ga.

Step S106 is: cooperate shown in Fig. 2 and Fig. 2 D, (under bump metallization, UBM) C11a is on the surface of this first type, semiconductor material unit Pa and on the surface of this insulation cell S a for the projection bottom metal layer that is shaped.For instance, through modes such as electroless plating, physical deposition, chemical deposition, sputter or vapor depositions, this projection bottom metal layer C11a is formed on the surface of this first type, semiconductor material unit Pa and on the surface of this insulation cell S a.

Step S108 is: cooperate shown in Fig. 2 and Fig. 2 E, be shaped one first conductive layer C12a on this projection bottom metal layer C11a.For instance, through modes such as plating or electroless platings, this first conductive layer C12a is formed on this projection bottom metal layer C11a.

Step S110 is: cooperate shown in Fig. 2 and Fig. 2 F, be shaped one second conductive layer C13a on this first conductive layer C12a.For instance, through modes such as plating or electroless platings, this second conductive layer C13a is formed on this first conductive layer C12a.

Therefore, above-mentioned steps S106 to step S110 is: the one first conductive unit C1a that is shaped is on the surface of this first type, semiconductor material unit Pa and on the surface of this insulation cell S a.Wherein, this first conductive unit C1a has one and forms on the surface of this first type, semiconductor material unit Pa and the lip-deep projection bottom metal layer C11a, of this insulation cell S a forms in the first conductive layer C12a on this projection bottom metal layer C11a, reaches the second conductive layer C13a that forms on this first conductive layer C12a.

Step S112 is: cooperate shown in Fig. 2 and Fig. 2 G, with this diode wafer Wa upset, so that this second type, semiconductor material unit Na up.

Step S114 is: cooperates shown in Fig. 2 and Fig. 2 H, and identical with the production method of above-mentioned steps S106, be shaped a projection bottom metal layer C21a on the surface of this second type, semiconductor material unit Na.

Step S116 is: cooperates shown in Fig. 2 and Fig. 2 H, and identical with the production method of above-mentioned steps S108, be shaped one first conductive layer C22a on this projection bottom metal layer C21a.

Step S118 is: cooperates shown in Fig. 2 and Fig. 2 H, and identical with the production method of above-mentioned steps S110, be shaped one second conductive layer C23a on this first conductive layer C22a.

In other words, step S114 to step S118 is: be shaped one second conductive unit C2a on the surface of this second type, semiconductor material unit N a.Wherein, this second conductive unit C 2a have one form in this second type, semiconductor material unit N a lip-deep projection bottom metal layer C21a, form in the first conductive layer C22a on this projection bottom metal layer C21a, and the second conductive layer C23a that forms on this first conductive layer C22a.

Step S120 is: cooperate (wherein Fig. 2 I1 is the generalized section of Fig. 2 I2) shown in Fig. 2, Fig. 2 H, Fig. 2 I1 and Fig. 2 I2; Along said a plurality of groove Ga (like direction) along said a plurality of X-X axles of Fig. 2 H; Cut this second conductive unit C2a, this second type, semiconductor material unit Na, this insulation cell S a and this first conductive unit C1a in regular turn, to form a plurality of second conductive structure C2a ', a plurality of insulating barrier Sa ' and a plurality of first conductive structure C1a ' respectively.

Therefore; Shown in Fig. 2 I1 and Fig. 2 I2; Above-mentioned carry out cutting step along said a plurality of groove Ga after; This first type, semiconductor material unit Pa becomes a plurality of first type semiconductor material layer Pa ', makes this second type, semiconductor material unit Na become a plurality of second type semiconductor material layer Na ' that are connected with said a plurality of first type semiconductor material layer Pa ' respectively.In addition, each first conductive structure C1a ' has one and forms on the surface of this first type semiconductor material layer Pa ' and the lip-deep projection bottom metal layer C11a ', of this insulating barrier Sa ' forms in the first conductive layer C12a ' on this projection bottom metal layer C11a ', and the second conductive layer C13a ' that forms on this first conductive layer C12a '.In addition, each second conductive structure C2a ' have one form in this second type semiconductor material layer Na ' lip-deep projection bottom metal layer C21a ', form in the first conductive layer C22a ' on this projection bottom metal layer C21a ', and the second conductive layer C23a ' that forms on this first conductive layer C22a '.

Therefore; Can know by Fig. 2 I1 and Fig. 2 I2; Manufacture method through the invention described above first embodiment; Can produce the diode package structure of a plurality of wafer level upright types, and the diode package structure of each wafer level upright type comprises: one first type semiconductor material layer Pa ', one second type semiconductor material layer Na ', an insulating barrier Sa ', one first conductive structure C1a ', and one second conductive structure C2a '.

Wherein, the second type semiconductor material layer Na ' is connected in the surface of this first type semiconductor material layer Pa '.In addition; According to different design requirements; This first type semiconductor material layer Pa ' can be a P type semiconductor material layer (for example P type silicon (P-type silicon)), and this second type semiconductor material layer Na ' can be a N type semiconductor material layer (for example N type silicon (N-type silicon)); Perhaps, this first type semiconductor material layer Pa ' can be a N type semiconductor material layer, and this second type semiconductor material layer Na ' can be a P type semiconductor material layer.In addition, this insulating barrier Sa ' is around around this first type semiconductor material layer of coating Pa ' and around the part of this second type semiconductor material layer Na '.

Moreover; This first conductive structure C1a ' forms on the surface of this first type semiconductor material layer Pa ' and on the surface of this insulating barrier Sa ', and wherein this first conductive structure C1a ' has one and forms on the surface of this first type semiconductor material layer Pa ' and the lip-deep projection bottom metal layer C11a ', of this insulating barrier Sa ' forms in the first conductive layer C12a ' on this projection bottom metal layer C11a ', and the second conductive layer C13a ' that forms on this first conductive layer C12a '.In addition; This second conductive structure C2a ' forms on the surface of this second type semiconductor material layer Na ', wherein this second conductive structure C2a ' have one form in this second type semiconductor material layer Na ' lip-deep projection bottom metal layer C21a ', form in the first conductive layer C22a ' on this projection bottom metal layer C21a ', and the second conductive layer C23a ' that forms on this first conductive layer C22a '.

Therefore, in the diode package structure of each wafer level upright type, the present invention can pass through this insulating barrier Sa ', this first conductive structure C1a ' and this second type semiconductor material layer Na ', so that this first type semiconductor material layer Pa ' is all coated.

See also shown in Fig. 2 J, its for the diode package structure of the wafer level upright type of first embodiment of the invention through the tin ball to be electrically connected at the generalized section on the circuit board.By knowing among the above-mentioned figure, this first conductive structure C1a ' and this second conductive structure C2a ' are electrically connected on the circuit board P with upright mode through at least two tin ball B respectively.In other words; Be electrically connected on the circuit board P with upright mode through this first conductive structure C1a ' and this second conductive structure C2a ' so that the diode package structure of wafer level upright type of the present invention directly the mode of formula electrically be arranged on this circuit board P.

See also shown in Fig. 2 K, its for the diode package structure of the wafer level upright type of first embodiment of the invention through tin cream to be electrically connected at the generalized section on the circuit board.By knowing among the above-mentioned figure, this first conductive structure C1a ' and this second conductive structure C2a ' are electrically connected on the circuit board P with upright mode through two-layer at least tin cream B ' respectively.In other words; Be electrically connected on the circuit board P with upright mode through this first conductive structure C1a ' and this second conductive structure C2a ' so that the diode package structure of wafer level upright type of the present invention directly the mode of formula electrically be arranged on this circuit board P.

See also shown in Fig. 3 A, it is the generalized section of second embodiment of the diode package structure of wafer level upright type of the present invention.By knowing among the above-mentioned figure; The maximum difference of the second embodiment of the invention and first embodiment (shown in Fig. 2 I1) is: in a second embodiment; One first type semiconductor material layer Pb ' has at least two conductive welding disk Ab insulated from each other, and one first conductive structure C1b ' have two groups of conductive structure Xb and that are electrically connected at above-mentioned at least two conductive welding disks respectively be arranged at above-mentioned two groups of conductive structure Xb between insulation system Yb.Therefore, the diode package structure of the wafer level upright type of second embodiment need on the passive component of a plurality of electrical contacts can be applicable to.

See also shown in Fig. 3 B, it is the generalized section of the 3rd embodiment of the diode package structure of wafer level upright type of the present invention.By knowing among the above-mentioned figure, the maximum difference of the third embodiment of the invention and first embodiment (shown in Fig. 2 I1) is: in the 3rd embodiment, an insulating barrier Sc ' is around around the part that coats one first type semiconductor material layer Pc '.

See also shown in Fig. 3 C, it is the generalized section of the 4th embodiment of the diode package structure of wafer level upright type of the present invention.By knowing among the above-mentioned figure, the maximum difference of the fourth embodiment of the invention and first embodiment (shown in Fig. 2 I1) is: in the 4th embodiment, an insulating barrier Sd ' is around around the coating one first type semiconductor material layer P d '.

In other words; Can know by above-mentioned the first, the 3rd and the 4th embodiment; Through the design of above-mentioned first depth of groove, this insulating barrier (Sa ', Sc ', Sd ') optionally around coat this first type semiconductor material layer P a ' around and (shown in first embodiment) around the part of this second type semiconductor material layer N a ', around (shown in the 3rd embodiment) around the part that coats this first type semiconductor material layer Pc ' or around coat this first type semiconductor material layer Pd ' around (shown in the 4th embodiment).

See also Fig. 4, Fig. 4 A to Fig. 4 I1, reach shown in Fig. 4 I 2, wherein Fig. 4 is the flow chart of the 5th embodiment of the manufacture method of the diode package structure of wafer level upright type of the present invention; Fig. 4 A to Fig. 4 I1 is the making flow process generalized section of the 5th embodiment of the manufacture method of the diode package structure of wafer level upright type of the present invention; Fig. 4 I2 is the schematic perspective view of the 5th embodiment of the diode package structure of wafer level upright type of the present invention.By knowing that fifth embodiment of the invention provides a kind of manufacture method of diode package structure of wafer level upright type among above-mentioned said a plurality of figure, it comprises the following steps:

Step S200 is: at first, cooperate shown in Fig. 4 and Fig. 4 A, a diode wafer We is provided, it has the second type, semiconductor material unit Ne that one first type, semiconductor material unit Pe and forms in this Pe bottom, first type, semiconductor material unit.Wherein, according to different design requirements, this first type, semiconductor material unit Pe can be a P type semiconductor material cell, and this second type, semiconductor material unit Ne can be a N type semiconductor material cell; Perhaps, this first type, semiconductor material unit Pe can be a N type semiconductor material cell, and this second type, semiconductor material unit Ne can be a P type semiconductor material cell.

Step S202 is: cooperate shown in Fig. 4 and Fig. 4 B, a plurality of first groove G1e that interlock each other and penetrate this first type, semiconductor material unit Pe and the part second type, semiconductor material unit Ne are shaped.

Step S204 is: cooperate shown in Fig. 4 and Fig. 4 C, be shaped one first insulation cell S 1e in said a plurality of first groove G1e.For instance; Earlier a welding resisting layer being coated this first type, semiconductor material unit Pe upward reaches in said a plurality of first groove G1e; And in regular turn through exposure, development, etched cooperation; To form the welding resisting layer that fully only is filled in said a plurality of first groove G1e, this welding resisting layer is the above-mentioned first insulation cell S 1e that forms in said a plurality of first groove G1e.

Step S206 is: cooperate shown in Fig. 4 and Fig. 4 D, the projection bottom metal layer C11e that is shaped is on the surface of this first type, semiconductor material unit Pe and on the surface of this first insulation cell S 1e.For instance, through modes such as electroless plating, physical deposition, chemical deposition, sputter or vapor depositions, this projection bottom metal layer C11e is formed on the surface of this first type, semiconductor material unit Pe and the surface of this first insulation cell S 1e on.

Step S208 is: cooperate shown in Fig. 4 and Fig. 4 D, be shaped one first conductive layer C12e on this projection bottom metal layer C11e.For instance, through modes such as plating or electroless platings, this first conductive layer C12e is formed on this projection bottom metal layer C11e.

Step S210 is: cooperate shown in Fig. 4 and Fig. 4 D, be shaped one second conductive layer C13e on this first conductive layer C12e.For instance, through modes such as plating or electroless platings, this second conductive layer C13e is formed on this first conductive layer C12e.

Therefore, above-mentioned steps S206 to step S210 is: the one first conductive unit C1e that is shaped is on the surface of this first type, semiconductor material unit Pe and on the surface of this first insulation cell S 1e.Wherein, this first conductive unit C1e has one and forms on the surface of this first type, semiconductor material unit Pe and the lip-deep projection bottom metal layer C11e, of this first insulation cell S 1e forms in the first conductive layer C12e on this projection bottom metal layer C11e, and the second conductive layer C13e that forms on this first conductive layer C12e.

Step S212 is: cooperate shown in Fig. 4 and Fig. 4 E, with this diode wafer We upset, so that this second type, semiconductor material unit Ne up.

Comparison by Fig. 4 and Fig. 2 can know that the step S200 of fifth embodiment of the invention is identical to step S112 with the step S100 of first embodiment of the invention to step S212.Therefore, after the step S212 of the 5th embodiment, the manufacture method of the diode package structure of the wafer level upright type of the 5th embodiment also further comprises:

Step S214 is: please cooperate shown in Fig. 4 and Fig. 4 F, a plurality of penetrating component second type, semiconductor material unit Ne and expose the second groove G2e of this first insulation cell S 1e are shaped.For instance, the forming mode of said a plurality of second groove G2e is identical with the manufacture method of the step S202 of the said a plurality of first groove G1e of above-mentioned shaping.

Step S216 is: please cooperate shown in Fig. 4 and Fig. 4 G; Be shaped one second insulation cell S 2e in said a plurality of second groove G2e; So that this first insulation cell S 1e and this second insulation cell S 2e are connected together; And then make this first type, semiconductor material unit Pe become a plurality of first type semiconductor material layer Pe ', make this second type, semiconductor material unit Ne become a plurality of second type semiconductor material layer Ne ' that are connected with said a plurality of first type semiconductor material layer Pe ' respectively.In addition, each first type semiconductor material layer Pe ' is combined into a diode with each second type semiconductor material layer Ne '.For instance, the step S204 of this first insulation cell S of forming mode and above-mentioned shaping 1e of this second insulation cell S 2e is identical.

Step S218 is: please cooperate shown in Fig. 4 and Fig. 4 H, be shaped a projection bottom metal layer C21e on the surface of (or on surface of said a plurality of second type semiconductor material layer Ne ') on the surface of this second type, semiconductor material unit Ne and this second insulation cell S 2e.For instance; Through modes such as electroless plating, physical deposition, chemical deposition, sputter or vapor depositions, this projection bottom metal layer C21e is formed on the surface on (or on surface of said a plurality of second type semiconductor material layer Ne ') and this second insulation cell S 2e on the surface of this second type, semiconductor material unit Ne.

Step S220 is: please cooperate shown in Fig. 4 and Fig. 4 H, be shaped one first conductive layer C22e on this projection bottom metal layer C21e.For instance, through modes such as plating or electroless platings, this first conductive layer C22e is formed on this projection bottom metal layer C21e.

Step S222 is: please cooperate shown in Fig. 4 and Fig. 4 H, be shaped one second conductive layer C23e on this first conductive layer C22e.For instance, through modes such as plating or electroless platings, this second conductive layer C23e is formed on this first conductive layer C22e.

Therefore, above-mentioned steps S218 to step S222 is: be shaped one second conductive unit C2e on the surface of (or on surface of said a plurality of second type semiconductor material layer Ne ') on the surface of this second type, semiconductor material unit Ne and this second insulation cell S 2e.Wherein, this second conductive unit C2e has one and forms in the lip-deep projection bottom metal layer C21e, on (or on surface of said a plurality of second type semiconductor material layer Ne ') and this second insulation cell S 2e on the surface of this second type, semiconductor material unit Ne and form in the first conductive layer C22e on this projection bottom metal layer C21e, and the second conductive layer C23e that forms on this first conductive layer C22e.

Step S224 is: cooperate (wherein Fig. 4 I1 is the cross-section illustration intention of Fig. 4 I2) shown in Fig. 4, Fig. 4 H, Fig. 4 I1 and Fig. 4 I2; Along said a plurality of first groove G1e or said a plurality of second groove G2e (like direction) along said a plurality of Y-Y axles of Fig. 4 H; Cut this second conductive unit C2e, this second insulation cell S 2e, this first insulation cell S 1e and this first conductive unit C1e in regular turn, to form a plurality of second conductive structure C2e ', a plurality of second insulating barrier S2e ', a plurality of first insulating barrier S1e ' and a plurality of first conductive structure C1e ' respectively.

Therefore; Shown in Fig. 4 I1 and Fig. 4 I2; Above-mentioned carry out cutting step along said a plurality of first groove G1e or said a plurality of second groove G2e after, each first conductive structure C1e ' has one and forms on the surface of this first type semiconductor material layer Pe ' and the lip-deep projection bottom metal layer C11e ', of this first insulating barrier S1e ' forms in the first conductive layer C12e ' on this projection bottom metal layer C11e ', and the second conductive layer C13e ' that forms on this first conductive layer C12e '.In addition, each second conductive structure C2e ' has one and forms on the surface of this second type semiconductor material layer Ne ' and the lip-deep projection bottom metal layer C21e ', of this second insulating barrier S2e ' forms in the first conductive layer C22e ' on this projection bottom metal layer C21e ', and the second conductive layer C23e ' that forms on this first conductive layer C22e '.

Therefore; Can know by Fig. 4 I1 and Fig. 4 I2; Manufacture method through the invention described above the 5th embodiment; Can produce the diode package structure of a plurality of wafer level upright types, and the diode package structure of each wafer level upright type comprises: one first type semiconductor material layer Pe ', one second type semiconductor material layer Ne ', an insulation cell S e ', one first conductive structure C1e ', and one second conductive structure C2e '.

Wherein, the second type semiconductor material layer Ne ' is connected in the surface of this first type semiconductor material layer Pe '.In addition; According to different design requirements; This first type semiconductor material layer Pe ' can be a P type semiconductor material layer (for example P type silicon (P-type silicon)), and this second type semiconductor material layer Ne ' can be a N type semiconductor material layer (for example N type silicon (N-type silicon)); Perhaps, this first type semiconductor material layer Pe ' can be a N type semiconductor material layer, and this second type semiconductor material layer Ne ' can be a P type semiconductor material layer.

In addition, this insulation cell S e ' around coat this first type semiconductor material layer Pe ' around and the second type semiconductor material layer Ne ' around.Wherein, this insulation cell S e ' have one be used for around coat this first type semiconductor material layer Pe ' around and the first insulating barrier S1e ' and around the part of the second type semiconductor material layer Ne ' be used for around the second insulating barrier S2e ' that coat around all the other of the second type semiconductor material layer Ne '.

Moreover; This first conductive structure C1e ' forms on the surface of this first type semiconductor material layer Pe ' and on the surface of this first insulating barrier S1e ', and wherein this first conductive structure C1e ' has one and forms on the surface of this first type semiconductor material layer Pe ' and the lip-deep projection bottom metal layer C11e ', of this first insulating barrier S1e ' forms in the first conductive layer C12e ' on this projection bottom metal layer C11e ', and the second conductive layer C13e ' that forms on this first conductive layer C12e '.

In addition; This second conductive structure C2e ' forms on the surface of this second type semiconductor material layer Ne ' and on the surface of this second insulating barrier S2e ', and wherein this second conductive structure C2e ' has one and forms on the surface of this second type semiconductor material layer Ne ' and the lip-deep projection bottom metal layer C21e ', of this second insulating barrier S2e ' forms in the first conductive layer C22e ' on this projection bottom metal layer C21e ', and the second conductive layer C23e ' that forms on this first conductive layer C22e '.

Therefore; In the diode package structure of each wafer level upright type; The present invention can be through the first insulating barrier S1e ' and the second insulating barrier S2e ', this first conductive structure C1e ' and this second conductive structure C2e ' of this insulation cell S e ', so that this first type semiconductor material layer Pe ' and this second type semiconductor material layer Ne ' are all coated.In other words, each second conductive structure C2e ', each second insulating barrier S2e ', each first insulating barrier S1e ' and each first conductive structure C1e ' cooperatively interact to encapsulate the diode that each is made up of this first type semiconductor material layer Pe ' and this second type semiconductor material layer Ne '.

See also shown in Fig. 4 J, its for the diode package structure of the wafer level upright type of fifth embodiment of the invention through the tin ball to be electrically connected at the generalized section on the circuit board.By knowing among the above-mentioned figure, this first conductive structure C1e ' and this second conductive structure C2e ' are electrically connected on the circuit board P with upright mode through at least two tin ball B respectively.In other words; Be electrically connected on the circuit board P with upright mode through this first conductive structure C1e ' and this second conductive structure C2e ' so that the diode package structure of wafer level upright type of the present invention directly the mode of formula electrically be arranged on this circuit board P.

See also shown in Fig. 4 K, its for the diode package structure of the wafer level upright type of fifth embodiment of the invention through tin cream to be electrically connected at the generalized section on the circuit board.By knowing among the above-mentioned figure, this first conductive structure C1e ' and this second conductive structure C2e ' are electrically connected on the circuit board P with upright mode through two-layer at least tin cream B ' respectively.In other words; Be electrically connected on the circuit board P with upright mode through this first conductive structure C1e ' and this second conductive structure C2e ' so that the diode package structure of wafer level upright type of the present invention directly the mode of formula electrically be arranged on this circuit board P.

See also shown in Figure 5ly, it is the generalized section of the 6th embodiment of the diode package structure of wafer level upright type of the present invention.By knowing among the above-mentioned figure; The maximum difference of sixth embodiment of the invention and the 5th embodiment (shown in Fig. 4 I1) is: in the 6th embodiment; One first type semiconductor material layer Pf ' has at least two conductive welding disk Af insulated from each other, and one first conductive structure C1f ' has two groups of conductive structure Xf and that are electrically connected at above-mentioned at least two conductive welding disks respectively and is arranged at insulation system Yf between above-mentioned two groups of conductive structure Xf.Therefore, the diode package structure of the wafer level upright type of the 6th embodiment need on the passive component of a plurality of electrical contacts can be applicable to.

In sum, the present invention encapsulates two interconnective P type semiconductor material layers and N type semiconductor material layer through the cooperation of at least one insulating barrier and at least two conductive structures, to accomplish a diode package structure; And this diode package structure directly produces with a circuit board through above-mentioned two conductive structures electrically connect at least; So that this diode package structure is arranged on this circuit board with upright mode electrically, so the present invention can produce a kind of diode package structure of wafer level upright type.

But; The above be merely the detailed description and the accompanying drawing of one best specific embodiment of the present invention, but characteristic of the present invention is not limited thereto; Be not in order to restriction the present invention; All scopes of the present invention should be as the criterion with following claims, and all closing in the embodiment of the spirit variation similar with it of claims of the present invention all should be contained in the category of the present invention; Any those of ordinary skills in the field of the invention, can think easily and variation or modify all can be encompassed in the protection range of following claims of the present invention.

Claims

1. the manufacture method of the diode package structure of a wafer level upright type is characterized in that, comprises the following steps: in regular turn

A diode wafer is provided, and it has the second type, semiconductor material unit that one first type, semiconductor material unit and forms in this bottom, first type, semiconductor material unit;

A plurality of first grooves that interlock each other and penetrate this first type, semiconductor material unit and the part second type, semiconductor material unit are shaped;

Be shaped one first insulation unit in said a plurality of first grooves;

Be shaped one first conductive unit on the surface of on the surface of this first type, semiconductor material unit and this first insulation unit;

With this diode wafer upset, so that this second type, semiconductor material unit up;

A plurality of penetrating components second type, semiconductor material unit and expose second groove of this first insulation unit is shaped;

Be shaped one second insulation unit in said a plurality of second grooves; So that this first insulation unit and this second insulation unit are connected together; And then make this first type, semiconductor material unit become a plurality of first type semiconductor material layer, make this second type, semiconductor material unit become a plurality of second type semiconductor material layer that are connected with said a plurality of first type semiconductor material layer respectively;

Be shaped one second conductive unit on the surface of on the surface of this second type semiconductor material layer and this second insulation unit; And

Along said a plurality of first grooves or said a plurality of second groove; Cut this second conductive unit, this second insulation unit, this first insulation unit and this first conductive unit in regular turn; Forming a plurality of second conductive structures, a plurality of second insulating barrier, a plurality of first insulating barrier and a plurality of first conductive structure respectively, and accomplish the making of the diode package structure of this wafer level upright type.

2. the manufacture method of the diode package structure of wafer level upright type as claimed in claim 1; It is characterized in that: each first type semiconductor material layer is a P type semiconductor material layer, and each second type semiconductor material layer is a N type semiconductor material layer.

3. the manufacture method of the diode package structure of wafer level upright type as claimed in claim 1; It is characterized in that: each first type semiconductor material layer is a N type semiconductor material layer, and each second type semiconductor material layer is a P type semiconductor material layer.

4. the manufacture method of the diode package structure of wafer level upright type as claimed in claim 1; It is characterized in that: through each first conductive structure, each second conductive structure, each first insulating barrier and each second insulating barrier, so that this first type semiconductor material layer and this second type semiconductor material layer are all coated.

5. the manufacture method of the diode package structure of wafer level upright type as claimed in claim 1; It is characterized in that: each first conductive structure has one and forms on the surface of this first type semiconductor material layer and the lip-deep projection bottom metal layer, of this first insulating barrier forms in first conductive layer on this projection bottom metal layer, and second conductive layer that forms on this first conductive layer, and each second conductive structure has one and forms on the surface of this second type semiconductor material layer and the lip-deep projection bottom metal layer, of this second insulating barrier forms in first conductive layer on this projection bottom metal layer, and second conductive layer that forms on this first conductive layer.

6. the manufacture method of the diode package structure of wafer level upright type as claimed in claim 1, it is characterized in that: each first conductive structure and each second conductive structure are electrically connected on the circuit board with upright mode through at least two tin balls or two-layer at least tin cream respectively.

7. the manufacture method of the diode package structure of wafer level upright type as claimed in claim 1; It is characterized in that: each first type semiconductor material layer has at least two conductive welding disks insulated from each other, and each first conductive structure has two groups of conductive structures and that are electrically connected at above-mentioned at least two conductive welding disks respectively and is arranged at the insulation system between above-mentioned two groups of conductive structures.

8. the manufacture method of the diode package structure of wafer level upright type as claimed in claim 1; It is characterized in that: each first type semiconductor material layer and each second type semiconductor material layer are combined into a diode, and each second conductive structure, each second insulating barrier, each first insulating barrier and each first conductive structure cooperatively interact to encapsulate each diode.