CN101459182A - Halbleitervorrichtung - Google Patents
Halbleitervorrichtung Download PDFInfo
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- CN101459182A CN101459182A CNA2008101843998A CN200810184399A CN101459182A CN 101459182 A CN101459182 A CN 101459182A CN A2008101843998 A CNA2008101843998 A CN A2008101843998A CN 200810184399 A CN200810184399 A CN 200810184399A CN 101459182 A CN101459182 A CN 101459182A
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Abstract
A semiconductor apparatus is disclosed. The semiconductor apparatus includes an SOI substrate including an active layer, a buried insulation film and a support substrate; a low potential reference circuit part located in the active layer and operable at a first reference potential; a high potential reference circuit part located in the active layer and operable at a second reference potential; a level-shifting element forming part located in the active layer and for providing a level-shift between the first and second reference potentials; and an insulation member insulating first and second portions of the support substrate from each other, wherein locations of the first and second portions respectively correspond to the low and high potential reference circuit parts.
Description
Technical field
The present invention relates to a kind of semiconductor device, relate more particularly to a kind of semiconductor device of element of the phase inverter as controlling and driving engine etc.
Background technology
For example, high-voltage integrated circuit (HVIC) is a kind of semiconductor device of the element as the power device of control in the phase inverter, and described phase inverter is used to drive the load such as engine etc.
Below with reference to Figure 14 an example that is used to drive the circuit of phase inverter is described.This circuit comprises first element 303, second element 304, as photoelectrical coupler 305a, 305b and the control circuit 306 of level moving meter 305a, 305b.First element can be as the high potential reference circuit parts that drive igbt (IGBT), and described igbt (IGBT) is arranged in the phase inverter 301 that drives engine 300 high-end.Second element can be as the low potential reference circuit parts that drive the IGBTs302b in the low side that is arranged on phase inverter 301.First element can be arranged in the different chips with second element.Photoelectrical coupler 305a, 306b and control circuit 306 are set between chip.In sort circuit, transmit signal by photoelectrical coupler 305a, 305b, thereby between the reference potential of height and low potential reference circuit parts, provide level to move.
Recently, because the miniaturization of phase inverter, foregoing circuit is integrated in the single chip, perhaps in other words, is integrated among the HVIC.As shown in Figure 15, HVIC (being semiconductor device) 406 comprises and is used for the high potential reference circuit parts 403 and the low potential reference circuit parts 404 of IGBTs 402a, 402b of phase inverter 401 of controlling and driving engine 400.HVIC 406 also comprises level moving meter 405 (for example, the LDMOS: laterally diffused metal oxide semiconductor element) with high-breakdown-voltage.
Yet, be formed on HVIC 406 in the single chip have with height and low potential reference circuit parts 403,404 between current potential disturb a relevant difficult problem.This interference causes incorrect operation in the circuit.Because an above-mentioned difficult problem is by using knot to isolate (JI) structure, electric isolation structure or having the groove isolation construction manufacturing element separation of silicon-on-insulator (SOI) substrate (cf.JP-A-2006-93229).Yet, in in the said elements isolation structure any one, when level when the electronegative potential such as 0V moves to high potential such as 750V, higher current potential is (for example, the current potential that surpasses 1200V) the big climbing speed with tens kV/ μ sec produces, and causes big potential amplitude.Intractable is above-mentioned to be had high climbing speed and not to comprise the high voltage surge of fault.Herein, because voltage is very big along with the increase of rise time, so this high voltage surge with high climbing speed is called the dv/dt surge.Especially, because obvious many than logical circuit of the fault that takes place in sort circuit, therefore, above-mentioned dv/dt surge becomes the problem in the circuit with noise-sensitive analog element.
Provide discussion below in conjunction with above-mentioned viewpoint about prior art.In the said elements isolation structure, the groove isolation construction with SOI substrate can have high noise immunity.Can be high potential one side for element separation, groove isolation construction.Yet, having in the level moving meter of groove isolation construction in research and development, the inventor finds following difficulty.When applying the dv/dt surge among the HVIC that is comprising groove isolation construction with SOI substrate, current potential is disturbed by support substrates, produces the displacement current that the parasitic capacitance that is formed at buried oxide (BOX) layer between support substrates and the active layer (being soi layer) is carried out charge or discharge.As a result, circuit can be operated improperly.Figure 25 is the sectional view that the generation of the displacement current among the HVIC is shown, and wherein forms high and low potential reference circuit parts HV, LV in soi layer 511.As shown in figure 25, for example, displacement current produces also (i) and flows into support base 512 from the empty GND current potential parts of high potential reference circuit parts HV via buried layer 513 (being the BOX layer), and (ii) flows into the GND current potential parts of low potential reference circuit parts LV once more via buried layer 513 from support base 512.
Can by so that the BOX layer thicken the mode that reduces parasitic capacitance or, get rid of above-mentioned difficulties so that the impurity concentration on support substrates 512 sides reduces to increase the propagation that the mode of resistance reduces displacement current.Yet for example when integrated when having the amplifier circuit of high power, the micro displacement electric current can become the factor of maloperation.
Summary of the invention
Consider above-mentioned and other is difficult, purpose of the present invention aims to provide a kind of semiconductor device that can suppress that displacement current produces and can the restricting circuits maloperation.
According to a first aspect of the invention, provide a kind of semiconductor device.This semiconductor device comprises SOI substrate 104, buried insulation film and the support substrates with active layer.By the buried insulation film active layer and support substrates are bonded together.This semiconductor device also comprises low potential reference circuit parts and the high potential reference circuit parts in the active layer.The high potential reference circuit parts are exercisable under second reference potential more than or equal to first reference potential.This semiconductor device comprises that also the level moving meter forms parts, and these level moving meter formation parts are in active layer and have the level moving meter, and this level moving meter provides level to move between first reference potential and second reference potential.This semiconductor device also comprises the insulating component with the first of support substrates and second portion mutually insulated.The position of first is corresponding to the low potential reference circuit parts, and the position of second portion is corresponding to the high potential reference circuit parts.
According to above-mentioned semiconductor device, for example, it for example can suppress the generation of the displacement current that causes by the dv/dt surge.It can the incorrect operation of restricting circuits.
According to a second aspect of the invention, provide a kind of semiconductor device.This semiconductor device comprises the semiconductor layer with front surface and rear surface.This semiconductor layer comprises: exercisable low potential reference circuit parts under first reference potential; Exercisable high potential reference circuit parts under second reference potential more than or equal to first reference potential; And have the level moving meter that the level moving meter that level moves is provided form parts between first and second reference potentials.This semiconductor device also be included on the rear surface of semiconductor layer respectively with the corresponding insulating components of first and second parts of low and high potential reference circuit parts.This semiconductor device also comprises with respect to insulating component and low potential reference circuit parts and being provided with on the contrary, and first conductive member that is electrically connected with the first area of low potential reference circuit parts.First reference potential is applied to the first area.This semiconductor device also comprises with respect to insulating component and high potential reference circuit parts and being provided with on the contrary, and second conductive member that is electrically connected with the second area of high potential reference circuit parts.Second reference potential is applied to second area.
According to above-mentioned semiconductor device, it for example can suppress the generation of the displacement current that causes by the dv/dt surge.It can the incorrect operation of restricting circuits.
Description of drawings
According to the detailed description below with reference to accompanying drawing, above-mentioned and other purpose of the present invention, feature and advantage will become more apparent.In the accompanying drawings:
Fig. 1 is the line I-I intercepting in Fig. 2 and sectional view according to the semiconductor device of first embodiment is shown;
Fig. 2 is the schematic diagram that the component placement on the front surface side of the semiconductor device shown in Fig. 1 is shown;
Fig. 3 is the schematic diagram that the component placement on the rear surface side of the semiconductor device shown in Fig. 1 is shown;
Fig. 4 A is that the cross-sectional view of manufacturing according to the technology of the semiconductor device with encapsulating resin of first embodiment is shown to 4E;
Fig. 5 is the curve chart that the displacement current of the relevant dv/dt surge situation in first embodiment and the conventional structure is shown;
Fig. 6 is the sectional view that illustrates according to the semiconductor device of second embodiment;
Fig. 7 A is that the sectional view of manufacturing according to the technology of the semiconductor device with encapsulating resin of second embodiment is shown to 7E;
Fig. 8 is the curve chart that illustrates according to the displacement current of the relevant dv/dt surge situation in second embodiment and the conventional configurations;
Fig. 9 be in Figure 10 line IX-IX intercepting and sectional view according to the semiconductor device of the 3rd embodiment is shown;
Figure 10 is the schematic diagram that the component placement on the rear surface side of the semiconductor device shown in Fig. 9 is shown;
Figure 11 is the sectional view that illustrates according to the semiconductor device of the 4th embodiment;
Figure 12 be in Figure 13 line XII-XII intercepting and sectional view according to the semiconductor device of the 5th embodiment is shown;
Figure 13 is the curve chart that the component placement on the rear surface side of the semiconductor device shown in Figure 12 is shown;
Figure 14 is the schematic diagram that illustrates according to the circuit structure of the phase inverter that is used for the controlling and driving engine of prior art;
Figure 15 is the schematic diagram that illustrates according to another circuit structure of the phase inverter that is used for the controlling and driving engine of prior art;
Figure 16 be in Figure 17 line XVI-XVI intercepting and sectional view according to the semiconductor device of the 6th embodiment is shown;
Figure 17 is the layout that the semiconductor device from observed Figure 16 of front surface side of semiconductor device is shown;
Figure 18 is the sectional view that the Potential distribution in the dielectric substrate of the semiconductor device shown in Figure 16 is shown;
Figure 19 is the sectional view that illustrates according to the semiconductor device of the 7th embodiment;
Figure 20 is the sectional view that illustrates according to the semiconductor device of the 8th embodiment;
Figure 21 is the sectional view that illustrates according to the semiconductor device of the 9th embodiment;
Figure 22 is the sectional view that illustrates according to the semiconductor device of the tenth embodiment;
Figure 23 is the sectional view that illustrates according to the semiconductor device of the 11 embodiment;
Figure 24 is the sectional view that illustrates according to the semiconductor device of the embodiment that revises;
Figure 25 is the sectional view that illustrates according to the displacement current flows among the HVIC of correlation technique;
Figure 26 is the sectional view that illustrates according to the semiconductor device of the modification example of exemplary embodiment; And
Figure 27 illustrates according to another of exemplary embodiment to revise the sectional view of the semiconductor device of example.
Embodiment
Below with reference to accompanying drawing exemplary embodiment is described.
(first embodiment)
The structure of the semiconductor device of first embodiment is described below with reference to Fig. 1 to 3.In the following description, the front surface side of supposing semiconductor device is corresponding to a side of being described in Fig. 1 upside, and a side of being described in the downside of rear surface side corresponding to Fig. 1 of semiconductor device.
As shown in fig. 1, form semiconductor device by utilizing the silicon SOI substrate 104 on the insulator, it comprises by the support substrates 102 of buried oxidation film 103 bondings and soi layer 101.For example, soi layer 101 is made by P type silicon.Soi layer 101 is as active layer 101.Buried oxidation film 103 is as buried insulation film 103.
A plurality of trench isolations members 105 are arranged to a plurality of annular patterns.Low potential reference circuit parts LV, it is corresponding to the zone shown in the left-hand side of Fig. 1 to 3, at outermost trench isolations member 105 and be adjacent in the zone between the trench isolations member 105 of outermost trench isolations member 105.High potential reference circuit parts HV, it to the zone shown in the right-hand side of 3A, is arranged in the zone of the most inboard trench isolations member 105 inside corresponding to Fig. 1.The level moving meter forms area L S between height and low potential reference circuit parts HV and LV.
The low potential reference circuit parts LV of soi layer 101 comprises signal processing circuit, and this signal processing circuit for example drives for logical circuit and by electronegative potential.Low potential reference circuit parts LV is by trench isolations member 105 other isolation of components with semiconductor device.Low potential reference circuit parts LV comprises multiple element (for example, CMOS 110), and described multiple element is the element of signal processing circuit.More specifically, insulating barrier 111 is disconnected from each other with element in soi layer 101.Can provide insulating barrier 111 from (STI), local oxidation of silicon (LOCOS) layer or the like by shallow trench isolation.For example, separated region comprises N trap layer 112a and P trap layer 112b.P+ type source region 113a and P+ type drain region 114a are arranged in N trap layer 112a.N+ type source region 113b and N+ type drain region 114b are arranged in P trap layer 112b.By gate insulating film 115a, gate electrode 116a is arranged on the surface of N trap layer 112a, this surface is between P+ type source region 113a and P+ type drain region 114a.By gate insulating film 115b, gate electrode 116b is arranged on the surface of P trap layer 112b, this surface is between N+ type source region 113b and N+ type drain region 114b.Therefore, provide a kind of CMOS110 with N-channel MOS FET and P channel mosfet.
Low potential reference circuit parts LV comprises kind of thread elements (not shown) and the interlayer dielectric (not shown) on the front surface side that is positioned at soi layer 101.Kind of thread elements is electrically connected with the element of CMOS 110, and the element of described CMOS 110 comprises each gate electrode 116a, 116b, each source region 113a, 113b and each drain region 114a, 114b.Low potential reference circuit parts LV can also comprise bipolar transistor, diffused resistor, memory or the like (not shown).
High potential reference circuit parts HV comprises signal processing circuit, and this signal processing circuit for example drives for logical circuit and by high potential.High potential reference circuit parts HV is by trench isolations member 105 other isolation of components with semiconductor device.High potential reference circuit parts HV comprises CMOS 110, its structure with low potential reference circuit parts LV in basic identical.High potential reference circuit parts HV can also comprise bipolar transistor, diffused resistor, memory or the like (not shown).
The level moving meter forms parts LS and comprises as having the Laterally Diffused Metal Oxide Semiconductor (LDMOS) 120 of the level moving meter 120 of high-breakdown-voltage.In the surface portion of soi layer 101, LDMOS 120 has N type drain region 121, P type channel region 122 and N+ type source region 123.In the surface portion of N type drain region 121, form N+ type contact layer 124.In the surface portion of P type channel region 122, form P+ type contact layer 125.N type drain region 121 and P type channel region 122 are separated from each other by LOCOS oxide layer 126.By gate insulating film 127 gate electrode 128 is arranged on the P type channel region 122.Therefore, provide LDMOS 120 with high-breakdown-voltage.
On the front surface side of soi layer 101, form kind of thread elements (not shown) and interlayer dielectric (not shown).With kind of thread elements and gate electrode 128, N+ type source region 123 and P+ type contact layer 125, or N+ type contact layer 124 is electrically connected.
Between low and high potential reference parts LV and HV, be formed for having a plurality of unit of the LDMOS 120 of above-mentioned structure and high-breakdown-voltage.By trench isolations member 105, that a plurality of unit are disconnected from each other.
Make support substrates 102 by silicon substrate.As shown in Fig. 1 and 3, support substrates 102 only is retained in the position that corresponds respectively to low and high potential reference circuit parts LV, HV.Insulating component 130 is embedded the position of wherein removing support substrates.By low permittivity made insulating component 130, for example described low permittivity material is the resin (for example, epoxy resin) that is used to seal.
In semiconductor device, support substrates 102 has at first below the low potential reference circuit parts LV and the second portion below high potential reference circuit parts HV.The first of support substrates 102 and second portion are by insulating component 130 mutual insulatings.Therefore, the first and the current potential between the second portion that can be suppressed at support substrates 102 propagated.This causes the potential difference between soi layer 101 and the support substrates 102 to reduce.Therefore, can suppress parasitic capacitance is carried out the generation of the displacement current of charge or discharge, and the maloperation in the inhibit circuit.
Though insulating component 130 makes the first and the second portion mutual insulating of support substrates 102, the parasitic capacitance of the permittivity of insulating component 130 can appear depending on.Because the first and the second portion of support substrates 102 are separated larger distance mutually, therefore, parasitic capacitance is very little, can suppress the generation of displacement current fully.But, preferred insulating component 130 is made by the material with alap permittivity, because parasitic capacitance depends on the permittivity of insulating component 130.
Can make above-mentioned semiconductor device by following method.Form the element of low potential reference circuit parts, the element of high potential reference circuit parts and the element that the level moving meter forms area L S.Partly remove support substrates 102.Then, insulating component 130 is embedded the position that is removed part that wherein once had support substrates 102.
To Fig. 4 E, describe a kind of method of making semiconductor device with reference to figure 4A in more detail below.Fig. 4 A is the sectional view that respectively illustrates according to the manufacturing process of the semiconductor device with encapsulating resin of present embodiment to 4E.In order to simplify, Fig. 4 A does not illustrate the element that is formed in the soi layer 101 to Fig. 4 E.
As shown in Fig. 4 A, after the element of element that forms low and high potential reference circuit parts LV, HV and level moving meter formation parts LS, the rear surface of polishing support substrates 102.Mask 131 with silicon oxide layer 131a and silicon nitride film 131b is set on the polished rear surface of support substrates 102.By using mask 131, by etching part remove support substrates 102.Carry out above-mentioned technology by in oxide layer and another layer, adopting the wet etching of KOH solution with high selectivity.The KOH solution that is adopted is to employed similar in the technology of the barrier film (diaphragm) that forms pressure sensor etc.
As shown in Fig. 4 B, so apply insulating component 130 so that cover support substrates 102 and wherein once had the zone partly that is removed of support substrates.As shown in Fig. 4 C, die bonding film 132 is arranged on the surface of insulating component 130.Then, as shown in Fig. 4 D, semiconductor device is bonded to lead frame 133 by die bonding film 132.As shown in Fig. 4 E, external connection terminals 134 is electrically connected with the predetermined portions of semiconductor device by using bonding line 135.Cover by the part of encapsulating resin member 136 semiconductor device, lead frame 133 and external connection terminals 134.By said method, can make semiconductor device with encapsulating resin.
To as shown in the 4E, support substrates 102 is covered fully by insulating component 130 as Fig. 4 A.Perhaps, after applying insulating component 130, can grind insulating component 130 till exposing support substrates 102, so that insulating component 130 is retained in the space that is removed part that wherein once had support substrates 102.
The inventor carries out emulation, makes semiconductor device be connected to the phase inverter (not shown) that drives engine.More specifically, a kind of situation of this simulation process, wherein will be used for a kind of like this square wave of voltage input conduct that level moves, thereby its voltage switches the reference potential that high and low potential reference circuit parts HV and LV are provided with the given time interval between 0V and 750V level moves.Applying when being used for voltage that level moves, be desirably in the moment that voltage switches from 0V to 750V, voltage can exceed 750V immediately and reach 1200V and 1300V between, cause big dv/dt surge.The inventor is devoted to study the displacement current of relevant dv/dt surge situation, and obtains the result shown in Fig. 5.
As shown in Figure 5, the displacement current in the semiconductor device of present embodiment is than little two orders of magnitude of displacement current of conventional configurations.Semiconductor device that it should be noted that conventional configurations has support substrates 102, and it is for monolithic integrated circuit and be not divided in blocks.This emulation proves that also the semiconductor device of present embodiment can the limiting displacement electric current and have above-mentioned advantage.
(second embodiment)
Difference between the semiconductor device of the semiconductor device of present embodiment and first embodiment comprises: the structure that is used to be provided with the current potential of support substrates 102.
Fig. 6 is the sectional view that a kind of semiconductor device according to present embodiment (being HVIC) is shown.As shown in Figure 6, semiconductor device has the second terminal (not shown) of the reference potential that receives the high potential reference circuit HV of portion.The second portion of second terminal and support substrates 102 is electrically connected mutually, so that have essentially identical current potential.The second portion of support substrates 102 is arranged on position corresponding to high potential reference circuit parts HV, perhaps in other words, second portion is provided with high potential reference circuit parts HV on the contrary with respect to buried oxidation film 103.More specifically, the base portion 141 that will have a conductive pattern 140 is bonded to the rear surface of the second portion of support substrates 102.By lead 142 conductive pattern 140 is electrically connected with second terminal.
Semiconductor device has the first terminal (not shown) of the reference potential that receives the low potential reference circuit parts LV in the soi layer 101.The first of the first terminal and support substrates 102 is electrically connected mutually, so that have essentially identical current potential.The first of support substrates 102 is arranged on position corresponding to low potential reference circuit parts LV, perhaps in other words, first is provided with low potential reference circuit parts LV on the contrary with respect to buried oxidation film 103.More specifically, the base portion 144 that will have a conductive pattern 143 is bonded to the rear surface of the first of support substrates 102.By lead 145 conductive pattern 143 is electrically connected with second terminal.
In above-mentioned structure, the second portion of support substrates 102 and high potential reference circuit parts HV can have essentially identical current potential, and the first of support substrates 102 and low potential reference circuit parts LV can have essentially identical current potential.That is, the corresponding region on two of buried oxidation film 103 sides can have essentially identical current potential.Therefore the more effectively generation of limiting displacement electric current.
The difference of making between the method for method and first embodiment of semiconductor device of present embodiment comprises: the technology that is electrically connected support substrates 102 and conductive pattern 140,143.
Fig. 7 A is that the cross-sectional view of a kind of manufacturing according to the method for the semiconductor device with encapsulating resin of present embodiment is shown to 7E.To 7E a kind of method of making semiconductor device is described below with reference to Fig. 7 A.In order to simplify, Fig. 7 A does not illustrate the element that is formed in the soi layer to 7E.
At first, carry out corresponding to the technology shown in Fig. 4 A.Then, as shown in Figure 7A, utilize the surface of the semiconductor device on the resist 146a protection front surface side.Etching is used for the resin of insulating component 130, and etching mask 131 then.Then, as shown in Fig. 7 B, after removing resist 146a, depositing metal layers 147 on the rear surface of support substrates 102.Be provided for metal level 147 is carried out the mask 148 of composition.Then, as shown in Fig. 7 C, utilize the surface on the resist 146b protection soi layer 101.By using 148 pairs of metal levels of mask 147 to carry out composition.By said method, form by metal level 147 conductive patterns 140 that provide and that be electrically connected with the second portion of support substrates 102.In addition, form conductive pattern 143, it is to be provided and be electrically connected with the first of support substrates 102 by metal level 147.
Then, as shown in Fig. 7 D, after removing mask 148 and resist 146b, conductive pattern 140,143 is electrically connected to the lead frame 133 that is used for base portion 141,144 by scolder 149.Then, as shown in Fig. 7 E, external connection terminals 134 is electrically connected on the predetermined parts of semiconductor device by bonding line 135.Lead frame 133 is electrically connected on external connection terminals 134, and this external connection terminals 134 is electrically connected by bonding line 135 one of them with high and low potential reference circuit parts HV, LV.By external connection terminals 134 and lead frame 133, the second portion of high potential reference section H V and support substrates 102 can have essentially identical current potential, and the first of low potential reference partial L V and support substrates 102 can have essentially identical current potential.That is, the corresponding region of two of buried oxidation film 103 sides can have essentially identical current potential.Then, encapsulating resin member 136 covers the part of semiconductor device, lead frame 133, external connection terminals.By said method, can make semiconductor device with encapsulating resin according to present embodiment.
Carry out emulation in the mode similar to the description among first embodiment.Result shown in Fig. 8, it shows: the semiconductor device of present embodiment can be than the more effectively generation of limiting displacement electric current of semiconductor device of first embodiment.Displacement current is than little general three orders of magnitude of displacement current of conventional configurations.
(the 3rd embodiment)
Difference between the semiconductor device of the semiconductor device of present embodiment and first embodiment comprises: the layout of support substrates 102.In the present embodiment, support substrates 102 has third part, and it is positioned at corresponding to element outside position component.
Fig. 9 be in Figure 10 line IX-IX intercepting and sectional view according to the semiconductor device of present embodiment is shown.Figure 10 is the schematic diagram that the component placement on the rear surface side of the semiconductor device shown in Fig. 9 is shown.
As shown in Fig. 9 and 10, element outside portion 150 is positioned at the outside of outermost channel insulation member 105.The third part of support substrates 102 is positioned at the position corresponding to element outside portion 150.The third part of support substrates 102 is opposite with element outside portion 150 with respect to buried oxidation film 103.More specifically, the third part of support substrates 102 has U-shaped shape roughly.Third part has two side components, and it extends along the direction of wherein arranging high and low potential reference circuit parts HV and LV.The parts of element outside portion 150 also have the opposite side parts, and it is towards low potential reference circuit parts LV.
When support substrates 102 had above-mentioned parts in the position corresponding with element outside parts 150, it can improve housing intensity.
(the 4th embodiment)
Difference between the semiconductor device of the semiconductor device of present embodiment and second embodiment comprises: in the mode similar to the 3rd embodiment, support substrates has this structure in the third part of the position corresponding with element outside parts.
Figure 11 is the sectional view that illustrates according to the semiconductor device of present embodiment.As shown in Figure 11, the third part of support substrates is arranged on position corresponding to element outside parts 150.According to above-mentioned structure, the semiconductor device of present embodiment can have the advantage the same with second embodiment.In addition, it can improve the intensity of the housing of semiconductor device.
According to present embodiment,, the third part of support substrates 102 terminal with the reference potential that is used to obtain low potential reference circuit parts LV is electrically connected by conductive pattern 143.Perhaps, the third part of support substrates 102 can be in the floating state, and needn't have the current potential of the reference potential that equals low potential reference circuit parts LV substantially.
(the 5th embodiment)
Difference between the semiconductor device of the semiconductor device of present embodiment and the 3rd embodiment comprises: the layout of support substrates 102.
Figure 12 is the line XII-XII intercepting in Figure 13 and sectional view according to the semiconductor device of present embodiment is shown.Figure 13 is the schematic diagram that the component placement on the rear surface side of the semiconductor device among Figure 12 is shown.
As shown in Figure 12 and 13, support substrates 102 has third part, and it is arranged on position corresponding to element outside parts 150.The third part of support substrates 102 is connected with first and integrates.Semiconductor device with above-mentioned structure can have the advantage similar to second embodiment.In addition, it can improve the intensity of the housing of semiconductor device.
(modification of first to the 5th embodiment)
First to the 5th embodiment has provided the example element of low potential reference circuit parts LV, high potential reference circuit parts HV and level moving meter formation parts LS.Perhaps, each partial L V, HV, LS can comprise and be different from above-mentioned example element or other element except that above-mentioned example element.
In first to the 5th embodiment, the insulating component 130 between the part of support substrates 102 is formed from a resin.Perhaps, insulating component 130 can be the dielectric film such as oxide-film etc.Perhaps, insulating component 130 can be air, vacuum etc.When insulating component 130 was air or vacuum, though this insulating component 130 does not have solid, air or vacuum can be used as insulating component 130.When insulating component 130 is vacuum, need sealing.For example, need be used for the shell of holding semiconductor to keep vacuum.In other words, it need be provided for utilizing the structure of vacuum as insulating component 130.
In the 3rd to the 5th embodiment, the third part of support substrates 102 has U-shaped shape roughly.Yet the shape of the third part of support substrates 102 is not limited to above-mentioned example.For example, the third part of support substrates 102 can be arranged on corresponding to the position of whole element outside parts 150 and can have roughly tubular shape.Perhaps, third part only has two side components, its each along the direction extension of wherein arranging high and low potential reference circuit parts HV and LV.Perhaps, third part can have a side of extending along the direction of wherein arranging high and low potential reference circuit parts HV and LV, and have opposite side parts, its towards high or low current potential reference circuit parts HV, LV so that third part has L shaped shape roughly.
In second embodiment and the 4th embodiment, the first of low potential reference circuit parts LV and support substrates 102 has essentially identical current potential, and the second portion of high potential reference circuit parts HV and support substrates 102 has essentially identical current potential.Perhaps, only the second portion of high potential reference circuit parts HV and support substrates 102 can have essentially identical current potential.In above-mentioned situation, semiconductor device can have above-mentioned advantage.
In second embodiment and the 4th embodiment, lead 142 is electrically connected the second portion of high potential reference circuit parts HV and support substrates 102, and lead 145 is electrically connected the first of low potential reference circuit parts LV and support substrates 102.Perhaps, in order such electrical connection to be provided, can to adopt structure or the element that is different from lead 142,145.For example, as shown in figure 26, through electrode (penetration electrode) 162 can be electrically connected the second portion of high potential reference circuit parts HV and support substrates 102.And another through electrode 160 can be electrically connected the first of low potential reference circuit parts LV and support substrates 102.As shown in figure 26, through electrode 160,162 can be arranged in the groove 161,163.More specifically, groove 161,163 and through electrode 160,162 can penetrate soi layer 101 and buried oxidation film 103.Perhaps, as shown in figure 27, have the structure 104 of partial SOI structure by utilization, low and high potential reference parts LV, HV can be electrically connected with support substrates 102.In the partial SOI structure, buried oxidation film 103 has and is not to be made but the part for example made by silicon by insulating material.As shown in figure 27, first silicon parts 170 of buried oxidation film 103 can be arranged between the first of low potential reference circuit parts LV and support substrates 102, so that low potential reference circuit parts LV is electrically connected with the first of support substrates 102.Second silicon parts 172 can be arranged between the second portion of high potential reference circuit parts HV and support substrates 102, so that high potential reference circuit parts HV is electrically connected with the second portion of support substrates 102.Therefore, first and second silicon parts 170,172 in the partial SOI structure can be used as through electrode.
In the semiconductor device of the foregoing description, by using lead 142,145, through electrode 160,162, the silicon parts 170,172 in the partial SOI structure etc., low and high potential reference circuit parts LV, HV can be electrically connected with first and second parts of support substrates 102 respectively.Perhaps, by connect up 142, silicon parts 172 in the through electrode 162, partial SOI structure etc., high potential reference circuit parts HV is electrically connected with the second portion of support substrates 102, and low potential reference circuit parts LV then may not be electrically connected with the first of support substrates 102.Perhaps, by connect up 145, silicon parts 170 in the through electrode 160, partial SOI structure etc., low potential reference circuit parts LV is electrically connected with the first of support substrates 102, and high potential reference circuit parts HV then may not be electrically connected with the first of support substrates 102.
(the 6th embodiment)
The structure of the semiconductor device of the 6th embodiment is described below with reference to Figure 16 to 17.Figure 16 is line XVI-XVI intercepting in Figure 17 and the sectional view that the semiconductor device (being HVIC) according to the 6th embodiment is shown.Figure 17 is from the observed schematic layout pattern of the top surface side of the semiconductor device shown in Figure 16.In description subsequently, the upside of supposing Figure 16 is the front surface side of semiconductor device, and the downside of hypothesis Figure 16 is the rear surface side of semiconductor device.
As shown in Figure 16, the semiconductor device of present embodiment comprises semiconductor layer 201, dielectric substrate 202, lead frame 203 and bonding line 204.Semiconductor layer 201 is for example made by the silicon with N conduction type.By dielectric substrate 202 semiconductor layer 201 is bonded to lead frame 203.Be electrically connected with lead frame 203 by the predetermined portions of bonding line 204 semiconductor layer 201.Dielectric substrate 202 can be used as insulating component 202.
A plurality of trench isolations members 205 are arranged to a plurality of annular patterns.Low potential reference circuit parts LV, it is corresponding to the zone shown in the left-hand side of Figure 16, at outermost trench isolations member 205 and be adjacent in the zone between the trench isolations member 205 of outermost trench isolations member 205.High potential reference circuit parts HV, it is corresponding to the zone shown in the right-hand side of Figure 16 A, in the most inboard groove insulating element 205 area surrounded of quilt.The level moving meter forms in the zone of parts LS between height and low potential reference circuit parts HV and LV.
The low potential reference circuit parts LV of semiconductor layer 201 comprises signal processing circuit, and this signal processing circuit for example drives for logical circuit and by electronegative potential.Signal processing circuit is in reference potential (the i.e. first current potential) operation down of 0V.By trench isolations member 205 other isolation of components with low potential reference circuit parts LV and semiconductor device.Low potential reference circuit parts LV comprises as the multiple element of the element of signal processing circuit (for example, CMOS 210).More specifically, it is disconnected from each other with element at semiconductor layer 201 to be used for the insulating barrier 211 that element separates.Insulating barrier 211 can be that shallow trench isolation is from (STI), local oxidation of silicon (LOCOS) layer etc.For example, each separate areas is N trap layer 212a or P trap layer 212b.P+ type source region 213a and P+ type drain region 214a are arranged in N trap layer 212a.N+ type source region 213b and N+ type drain region 214b are arranged in P type trap layer 212b.By gate insulating film 215a, gate electrode is arranged on the surface of N trap layer 212a, this surface is between P+ type source region 213a and P+ type drain region 214a.By gate insulating film 215b, gate electrode 216b is arranged on the surface of P trap layer 212b, this surface is between N+ type source region 213b and N+ type drain region 214b.Therefore, the CMOS 210 of the combination with N-channel MOS FET and P channel mosfet is provided.
The low potential reference circuit parts LV of semiconductor layer 201 comprises the interlayer dielectric (not shown) on the front surface side of kind of thread elements (not shown) and semiconductor layer 201.Kind of thread elements is electrically connected with the element of CMOS 210, and the element of described CMOS 210 comprises each gate electrode 216a, 216b, each source region 213a, 213b and each drain region 214a, 214b.Low potential reference circuit parts LV can also comprise (not shown)s such as bipolar transistor, diffused resistor, memory.
The high potential reference circuit parts HV of semiconductor layer 201 comprises signal processing circuit, and this signal processing circuit for example drives for logical circuit and by high potential.Signal processing circuit is operated under the reference potential of for example 1200V, and it is greater than the reference potential of low potential reference circuit parts LV.It is second current potential that the reference potential of high potential reference circuit parts HV is also called.By trench isolations member 205 other isolation of components with high potential reference circuit parts HV and semiconductor device.High potential reference circuit parts HV comprises CMOS 210, and its structure is basic identical with the structure of low potential reference circuit parts LV.High potential reference circuit parts HV can also comprise (not shown)s such as bipolar transistor, diffused resistor, memory.
The level moving meter forms parts LS and comprises as the LDMOS (LDMOS: Laterally Diffused Metal Oxide Semiconductor) with level moving meter 220 of high-breakdown-voltage.In the surface portion of semiconductor layer 201, LDMOS comprises N type drain region 221, P type channel region 222 and N+ type source region 223.In the surface portion of N type drain region 221, form N+ type contact layer 224.In the surface portion of P type channel region 222, form P+ type contact layer 225.By locos oxide film 226 that N type drain region 221 and P type channel region 222 is disconnected from each other.By gate insulating film 227 gate electrode 228 is arranged on the P type channel region 222.The LDMOS 220 that utilizes above-mentioned structure to provide to have high-breakdown-voltage.
On the front surface side of semiconductor layer 201, form kind of thread elements (not shown) and interlayer dielectric (not shown).Kind of thread elements is electrically connected with gate electrode 228, N+ type source region 223 and P+ type contact layer 225 or N+ type contact layer 224.
Between low and high potential parts LV, HV, form a plurality of unit that respectively comprise LDMOS 220 with above-mentioned structure and high-breakdown-voltage.By trench isolations member 205 that a plurality of unit are disconnected from each other.
Make dielectric substrate 202 by insulating material such as glass, resin etc.Dielectric substrate 202 is as insulating component.The thickness of dielectric substrate 202 can be for arbitrarily.Yet, as described below, owing to being biased, preferably form dielectric substrate 202 thin as much as possible when semiconductor device current potential when operating, dielectric substrate 202 has sufficient thickness to guarantee the insulation between semiconductor layer 201 and the lead frame 203 simultaneously.The biasing of current potential is depended on the material of dielectric substrate 202 and is changed, more specifically, depends on the permittivity of dielectric substrate 202.Can determine the preferred thickness of dielectric substrate 202 according to the material of dielectric substrate 202.
As shown in Figure 16 and 17, with lead frame be arranged on low and high potential circuit block LV, HV below so that respectively with low relative with high potential circuit block LV, HV.As shown in Figure 16, lead frame 203 has the first lead frame 203a as the first conductive member 203a, and it is corresponding to low potential reference circuit parts LV.Lead frame 203 also has the second lead frame 203b as second conductive member, and it is corresponding to high potential reference circuit parts HV.The first lead frame 203a is from forming parts LS trench isolations member 205 disconnected from each other forms parts LS towards the level moving meter inboard extended distance L1 with low potential reference circuit parts LV and level moving meter.The second lead frame 203b is from forming parts LS trench isolations member 205 disconnected from each other forms parts LS towards the level moving meter inboard extended distance L2 with high potential reference circuit parts HV and level moving meter.
Consider the sprocket bit in-migration designed distance L1 and the L2 that can in making semiconductor device, take place.Distance L 1 is designed to equal distance L 2 basically.More specifically, in the mill, in semiconductor layer 201, behind each element of formation, can locate and adhere to dielectric substrate 202 and lead frame 203.In above-mentioned technology, can locate displacement.On the basis of the estimation of location displacement that may be maximum, each distance L 1, L2 are made as may maximum value.When the location displacement takes place in making semiconductor device, can be at the identical direction superior displacement first and second lead frame 203a, 203b.In above-mentioned situation, though distance L 1 needn't equal distance L 2, owing to consider sprocket bit in-migration designed distance L1 and L2 that possibility is maximum, low potential reference circuit parts LV and level moved the outside that forms parts LS trench isolations member 205 disconnected from each other so the end of the first lead frame 203a on high potential reference circuit parts HV side can not be positioned at.In addition, the end of the second lead frame 203b on low potential reference circuit parts LV side can not be positioned at high potential reference circuit parts HV and level are moved the outside that forms parts LS trench isolations member 205 disconnected from each other.
With the first lead frame 203a be electrically connected to the line (not shown) that it applies the reference potential of low potential reference circuit parts LV by bonding line 204.With the second lead frame 203b be electrically connected to the line (not shown) that it applies the reference potential of high potential reference circuit parts LV by bonding line 204.
In above-mentioned semiconductor device, the first lead frame 203a is arranged to corresponding with low potential reference circuit parts LV, and the second lead frame 203b is arranged to corresponding with high potential reference circuit parts HV.Therefore, dielectric substrate 202 is clipped in the part below the low potential reference circuit parts LV between two elements with same potential, and these two elements are the low potential reference circuit parts LV and the first lead frame 203a.Dielectric substrate 202 is clipped at the another part below the high potential reference circuit parts HV between two elements with same potential, and these two elements are the high potential reference circuit parts HV and the second lead frame 203b.
Therefore can eliminate the potential difference between the two ends of the capacitor parasitics in the semiconductor device substantially.It can eliminate parasitic capacitance.Therefore can limit by the dv/dt surge and cause and parasitic capacitance is charged and the generation of the displacement current that discharges.Can the restricting circuits fault.
When semiconductor device had above-mentioned structure, appearance potential was poor between height and low potential reference circuit parts HV, the LV, thereby produced electric field in the part of the dielectric substrate 202 between height and low potential reference circuit parts HV, LV.Figure 18 illustrates the schematic diagram that the equipotential lines in the dielectric substrate 202 of semiconductor device distributes.As shown in Figure 18, the whole equipotential liness in the dielectric substrate 202 are not arranged in parallel between height and low potential reference circuit parts HV, the LV.In dielectric substrate 202, current potential is biased to more near high potential reference circuit HV or low potential reference circuit LV.Above-mentioned current potential biasing meeting is at high potential reference circuit parts HV and have between the part of bias potential, and also at low potential reference circuit parts LV with have between another part of bias potential and form parasitic capacitance, this can produce displacement current.
The thickness and the permittivity of dielectric substrate 202 depended in the biasing of current potential.More specifically, the biasing of current potential has big more thickness or big more permittivity along with dielectric substrate 202 and becomes big more.Because the material of dielectric substrate 202 is determined the permittivity of dielectric substrate 202 uniquely, the material of dielectric substrate is selected the permittivity of decision dielectric substrate 202.Yet the thickness of dielectric substrate 202 is can be according to design and the parameter of appropriate change.Therefore aspect effective inhibition of displacement current, the dielectric substrate 202 with little thickness may be favourable.
(the 7th embodiment)
The semiconductor device of present embodiment comprises with the semiconductor device difference of the 6th embodiment: be used to provide between low potential reference circuit parts LV and the first lead frame 203a be electrically connected and high potential reference circuit parts HV and the second lead frame 203b between the structure that is electrically connected.
Figure 19 is the sectional view that the semiconductor device (being HVIC) according to present embodiment is shown.As shown in Figure 19, through electrode 230 is arranged in dielectric substrate 202 and lays respectively at the below of high and low potential reference circuit parts HV, LV.More specifically, groove 231 is formed in the dielectric substrate 202 so that extend to lead frame 203 from semiconductor layer 201.The through electrode 230 that utilization is made by electric conducting material (for example, aluminium) comes filling groove 231.
By through electrode 230, the first lead frame 203a is electrically connected with the part of low potential reference circuit parts LV, wherein apply reference potential to this part.In addition,, the second lead frame 203b is electrically connected with the part of high potential reference circuit parts HV, wherein applies reference potential to this part by another through electrode 230.Semiconductor device basic identical with the advantage of semiconductor device of above-mentioned structure and the 6th embodiment.
(the 8th embodiment)
The semiconductor device of present embodiment uses the substrate with conductive pattern, replaces the lead frame 203 of the semiconductor device of the 6th embodiment.
Figure 20 is the sectional view that the semiconductor device (being HVIC) according to present embodiment is shown.As shown in Figure 20, use has the substrate 241 replacement lead-frame 203 of conductive pattern 240 and it is arranged on the rear surface side of dielectric substrate 202.Conductive pattern 240 can be used as conductive member.Conductive pattern 240 is used for the applying of reference potential and applying of the reference potential of high potential reference circuit parts HV of low potential reference circuit parts LV.
As shown in Figure 20, conductive pattern 240 comprises as the conductive pattern 240a of first conductive member with as the second conductive pattern 240b of second conductive member.The first conductive pattern 240a is positioned at the below of the part of the dielectric substrate 202 corresponding with low potential reference circuit parts LV.The second conductive pattern 240b is positioned at the below of another part of the dielectric substrate 202 corresponding with high potential reference circuit parts HV.The first conductive pattern 240a corresponding with low potential reference circuit parts LV is designed to, forms the inboard extended distance L1 of parts LS from the trench isolations member 205 that low potential reference circuit parts LV is separated with level moving meter formation parts LS towards the level moving meter.The second conductive pattern 240b corresponding with high potential reference circuit parts HV is designed to, forms the inboard extended distance L2 of parts LS from the trench isolations member 205 that high potential reference circuit parts HV is separated with level moving meter formation parts LS towards the level moving meter.
The reason that distance L 1, L2 be provided in the present embodiment and advantage be identical with the 6th embodiment basically.Even the location displacement takes place, prevent that also the end of the first conductive pattern 240a on the level moving meter formation parts LS side is positioned at the outside of the trench isolations member 205 that low potential reference circuit parts LV is separated with level moving meter formation parts LS in connecting conductive pattern 240 and substrate 241.In addition, put the outside that the end that ends the second conductive pattern 240b on the level moving meter formation parts LS side is positioned at the trench isolations member 205 that high potential reference circuit parts LV is separated with level moving meter formation parts LS.
Use conductive pattern 240 to replace basic identical among the advantage of lead frames 203 and the 6th embodiment in the present embodiment.
In the superincumbent description, set forth wherein the situation of semiconductor device that the structure applications of present embodiment is provided the 7th embodiment of electrical connection to through electrode 230 wherein.Perhaps, the structure according to present embodiment can be applied to the semiconductor device that the 6th embodiment of electrical connection is provided according to bonding line 204 wherein.More specifically, by bonding line 204, the first conductive pattern 240a can be electrically connected with the line of reference voltage apply low potential reference circuit parts LV to it in.Equally, by bonding line 204, the second conductive pattern 240b can be electrically connected with the line of reference voltage apply high potential reference circuit parts HV to it in.
(the 9th embodiment)
The semiconductor device of present embodiment uses dielectric film to replace the dielectric substrate 202 of the semiconductor device of the 6th embodiment as insulating component.
Figure 21 is the sectional view that the semiconductor device (being HVIC) according to present embodiment is shown.As shown in Figure 21, semiconductor device uses dielectric film 250 to replace dielectric substrate 202.Dielectric film 250 can be used as insulating component.For example, provide dielectric film 250 by the buried oxide layer in the SOI substrate, this SOI substrate also has soi layer and the support substrates that semiconductor layer 201 is provided.By buried oxide layer, soi layer is bonded to support substrates.Before adhering to lead frame 203, grind and remove support substrates.By said method, the semiconductor device of present embodiment can have above-mentioned structure.
Use dielectric film 250 to replace the semiconductor device of dielectric substrate 202 to have and the essentially identical advantage of the semiconductor device of the 6th embodiment.As mentioned above, the thickness of dielectric substrate 202 is more little, can more effectively suppress because the displacement current that the current potential biasing causes.Therefore, the use of dielectric film 250 more effectively suppresses displacement current.Can more effectively limit current failure.
(the tenth embodiment)
The semiconductor device of present embodiment comprises the substrate 241 with conductive pattern similar to the semiconductor device of the 8th embodiment 240.In the present embodiment, use the encapsulating resin member to replace dielectric substrate 202 as insulating component.
Figure 22 is the sectional view that the semiconductor device (being HVIC) according to present embodiment is shown.Similar to the 8th embodiment, in semiconductor layer 201, form different element (not shown)s, form parts LS element is provided to move to low and high potential circuit block LV, HV and level.Utilize encapsulating resin member 260 encapsulating semiconductor layers 201 as insulating component.By bonding line 262, an end of the lead frame in the encapsulating resin member 260 261 is electrically connected to the line that applies the reference potential of low potential reference circuit parts LV to it.By another bonding line 262, the other end of the lead frame in the encapsulating resin member 260 261 is electrically connected to the line that applies the reference potential of high potential reference circuit parts HV to it.
In said method, encapsulating resin member 260 can be used as insulating component.Therefore, when conductive pattern 240 is provided with semiconductor layer 201 on the contrary with respect to the part of encapsulating resin member 260, the semiconductor device of the advantage of the semiconductor device of present embodiment and the 6th embodiment basic identical.
Perhaps, semiconductor device can be for like this, and promptly substrate 241 is a mounting panel, for example is the printed circuit board (PCB) that has as the wiring pattern of the lip-deep first and second conductive pattern 240a of plate, 240b.
(the 11 embodiment)
The semiconductor device of present embodiment uses ceramic packaging to replace the encapsulating resin member 260 of the semiconductor device of the tenth embodiment as insulating component.
Figure 23 is the sectional view that the semiconductor device (being HVIC) according to present embodiment is shown.As shown in Figure 23, use ceramic packaging 270 to replace encapsulating resin member 260.Ceramic packaging 270 can and have sunk part 270a in its surface as insulating component.Semiconductor layer 201 is installed in the sunk part 270a.One end of lead frame 261 is exposed within the sunk part 270a.Be electrically connected with an end of lead frame 261 by the predetermined portions of bonding line 262 semiconductor layer 201.
When ceramic packaging 270 is used as insulating component, can be with semiconductor layer 201 with respect to ceramic packaging 270 and conductive pattern 240 opposite settings.The semiconductor device of the advantage of the semiconductor device of present embodiment and the 6th embodiment basic identical.
(modification of the 6th to the 11 embodiment)
In the 6th to the 9th embodiment, present the exemplary elements that is used for low potential reference circuit parts LV, high potential reference circuit parts HV and level moving meter formation parts LS.Perhaps, each of parts LV, HV, LS can comprise and is different from above-mentioned exemplary elements or the element except that above-mentioned exemplary elements.In addition, perhaps, semiconductor device can have different low potential reference circuit parts LV, high potential reference circuit parts HV and level moves the layout that forms parts LS.
In the the the 6th to the 8th, the tenth and the 11 embodiment, do not provide semiconductor layer 201, but provide semiconductor layer 201 by the epitaxial substrate of using big block substrate or form by the epitaxial growth of silicon layer on big block substrate by use SOI substrate.Perhaps, in the the the 6th to the 8th, the tenth and the 11 embodiment, can provide semiconductor layer 201 by using the SOI substrate.In the 9th embodiment, provide semiconductor layer 201 by using the SOI substrate.Perhaps, in the 9th embodiment, can use big block substrate or epitaxial substrate that semiconductor layer 201 is provided, and in addition, can on the rear surface of the semiconductor layer 201 that uses big block substrate or epitaxial substrate to provide, form dielectric film 250.
In the above-described embodiments, the insulating component for dielectric substrate 202, dielectric film 250 etc. is positioned on the whole rear surface of semiconductor layer 201.Perhaps, insulating component is positioned on the part of rear surface of the semiconductor layer 201 that corresponds respectively to low and high potential reference circuit parts LV, HV.
In the tenth embodiment, encapsulating resin member 260 is as insulating component, and the part of encapsulating resin member 260 be positioned at semiconductor layer 201 above.In said structure, there be the possibility of encapsulating resin member 260 as capacitor parasitics.Preferably conductive member 280 is arranged on the encapsulating resin member 260, as shown in Figure 24.
According to first kind of aspect disclosed by the invention, provide a kind of semiconductor device.This semiconductor device comprises SOI substrate 104, buried insulation film 103 and the support substrates 102 with active layer 101.By buried insulation film 103 active layer 101 and support substrates 102 are bonded together.This semiconductor device also comprises and is arranged in active layer 101 and exercisable low potential reference circuit parts LV under first reference potential.This semiconductor device also comprises and is arranged in active layer 101 and exercisable high potential reference circuit parts HV under second reference potential more than or equal to first reference potential.This semiconductor device also comprises in active layer 101 and has and is used for providing between first reference potential and second reference potential level moving meter of the level moving meter 120 that level moves to form parts LS.This semiconductor device also comprises the first that makes support substrates 102 and the insulating component 130 of second portion mutual insulating.The position of first is corresponding to low potential reference circuit parts LV, and the position of second portion is corresponding to high potential reference circuit parts HV.
According to above-mentioned structure, insulating component 130 makes first and second SI semi-insulations of support substrates 102.First is positioned at the position corresponding to low potential reference circuit parts LV.Second portion is positioned at the position corresponding to high potential reference circuit parts HV.Therefore, can limit the part of low potential reference circuit parts LV below and the current potential between the another part below the high potential reference circuit parts HV propagates.Therefore can suppress parasitic capacitance is charged and the generation of the displacement current that discharges.The incorrect operation of its restricting circuits.
Can construct above-mentioned semiconductor device like this, make, perhaps, make insulating component 130 by air or vacuum by resin.
Can construct above-mentioned semiconductor device like this, make: high potential reference circuit parts HV has the second area that applies second reference potential to it; And the second portion of support substrates 102 is electrically connected with the second area of high potential reference circuit parts HV.
According to above-mentioned structure, the second portion of high potential reference circuit parts HV and support substrates 102 can have essentially identical current potential.That is, the both sides of buried insulation film 103 can have essentially identical current potential.The more effectively generation of limiting displacement electric current.
Can so construct above-mentioned semiconductor device, make: low potential reference circuit parts LV has the first area that applies first reference potential to it; And the first of support substrates 102 is electrically connected with the first area of low potential reference circuit parts LV.
According to above-mentioned structure, the first of low potential reference circuit parts LV and support substrates 102 can have essentially identical current potential.The more effectively generation of limiting displacement electric current.
Can so construct semiconductor device, make: the level moving meter forms parts LS between low potential reference circuit parts LV and high potential reference circuit parts HV; And active layer 101 has the channel insulation member 105 that surrounds low potential reference circuit parts LV, high potential reference circuit parts HV and level moving meter formation parts LS.This semiconductor device also comprises: be arranged in active layer 101 and be positioned at the element outside parts 150 of channel insulation member 105 outsides.Support substrates 102 can also have third part, and its position is corresponding to element outside parts 150.
According to above-mentioned structure, because the existence of the third part of support substrates 102, can strengthen the intensity of the housing of semiconductor device.
Can so construct above-mentioned semiconductor device, make the first of integrated support substrates 102 and the third part of support substrates 102, described first is positioned at the position corresponding to low potential reference circuit parts LV, and described third part is positioned at the position corresponding to element outside parts 150.
Can so construct above-mentioned semiconductor device, make the first of support substrates 102 be electrically connected mutually with the third part of support substrates 102, described first is positioned at the position corresponding to low potential reference circuit parts LV, the described the 3rd that part of position that is positioned at corresponding to element outside parts 150.Can so construct above-mentioned semiconductor device, make that second reference potential is variable.
According to second kind of aspect disclosed by the invention, provide a kind of semiconductor device.This semiconductor device comprises the semiconductor layer 201 with front surface and rear surface.This semiconductor layer 201 comprises: exercisable low potential reference circuit parts LV under first reference potential; Exercisable high potential reference circuit parts HV under second reference potential more than or equal to first reference potential; And have and be used between first and second reference potentials, providing the level moving meter of the level moving meter 220 that level moves to form parts SV.This semiconductor device also comprises: insulating component 202,250,260,270 is positioned at respectively on first and second parts with the rear surface of low and the semiconductor layer 201 that high potential reference circuit parts LV, HV are corresponding; The first conductive member 203a, 240a, it is provided with on the contrary with respect to insulating component 202,250,260,270 and low potential reference circuit parts LV, and be electrically connected with the first area of low potential reference circuit parts LV, wherein first reference potential be applied to the first area; And the second conductive member 203b, 240b, it is provided with on the contrary with respect to insulating component 202,250,260,270 and high potential reference circuit parts HV, and be electrically connected with the second area of high potential reference circuit parts HV, wherein second reference potential be applied to second area.
According to above-mentioned semiconductor device, the first conductive member 203a, 240a and the second conductive member 203b, 240b are so arranged, so that respectively corresponding to low potential reference circuit parts LV and high potential reference circuit parts HV.Therefore, insulating component 202,250,260,270 has in the part below the low potential reference circuit parts LV between two elements of same potential, and these two elements are low potential reference circuit parts LV and the first conductive member 203a, 240a.Insulating component 202 has at the another part below the high potential reference circuit parts HV between two elements of same potential, and these two elements are high potential reference circuit parts HV and the second conductive member 203b, 240b.
Therefore can eliminate the potential difference between the two ends that are formed on the capacitor parasitics in the semiconductor device basically.Can eliminate parasitic capacitance.Therefore can limit cause by the dV/dt surge and parasitic capacitance charged and the generation of the displacement current that discharges.It can prevent fault.
Above-mentioned semiconductor device also comprises the bonding line 204,262 with first bonding line and second bonding line.First bonding line is electrically connected to the first conductive member 203a, 240a the first area of low potential reference circuit parts LV.Second bonding line is electrically connected to the second conductive member 203b, 240b the second area of high potential reference circuit parts HV.
Can so construct above-mentioned semiconductor device, make: insulating component 202,250,260,270 has first groove and is embedded in first through electrode 230 in first groove; First through electrode 230 is electrically connected to the first conductive member 203a, 240a the first area of low potential reference circuit parts LV; Insulating component 202,250,260,270 also has second groove and is embedded in second through electrode 230 in second groove; And second through electrode 230 is electrically connected to the second conductive member 203b, 240b the second area of high potential reference circuit parts HV.
Above-mentioned semiconductor device can also comprise lead frame (203), and this lead frame (203) is used for hanging down and is connected with the external electric of high potential reference circuit parts (LV, HV).Lead frame (203) comprises first and second conductive members (203a, 240a, 203b, 240b).
Above-mentioned semiconductor device can also comprise the substrate (241) that is provided with on the contrary with respect to insulating component (202,250,260,270) and semiconductor layer (201), and this substrate 241 has first conductive pattern (240a) and second conductive pattern (240b).First and second conductive patterns (240a, 240b) comprise first and second conductive members (203a, 240a, 203b, 240b) respectively.
Above-mentioned semiconductor device can also comprise encapsulating resin member 260, this encapsulating resin member 260 encapsulating semiconductor layers 201 and comprise insulating component 202,250,260,270.Above-mentioned semiconductor device can also comprise first lead frame 261 and second lead frame 261.First end of first lead frame 261 can be positioned at encapsulating resin member 260, and is electrically connected with the first area of low potential reference circuit parts LV.Second end of first lead frame 261 can be electrically connected with the first conductive pattern 240a of substrate 241.First end of second lead frame 261 is positioned at encapsulating resin member 260, and is electrically connected with the second area of high potential reference circuit parts HV.Second end of second lead frame 261 is electrically connected with the second conductive pattern 240b of substrate 241.
Can so construct above-mentioned semiconductor device, make insulating component 202,250,260,270 comprise in the ceramic packaging 270 that semiconductor layer 201 is installed thereon.Above-mentioned semiconductor device can also comprise first lead frame 261 and second lead frame 261.Ceramic packaging 270 can have the sunk part that semiconductor layer 201 is installed within it.One end of first lead frame 261 can highlight from the sunk part of ceramic packaging 270, and is electrically connected with the first area of low potential reference circuit parts LV.The other end of first lead frame 261 can highlight from ceramic packaging 270, and is electrically connected with the first conductive pattern 240a of substrate 241.One end of second lead frame 261 can highlight from the sunk part of ceramic packaging 270, and is electrically connected with the second area of high potential reference circuit parts HV.The other end of second lead frame 261 can highlight from ceramic packaging 270, and is electrically connected with the second conductive pattern 240b of substrate 241.
Can so construct above-mentioned semiconductor device, making provides insulating component 202,250,260,270 by one of them of dielectric substrate 202 and dielectric film 250.Can so construct above-mentioned semiconductor device, make that second reference potential is variable.
Though described the present invention with reference to its various embodiments above, should be appreciated that the present invention is not subjected to the restriction of the foregoing description and explanation.The present invention is intended to the layout that covers multiple modification and be equal to.In addition, though imagine above-mentioned multiple combination and structure embodies the present invention, also imagine comprise more, still less or only other combination and the structure of discrete component fall within the scope of the present invention.
Claims (22)
1, a kind of semiconductor device comprises:
SOI substrate (104), it comprises active layer (101), support substrates (102) and buried insulation film (103), wherein by described active layer of described buried insulation film (103) bonding (101) and described support substrates (102);
Low potential reference circuit parts (LV), it is arranged in described active layer (101), and can operate under first reference potential;
High potential reference circuit parts (HV), it is arranged in described active layer (101), and can operate under second reference potential more than or equal to described first reference potential;
The level moving meter forms parts (LS), and it is arranged in described active layer (101), and the level moving meter (120) that provides level to move between described first reference potential and described second reference potential is provided; And
Insulating component (130), it makes the first and the second portion of described support substrates (102) insulated from each other, the position of wherein said first is corresponding to described low potential reference circuit parts (LV), and the position of wherein said second portion is corresponding to described high potential reference circuit parts (HV).
2, semiconductor device according to claim 1, wherein
Be formed from a resin described insulating component (130).
3, semiconductor device according to claim 1, wherein
Described insulating component (130) is an air.
4, semiconductor device according to claim 1, wherein
Described insulating component (130) is a vacuum.
5, semiconductor device according to claim 1, wherein
Described high potential reference circuit parts (HV) have second area, and described second reference potential is applied to this second area; And
The second portion of described support substrates (102) is electrically connected with the second area of described high potential reference circuit parts (HV).
6, semiconductor device according to claim 1, wherein:
Described low potential reference circuit parts (LV) have the first area, and described first reference potential is applied to this first area; And
The first of described support substrates (102) is electrically connected with the first area of described low potential reference circuit parts (LV).
7, semiconductor device according to claim 1, wherein:
Described level moving meter forms parts (LS) and is positioned between described low potential reference circuit parts (LV) and the described high potential reference circuit parts (HV); And
Described active layer (101) has: channel insulation member (105), and this channel insulation member (105) surrounds described low potential reference circuit parts (LV), described high potential reference circuit parts (HV) and described level moving meter and forms parts (LS);
Semiconductor device according to claim 1 also comprises:
Element outside parts (150), it is arranged in described active layer (101), and be positioned at outside the described channel insulation member (105), wherein said support substrates (102) also has third part, and the position of wherein said third part is corresponding to described element outside parts (150).
8, semiconductor device according to claim 7, wherein:
The described first and the described third part of described support substrates (102) integrate.
9, semiconductor device according to claim 7, wherein:
The described first and the described third part of described support substrates (102) are electrically connected to each other.
10, according to any described semiconductor device in the claim 1 to 9, wherein:
Described second reference potential is variable.
11, a kind of semiconductor device comprises:
Have the semiconductor layer (201) of front surface and rear surface, this semiconductor layer (201) comprising:
Low potential reference circuit parts (LV), it can be operated under first reference potential;
High potential reference circuit parts (HV), it can be operated under second reference potential more than or equal to described first reference potential; And
The level moving meter forms parts (LS), and level moving meter (220) that provides level to move between described first and second reference potentials is provided for it;
Insulating component (202,250,260,270), it is positioned in the first and second portion of rear surface of described semiconductor layer (201), and this first and second part corresponds respectively to described low and high potential reference circuit parts (LV, HV);
First conductive member (203a, 240a), it is provided with on the contrary with respect to described insulating component (202,250,260,270) and described low potential reference circuit parts (LV), and be electrically connected with the first area of described low potential reference circuit parts (LV), wherein apply described first reference potential to described first area; And
Second conductive member (203b, 240b), it is provided with on the contrary with respect to described insulating component (202,250,260,270) and described high potential reference circuit parts (HV), and be electrically connected with the second area of described high potential reference circuit parts (HV), wherein apply described second reference potential to described second area.
12, semiconductor device according to claim 11 also comprises:
Bonding line (204), it has first bonding line and second bonding line, wherein:
Described first bonding line is electrically connected to described first conductive member (203a, 240a) the described first area of described low potential reference circuit parts (LV); And
Described second bonding line is electrically connected to described second conductive member (203b, 240b) the described second area of described high potential reference circuit parts (HV).
13, semiconductor device according to claim 11, wherein:
Described insulating component (202,250,260,270) has first groove (231) and is embedded in first through electrode (230) in described first groove (231);
Described first through electrode (230) is electrically connected to described first conductive member (203a, 240a) the described first area of described low potential reference circuit parts (LV);
Described insulating component (202,250,260,270) also has second groove (231) and is embedded in second through electrode (230) in described second groove (231); And
Described second through electrode (230) is electrically connected to described second conductive member (203b, 240b) the described second area of described high potential reference circuit parts (HV).
14, semiconductor device according to claim 11 also comprises:
Lead frame (203) with first lead frame (203a) and second lead frame (203b), wherein
Described first conductive member (203a, 240a) is first lead frame (203a) that is used for the external electric connection of described low potential reference circuit parts (LV); And
Described second conductive member (203b, 240b) is second lead frame (203b) that is used for the external electric connection of described high potential reference circuit parts (HV).
15, semiconductor device according to claim 11 also comprises:
Substrate (241), it is provided with on the contrary with respect to described insulating component (202,250,260,270) and described semiconductor layer (201), and has first conductive pattern (240a) and second conductive pattern (240b), wherein:
Described first conductive member (203a, 240a) is described first conductive pattern (240a); And
Described second conductive member (203b, 240b) is described second conductive pattern (240b).
16, semiconductor device according to claim 15, wherein:
Described insulating component (202,250,260,270) is an encapsulating resin member (260) of sealing described semiconductor layer (201).
17, semiconductor device according to claim 16 also comprises:
First and second lead frames (261), wherein:
First end of described first lead frame (261) is positioned within the described encapsulating resin member (260), and is electrically connected with the described first area of described low potential reference circuit parts (LV);
Second end of described first lead frame (261) is electrically connected with described first conductive pattern (240a) of described substrate (241);
First end of described second lead frame (261) is positioned within the described encapsulating resin member (260), and is electrically connected with the described second area of described high potential reference circuit parts (HV); And
Second end of described second lead frame (261) is electrically connected with described second conductive pattern (240b) of described substrate (241).
18, semiconductor device according to claim 15, wherein:
Described insulating component (202,250,260,270) is ceramic packaging (270), and described semiconductor layer (201) is installed on this ceramic packaging (270).
19, semiconductor device according to claim 18 also comprises:
First and second lead frames (261), wherein:
Described ceramic packaging (270) has sunk part (270a), and described semiconductor layer (201) is installed in this sunk part (270a);
One end of described first lead frame (261) highlights from the described sunk part (270a) of described ceramic packaging (270), and is electrically connected with the described first area of described low potential reference circuit parts (LV);
The other end of described first lead frame (261) highlights from described ceramic packaging (270), and is electrically connected with described first conductive pattern (240a);
One end of described second lead frame (261) highlights from the described sunk part (270a) of described ceramic packaging (270), and is electrically connected with the described second area of described high potential reference circuit parts (HV); And
The other end of described second lead frame (261) highlights from described ceramic packaging (270), and is electrically connected with described second conductive pattern (240b).
20, semiconductor device according to claim 11, wherein
Described insulating component (202,250,260,270) is one of them of dielectric substrate (202) and dielectric film (250).
21, according to any described semiconductor device in the claim 11 to 20, wherein
Described second reference potential is variable.
22, semiconductor device according to claim 5, wherein
Described low potential reference circuit parts have the first area, and described first reference potential is applied to this first area; And
The described first of described support substrates is electrically connected with the described first area of described low potential reference circuit parts.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007323064A JP4438859B2 (en) | 2007-12-14 | 2007-12-14 | Semiconductor device |
| JP323064/2007 | 2007-12-14 | ||
| JP112483/2008 | 2008-04-23 | ||
| JP2008112483A JP4479823B2 (en) | 2008-04-23 | 2008-04-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101459182A true CN101459182A (en) | 2009-06-17 |
| CN101459182B CN101459182B (en) | 2010-10-20 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101843998A Expired - Fee Related CN101459182B (en) | 2007-12-14 | 2008-12-12 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP4438859B2 (en) |
| CN (1) | CN101459182B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237357A (en) * | 2010-04-23 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Integrated circuit apparatus and manufacturing method thereof |
| CN106104770A (en) * | 2014-03-12 | 2016-11-09 | 株式会社晶磁电子日本 | Stacked semiconductor IC apparatus |
| CN110690202A (en) * | 2019-10-09 | 2020-01-14 | 长江存储科技有限责任公司 | Integrated circuit device and method of making the same |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5401845B2 (en) * | 2008-06-25 | 2014-01-29 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| JP2011096862A (en) * | 2009-10-30 | 2011-05-12 | Hitachi Ltd | Semiconductor device and method of manufacturing the same |
| CN102110605B (en) * | 2009-12-24 | 2012-06-06 | 北大方正集团有限公司 | Method and device for manufacturing insulated gate bipolar transistor (IGBT) chip |
| JP5479227B2 (en) * | 2010-05-28 | 2014-04-23 | 株式会社東芝 | Semiconductor device |
| JP5724934B2 (en) | 2011-07-05 | 2015-05-27 | 株式会社デンソー | Semiconductor device |
-
2007
- 2007-12-14 JP JP2007323064A patent/JP4438859B2/en not_active Expired - Fee Related
-
2008
- 2008-12-12 CN CN2008101843998A patent/CN101459182B/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237357A (en) * | 2010-04-23 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Integrated circuit apparatus and manufacturing method thereof |
| CN106104770A (en) * | 2014-03-12 | 2016-11-09 | 株式会社晶磁电子日本 | Stacked semiconductor IC apparatus |
| CN106104770B (en) * | 2014-03-12 | 2019-02-15 | 株式会社晶磁电子日本 | Stacked semiconductor IC apparatus |
| CN110690202A (en) * | 2019-10-09 | 2020-01-14 | 长江存储科技有限责任公司 | Integrated circuit device and method of making the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4438859B2 (en) | 2010-03-24 |
| JP2009147119A (en) | 2009-07-02 |
| CN101459182B (en) | 2010-10-20 |
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