CN100517608C - 非晶电介质薄膜及其制造方法 - Google Patents
非晶电介质薄膜及其制造方法 Download PDFInfo
- Publication number
- CN100517608C CN100517608C CNB2004100832521A CN200410083252A CN100517608C CN 100517608 C CN100517608 C CN 100517608C CN B2004100832521 A CNB2004100832521 A CN B2004100832521A CN 200410083252 A CN200410083252 A CN 200410083252A CN 100517608 C CN100517608 C CN 100517608C
- Authority
- CN
- China
- Prior art keywords
- thin film
- film
- dielectric
- dielectric thin
- amorphous dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000010409 thin film Substances 0.000 title claims description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 229910052797 bismuth Inorganic materials 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 57
- 238000000034 method Methods 0.000 claims description 15
- 239000004744 fabric Substances 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000002243 precursor Substances 0.000 claims description 4
- 239000010936 titanium Substances 0.000 abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 21
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910003077 Ti−O Inorganic materials 0.000 description 4
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 238000011160 research Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 229910052788 barium Inorganic materials 0.000 description 3
- 239000002178 crystalline material Substances 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 229910052712 strontium Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910018557 Si O Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- -1 Ba and Sr Chemical class 0.000 description 1
- 229910052784 alkaline earth metal Inorganic materials 0.000 description 1
- 150000001342 alkaline earth metals Chemical class 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910052747 lanthanoid Inorganic materials 0.000 description 1
- 150000002602 lanthanoids Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000021715 photosynthesis, light harvesting Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
- H01L21/02153—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing titanium, e.g. TiSiOx
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
- H01L21/02156—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing at least one rare earth element, e.g. silicate of lanthanides, scandium or yttrium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12535—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.] with additional, spatially distinct nonmetal component
- Y10T428/12597—Noncrystalline silica or noncrystalline plural-oxide component [e.g., glass, etc.]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12535—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.] with additional, spatially distinct nonmetal component
- Y10T428/12611—Oxide-containing component
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Mechanical Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Memories (AREA)
- Formation Of Insulating Films (AREA)
- Inorganic Insulating Materials (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
一种用在半导体器件中的非晶电介质薄膜和制造该非晶电介质薄膜的方法。该非晶电介质薄膜包括用作诸如DRAM器件中电容器的电介质材料的Bi、Ti、Si和O，并具有60或更高的介电常数。这样的BTSO基薄膜即使在其厚度已经减小时也能防止泄露电流的增加，因此允许半导体器件被高度集成。
Description
技术领域
本发明涉及一种用作高度集成存储器件的电容器的非晶电介质薄膜(amorphpus dielectric thin film)及其制造方法，更具体地，涉及一种使用具有非晶微观结构的基于Bi-Ti-Si-O(BTSO)的材料作为存储器件的电容器的非晶电介质薄膜，及其制造方法。
背景技术
按照摩尔定律，动态随机存取存储器(DRAM)，即高度集成的存储器件，的存储密度每三年几乎翻两番，同时设计规则持续地降低。因此，每个单元所占据的平面空间持续减小。特别地，在DRAM由单个晶体管和单个电容器构成的情况下，电容器的平面空间不可避免的被减小，反过来减小了电容器的平面尺寸，因此通过公式1说明的关系降低了电容器的电容C，公式1如下：
(此处ε表示介电常数，A表示有效面积，t表示电介质膜的厚度)。
因此，尽管器件的特征尺寸持续减小，但是应当保持DRAM器件工作所需的电容(＞25fF/cell)。因此，一直进行致力于降低电介质膜厚度和增加电介质膜有效面积的研究。近来，人们在使用具有高介电常数(高K)的高电介质氧化物层代替用于形成传统的电介质膜的诸如SiO2的材料方面做出了相当多的努力。
在半导体工业中，在栅极氧化物层和DRAM电容器的电介质膜中采用了高电介质薄膜(high dielectric thin film)。在栅极氧化物层的情况中，目前的研究方向是基于Hf或Zr的氧化物层和例如镧系元素的三价金属氧化物层。通常，由于能带较窄，所以高电介质栅极氧化物层具有大泄露电流(leakage current)以及在接合到硅表面期间的高温下热稳定性下降的问题。因此，通过添加具有良好热稳定性和宽能带的SiO2或AL2O3来进行弥补电介质膜缺陷的研究(参考Journal of Applied Physics，87，484(2000)；Appl.Phys.Lett.80，3385(2002)；Appl.Phys.Lett.81，1071(2002))。
但是，由于通过高电介质材料与SiO2或AL2O3的混合形成的膜具有非晶微观结构和明显较低的介电常数的问题，所以使用非晶结构混合物作为电容器电介质材料并不具有吸引力。例如，当薄膜变到具有非晶微观结构时，在具有钙钛矿结构的晶体薄膜中已知为250或更高的(Ba，Sr)TiO3薄膜(BST)的介电常数下降至大约25。
为了能够被用作吉比特级别DRAM的电容器电介质材料，薄膜的物理厚度应当小于15nm，并且等效的氧化物层厚度大约小于1nm。因此，实际是不可能使用非晶电介质薄膜的。因此，关于电容器电介质膜的研究集中在晶体的高电介质薄膜上，该薄膜具有一个问题，即一旦薄膜厚度减小到约15nm，通过晶粒边界的泄露电流就增大。
另一方面，在制造三维电容器期间的三维地构成的图形的情况下，当采用例如BST的多原子电介质材料时出现的严重问题是很难用一致的成分(consistent composition)沉积薄膜。这是因为诸如Ba和Sr的二价碱土金属具有小的电荷半径比(charge-to radius ratio)，其导致了不稳定的前体结构(precursor structure)和不充足的汽压。
发明内容
本发明提供一种具有高介电常数的非晶材料，其在制造三维电容器期间能够获得一致的厚度和成分，当用作例如DRAM的半导体器件的电容器时不会产生泄露电流。
按照本发明的一个方面，提供一种用在半导体器件中的电介质膜，其中用在半导体器件中的非晶电介质薄膜包括Bi、Ti、Si和O。
优选地是通过化学式Bi1-x-yTixSiyOz来表示电介质膜，此处0.2＜x＜0.5，0＜y＜0.5，1.5＜z＜2。
按照本发明的另一个方面，提供一种制造用在半导体器件中的非晶电介质薄膜的方法，半导体器件包括底层结构、电介质膜和上电极。此时，通过在底层结构中包括Bi、Ti、Si和O形成该非晶电介质薄膜。
优选地，使用原子层沉积形成该非晶电介质薄膜。
附图说明
通过参照附图及详细说明典型的实施例，本发明上述和其它的特征及优点将显而易见，其中：
图1A是显示DRAM的电容器结构的视图，所述DRAM是半导体存储器件；
图1B是显示根据本发明的基于BTSO的电介质膜的样本的透射电子显微镜(TEM)照片，该电介质膜形成厚度约为12.9nm；
图2A示出用于解释按照本发明制造的图1B的基于BTSO的电介质膜的泄露电流特征的曲线图；
图2B是说明按照本发明的厚度约为9.6nm、12.9nm和14.2nm的电介质层的等价氧化物层的厚度的曲线图；
图2C是显示相对于图2B中等效氧化物层的厚度的介电常数的曲线图；以及
图3A和3B分别示出基于Bi-Ti-O的薄膜的横截面的TEM相片和按照位置标注的原子比的曲线图，该基于Bi-Ti-O的薄膜沉积在在硅衬底上由SiO2形成的孔形图案(hole pattern)中，该孔形图案具有大约为7的高宽比(aspect ratio)和根据位置绘图的原子比(graph plotting atomic ratioaccording to position)。
具体实施方式
以下将参照附图详细说明含有非晶电介质薄膜的半导体器件及其制造方法。
图1A给出了作为半导体存储器件的DRAM的电容器结构。在底层结构11上形成电介质膜12，在电介质膜12上形成上电极13。此处，本发明特征在于使用基于Bi(铋)-Ti(钛)-Si(硅)-O(氧化物)的材料作为电介质膜12。
没有定义上述材料的成分比，但优选以相同的比例形成Bi和Ti。关于Si，在Si与其它材料的比下降50％或更少时，其介电常数的值倾向于增加。然而，如果Si的比例过分的降低，非晶电介质薄膜12变成晶体薄膜，结晶化能够导致泄露电流。按照本发明的电介质膜12优选具有化学式Bi1-x-yTixSiyOz，(其中0.2＜x＜0.5，0＜y＜0.5，1.5＜z＜2)。
具有上述化学成分的BTSO基材料不是晶体材料而是非晶材料，因此，不会由薄膜形成导致通过晶粒边缘的泄露电流。此外，其具有不需要用于结晶化的单独退火工艺即可获得的大约60或更大的高介电常数。此外，虽然作为非晶电介质材料的BTSO薄膜是包括三价金属离子的多原子氧化物层，但由于BTSO薄膜具有小的离子半径、与3或更大的大原子价有关的好的前体挥发性和好的稳定性，所以对薄膜工艺是有利的。
此后将详细说明按照本发明的BTSO薄膜的制造方法的一个实施例。此处，Ru/SiO2/Si衬底被用作底层结构11，在其上形成电介质膜12。为了分析电介质膜12的特性，使用原子层沉积形成电介质膜12的三个样本，其厚度分别约为9.6nm、12.9nm和14.2nm。该样本具有4O％Bi、40％Ti和20％Si的金属组分。
为了形成按照本发明的电介质膜12，使用在低温下执行的原子层沉积。此处，使用Bi(mmp)3、Ti(mmp)4和Si(OEt)4作为形成薄膜的前体，O3作为反应气体，其中mmp表示1-甲氧基-2-甲基-2-丙氧化物，Et表示乙烷基。以非晶态形成电介质膜12，这不包括用于结晶化的退火工艺。可以采用制造电容器的传统技术。
图1B是厚度约为12.9nm的电介质膜12样本的TEM相片。参照图1B，能够确认底层结构的Ru层和作为本发明的电介质膜12的BSTO层。此处，电介质膜12是非晶态的。按照本发明形成的电介质膜12的密度相当高，大约在6.5-7.1g/cm3，是在X射线反射率(XRR)试验中测量的。
为了检验按照上述方法制造的电介质膜12的电气特性，测量泄露电流、击穿电压和介电常数。
图2A给示出了电介质膜12的泄露电流。参照图2A，与DRAM电容器的要求一样，在1V时电流密度小于10-7A/cm2，因此显示出极好的绝缘特性。直接涉及器件可靠性的电介质漏电强度是0.6至1.6MV/cm，因此显示出相对较好的绝缘特性。
图2B给出了按照本发明的厚度约为9.6nm、12.9nm和14.2nm的电介质层的等效氧化物层的厚度。参照图2B，物理厚度约为9.6nm的电介质膜12的样本具有厚度约为的等效氧化物层。物理厚度约为12.9nm和14.2nm的电介质膜12的另两个样本分别具有厚度约为
和
的等效氧化物层。
图2C是显示相对于图2B中等效氧化物层厚度的介电常数的曲线图。参照图2C，对于厚度约为9.6nm的电介质膜12的情况，介电常数约为64。厚度分别约为12.9nm和14.2nm的另两个样本分别具有55或更高的介电常数值，根据厚度稍有差别。获得的介电常数值明显大于非晶电介质薄膜的传统的已知值。具体地，非晶BST((Ba，Sr)TiO3)的传统已知的介电常数约为25，按照本发明的非晶BTSO薄膜的介电常数是其两倍多。
图3A和3B用于确认电介质膜12的厚度和组分的一致性，当多原子电介质膜被应用于复杂的三维器件中时，厚度和组分的一致性被视为传统的问题。此处，图3A和3B分别示出了基于Bi-Ti-O的薄膜的横截面的TEM相片和根据位置绘图的原子比的曲线图，该基于Bi-Ti-O的薄膜沉积在在硅衬底上由SiO2形成的孔形图案中，该孔形图案具有大约为7的高宽比和根据位置绘图的原子比。实验关注具有BiTi组分的薄膜，因为当Si被包含在组分分析中时，由于将该薄膜涂覆在由SiO2形成的孔形图案中，致使很难获得精确的数据。由于为了在其上形成薄膜引入了很多工艺，所以Si本身不会在处理中产生问题，但是Bi和Ti的组分一致性经常引起问题。
参照图3A的TEM相片，能够看出均匀地形成了Bi和Ti组分的薄膜。
为了确认一致性，在图3A中TEM相片上1至9表示的9个位置上，通过EDS(能量扩散X射线系统)分析每个位置的组分。然后在图3B所示的曲线中标注测量的结果。参照图3B，Bi/(Bi+Ti)的原子比一直约为0.6。换言之，就厚度和组分而言，与其它的多原子电介质材料相比，按照本发明的基于Bi-Ti-Si-O的薄膜显示出极好的阶梯覆盖(step coverage)。
本发明产生下面的结果。
第一，基于BTSO的非晶薄膜被用作诸如DRAM器件的电容器的电介质膜材料，因此防止了电介质薄膜的物理厚度降低时导致的泄露电流增加。
第二，尽管使用非晶薄膜，但获得了60或更大的介电常数。在没有执行用于使非晶薄膜结晶化的退火工艺的电容器制造中，这样大的介电常数通常是不能得到的。
第三，由于形成非晶薄膜的成分具有相对较大的电荷半径比，所以在制造三维结构的电容器期间厚度和组分的一致性最好。
尽管已经参照其典型的实施例部分显示和说明了本发明，但本领域普通技术人员应当理解，在没有脱离由下面的权利要求限定的本发明的实质和范围的情况下，在此可进行各种形式和细节上的变化。
Claims (4)
1.一种用在半导体器件中的非晶电介质薄膜，所述非晶电介质薄膜包括Bi、Ti、Si和O，其中所述非晶电介质薄膜通过化学式
Bi1-x-yTixSiyOz来表示，此处0.2＜x＜0.5，0＜y＜0.5和1.5＜z＜2。
2.一种制造用在半导体器件中的非晶电介质薄膜的方法，其中所述半导体器件包括一底层结构、一电介质膜和一上电极，所述方法包括在所述底层结构上形成包括Bi、Ti、Si和O的所述非晶电介质薄膜，其中所述非晶电介质薄膜具有Bi1-x-yTixSiyOz的化学组成，此处0.2＜x＜0.5，0＜y＜0.5和1.5＜z＜2。
3.如权利要求2所述的制造非晶电介质薄膜的方法，其中使用原子层沉积形成所述非晶电介质薄膜。
4.如权利要求3所述的制造非晶电介质薄膜的方法，其中使用O3作为反应气体，通过一前体，在所述底层结构上，由Bi、Ti和Si以单层的形式形成所述非晶电介质薄膜。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20040013787 | 2004-02-28 | ||
| KR13787/2004 | 2004-02-28 | ||
| KR13787/04 | 2004-02-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1661781A CN1661781A (zh) | 2005-08-31 |
| CN100517608C true CN100517608C (zh) | 2009-07-22 |
Family
ID=34880338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100832521A Expired - Fee Related CN100517608C (zh) | 2004-02-28 | 2004-09-29 | 非晶电介质薄膜及其制造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7501191B2 (zh) |
| JP (1) | JP4901092B2 (zh) |
| KR (1) | KR100624451B1 (zh) |
| CN (1) | CN100517608C (zh) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100781964B1 (ko) * | 2005-12-02 | 2007-12-06 | 한국과학기술연구원 | 내장형 커패시터 및 그 제조 방법 |
| KR102692564B1 (ko) * | 2018-09-21 | 2024-08-06 | 삼성전자주식회사 | 다층 박막 구조물 및 이를 이용한 위상 변환 소자 |
| CN117203729A (zh) * | 2021-04-28 | 2023-12-08 | 松下知识产权经营株式会社 | 电介质、电容器、电气电路、电路基板及设备 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3609482A (en) * | 1970-01-28 | 1971-09-28 | Sylvania Electric Prod | Bismuth titanate film capacitor and method of manufacture |
| US4306214A (en) * | 1978-08-08 | 1981-12-15 | Tdk Electronics Co., Ltd. | Non-linear resistance element, method for preparing same and noise suppressor therewith |
| JPH01254913A (ja) * | 1988-04-04 | 1989-10-11 | Kokusai Denshin Denwa Co Ltd <Kdd> | 高電圧駆動素子用絶縁膜 |
| US5998037A (en) * | 1997-12-22 | 1999-12-07 | Ferro Corporation | Porcelain enamel composition for electronic applications |
| US6255122B1 (en) * | 1999-04-27 | 2001-07-03 | International Business Machines Corporation | Amorphous dielectric capacitors on silicon |
| JP4386529B2 (ja) * | 2000-03-03 | 2009-12-16 | 株式会社Ａｄｅｋａ | 化学気相成長用原料及びこれを用いた金属酸化物薄膜 |
| US6593181B2 (en) * | 2001-04-20 | 2003-07-15 | International Business Machines Corporation | Tailored insulator properties for devices |
| CN100379745C (zh) * | 2001-10-26 | 2008-04-09 | 埃普切公司 | 化学气相淀积用的改良的前体 |
| JP4075485B2 (ja) * | 2002-07-02 | 2008-04-16 | 富士通株式会社 | 半導体装置および非晶質高誘電体膜の堆積方法 |
| AU2003267995A1 (en) * | 2002-07-18 | 2004-02-09 | Aviza Technology, Inc. | Atomic layer deposition of multi-metallic precursors |
| KR100723399B1 (ko) * | 2002-08-06 | 2007-05-30 | 삼성전자주식회사 | 비스무트 티타늄 실리콘 산화물, 비스무트 티타늄 실리콘산화물 박막 및 그 제조방법 |
| KR100682931B1 (ko) * | 2005-02-15 | 2007-02-15 | 삼성전자주식회사 | 비정질 유전막 및 그 제조 방법 |
-
2004
- 2004-09-29 CN CNB2004100832521A patent/CN100517608C/zh not_active Expired - Fee Related
- 2004-09-30 US US10/953,267 patent/US7501191B2/en not_active Expired - Fee Related
- 2004-11-17 JP JP2004332543A patent/JP4901092B2/ja not_active Expired - Fee Related
- 2004-12-17 KR KR1020040108034A patent/KR100624451B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US20050191514A1 (en) | 2005-09-01 |
| KR100624451B1 (ko) | 2006-09-18 |
| KR20050088038A (ko) | 2005-09-01 |
| JP2005244170A (ja) | 2005-09-08 |
| JP4901092B2 (ja) | 2012-03-21 |
| CN1661781A (zh) | 2005-08-31 |
| US7501191B2 (en) | 2009-03-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9281357B2 (en) | DRAM MIM capacitor using non-noble electrodes | |
| KR100297210B1 (ko) | 강유전체커패시터및다른커패시터구조체를위한고온전극-배리어 | |
| US8741712B2 (en) | Leakage reduction in DRAM MIM capacitors | |
| KR100419683B1 (ko) | 평활 전극 및 향상된 메모리 유지 특성을 가지는 박막 강유전성 커패시터를 제작하는 ｄｃ 스퍼터링 공정 | |
| Kim et al. | Atomic layer deposition of ZrO2 thin films with high dielectric constant on TiN substrates | |
| EP2166562B1 (en) | Method for forming a capacitor having a strontium titanium oxide dielectric layer by means of ALD | |
| Kim et al. | Growth characteristics of atomic layer deposited TiO2 thin films on Ru and Si electrodes for memory capacitor applications | |
| US20160133691A1 (en) | DRAM MIMCAP Stack with MoO2 Electrode | |
| Popovici et al. | High-performance ($\text {EOT}< 0.4\text {nm} $, Jg∼ 10− 7 A/cm 2) ALD-deposited Ru\SrTiO 3 stack for next generations DRAM pillar capacitor | |
| US8530348B1 (en) | Integration of non-noble DRAM electrode | |
| JP4094970B2 (ja) | 半導体デバイス用のキャパシタの製造方法及びこのキャパシタを用いる電子デバイス | |
| CN102655176A (zh) | 具有纳米线结构的电容器及其制备方法 | |
| Thomas et al. | Liquid Injection MOCVD of Dysprosium Scandate Films: Deposition Characteristics and High-Applications | |
| Xu et al. | Atomic layer deposition and characterization of amorphous ErxTi1-xOy dielectric ultra-thin films | |
| US8835273B2 (en) | High temperature ALD process of metal oxide for DRAM applications | |
| US7379322B2 (en) | Amorphous high-k thin film and manufacturing method thereof | |
| CN100517608C (zh) | 非晶电介质薄膜及其制造方法 | |
| KR100519777B1 (ko) | 반도체 소자의 캐패시터 및 그 제조 방법 | |
| Lukosius et al. | Electrical and morphological properties of ALD and AVD grown perovskite-type dielectrics and their stacks for metal-insulator-metal applications | |
| CN102007591A (zh) | 电容器及电容器的制造方法 | |
| CN101131931A (zh) | 形成绝缘膜的方法和制造半导体器件的方法 | |
| Seemen et al. | Properties of Atomic Layer Deposited Nanolaminates of Zirconium and Cobalt Oxides | |
| Debnath et al. | Investigations on BaMn x Ti 1-x O 3 ferroelectric film based MFS structure for non-volatile memory application | |
| Ruhl et al. | Dielectric material options for integrated capacitors | |
| Tongpeng et al. | Effects of La-Doped HfO2 Films on Dielectric Properties by Sol-Gel Method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090722 Termination date: 20160929 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |