CN109698008B - Method and device for repairing NOR type memory bit line fault - Google Patents
Method and device for repairing NOR type memory bit line fault Download PDFInfo
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- CN109698008B CN109698008B CN201710992665.9A CN201710992665A CN109698008B CN 109698008 B CN109698008 B CN 109698008B CN 201710992665 A CN201710992665 A CN 201710992665A CN 109698008 B CN109698008 B CN 109698008B
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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Abstract
The invention discloses a method and a device for repairing NOR type memory bit line faults, wherein the method comprises the following steps: detecting whether bit lines of the main array memory unit and the functional array memory unit are abnormal or not, finding out a memory unit connected with a fault bit line, and marking as a fault memory unit; storing the address of the fault storage unit, the repair enabling bit of the fault storage unit and the class identification bit of the fault storage unit, and setting the repair enabling bit of the fault storage unit to be 0 or 1; establishing a mapping relation between a fault storage unit and a redundant storage unit; if the repair enable bit corresponding to the memory cell to be accessed is 1, the memory cell to be accessed is a fault memory cell needing to be repaired; and selecting a redundant storage unit corresponding to the fault storage unit to replace the fault storage unit. According to the technical scheme of the embodiment of the invention, the fault storage unit is repaired by adding the category identification bit, so that the product yield and the utilization rate of the redundant storage unit are improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of nonvolatile memories, in particular to a method and a device for repairing a fault of a bit line of a NOR type memory.
Background
In the NOR type memory, although the structure determines that the NOR type memory has higher reliability, in order to better improve the product yield, a group of redundant memory cells are generally added beside a main array memory cell during design, when some memory cells are unwritable or erased during factory test of the main array memory cell, the memory cell may be a memory cell connected with a fault bit line, and at the moment, the memory cell can be replaced by the redundant memory cell through a certain mapping relation, so that when corresponding erasing operation is performed on a bad memory cell address, the chip data is ensured to be correct, and the production yield of products is improved.
In some special applications, in order to further ensure chip reliability, functions such as error correction, encryption and decryption are added, but a repair process for a memory cell in which a fault occurs is not performed.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method and an apparatus for repairing a NOR-type memory bit line fault, which can repair a faulty memory cell in a main array memory cell and a functional array memory cell, thereby improving the yield of products and the utilization rate of redundant memory cells.
In a first aspect, an embodiment of the present invention provides a method for repairing a NOR-type memory bit line fault, where the method includes:
detecting whether bit lines of the main array memory unit and the functional array memory unit are abnormal or not, finding out a memory unit connected with a fault bit line, and marking as a fault memory unit;
storing the address of the fault storage unit, the repair enable bit of the fault storage unit and the class identification bit of the fault storage unit, and setting the repair enable bit of the fault storage unit to be 0 or 1 according to part of the address of the fault storage unit;
establishing a mapping relation between the fault storage unit and the redundant storage unit;
obtaining a repair enable bit corresponding to a memory cell to be accessed by comparing an address of the memory cell to be accessed with a part of addresses stored in advance in the address of the failed memory cell, wherein if the repair enable bit corresponding to the memory cell to be accessed is 1, the memory cell to be accessed is the failed memory cell to be repaired;
and when the repair enable bit corresponding to the memory cell to be accessed is 1, comparing the address of the memory cell to be accessed with the address of the fault memory cell stored in advance, and if the address of the memory cell to be accessed is matched with the address of the fault memory cell stored in advance, selecting the redundant memory cell corresponding to the fault memory cell from the redundant memory cells to replace the fault memory cell according to the mapping relation and the type identification bit of the fault memory cell.
Optionally, the selecting, according to the mapping relationship and the category identification bit of the faulty storage unit, the redundant storage unit corresponding to the faulty storage unit from the redundant storage units to replace the faulty storage unit specifically includes:
setting a repair sequence of the fault storage units in the main array storage unit and the fault storage units in the functional array storage unit according to the class identification bits of the fault storage units;
and selecting the redundant storage unit corresponding to the fault storage unit to replace the fault storage unit according to the repair sequence and the mapping relation.
Optionally, the functional array storage unit includes one or more of an encryption array storage unit, a decryption array storage unit, or an error correction array storage unit.
Optionally, if the faulty storage unit is located in the main array storage unit and the functional array storage unit, and the functional array storage unit is an error correction array storage unit, the category identification bit of the faulty storage unit of the main array storage unit is 1, and the category identification bit of the faulty storage unit of the functional array storage unit is 0.
In a second aspect, an embodiment of the present invention provides a device for repairing a NOR-type memory bit line fault, including:
the detection module is used for detecting whether the bit lines of the main array storage unit and the functional array storage unit are abnormal or not, finding out the storage unit connected with the fault bit line and marking as the fault storage unit;
the latch module is connected with the detection module and is used for storing the address of the fault storage unit, the repair enabling bit of the fault storage unit and the class identification bit of the fault storage unit, and the repair enabling bit of the fault storage unit is set to be 0 or 1 according to part of addresses in the address of the fault storage unit;
the mapping relation establishing module is connected with the latching module and used for establishing the mapping relation between the fault storage unit and the redundant storage unit;
the confirmation and repair module is connected with the latch module and used for obtaining a repair enable bit corresponding to the memory unit to be accessed by comparing the address of the memory unit to be accessed with a part of prestored addresses in the fault memory unit address, and if the repair enable bit corresponding to the memory unit to be accessed is 1, the memory unit to be accessed is the fault memory unit to be repaired;
and the repair module is respectively connected with the repair confirmation module and the mapping relation establishment module and is used for comparing the address of the memory unit to be accessed with the address of the fault memory unit stored in advance when the repair enable bit corresponding to the memory unit to be accessed is 1, and selecting the redundant memory unit corresponding to the fault memory unit from the redundant memory units to replace the fault memory unit according to the mapping relation and the type identification bit of the fault memory unit if the address of the memory unit to be accessed is matched with the address of the fault memory unit stored in advance.
Optionally, the repair module further includes a repair order setting unit, where the repair order setting unit is configured to set a repair order of a failed storage unit in the main array storage unit and a failed storage unit in the functional array storage unit according to the class identifier of the failed storage unit;
and the repair module is used for selecting the redundant storage unit corresponding to the fault storage unit to replace the fault storage unit according to the repair sequence and the mapping relation.
Optionally, the functional array storage unit includes one or more of an encryption array storage unit, a decryption array storage unit, or an error correction array storage unit.
Optionally, if the faulty storage unit is located in the main array storage unit and the functional array storage unit, and the functional array storage unit is an error correction array storage unit, the category identification bit of the faulty storage unit of the main array storage unit is 1, and the category identification bit of the faulty storage unit of the functional array storage unit is 0.
According to the technical scheme of the embodiment, the address of the storage fault storage unit and the type identification bit of the storage fault storage unit are recorded, and the storage unit which has a mapping relation with the storage fault units in the main array storage unit and the functional array storage unit in the redundant storage unit is used for replacing the storage fault unit, so that the purpose of repairing the storage fault unit is achieved. Because the category identification bits of the fault storage units are recorded, the fault storage units can be repaired by using a group of redundant storage units, and whether the main array storage units or the functional array storage units are repaired can be distinguished, so that the product yield and the utilization rate of the redundant storage units are improved.
Drawings
FIG. 1 is a flow chart illustrating a method for repairing a bit line fault in a NOR-type memory according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for repairing a bit line fault in a NOR-type memory according to a second embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a device for repairing a bit line fault in a NOR-type memory according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of another repair apparatus for a NOR-type memory bit line fault according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a schematic flowchart of a method for repairing a NOR-type memory bit line fault according to an embodiment of the present invention, where the method may be implemented by an apparatus for repairing a NOR-type memory bit line fault, where the apparatus may be implemented by hardware and/or software, and specifically includes the following steps:
In this embodiment, the main array memory cells are typically used for read, write and erase operations. In order to further ensure the reliability of the chip, functions such as error correction, encryption and decryption are added, and when the functions are added, corresponding coding and decoding information can be stored in the functional array storage unit. Optionally, the functional array memory unit includes one or more of an encryption array memory unit, a decryption array memory unit, or an error correction array memory unit.
In the present embodiment, when storing the address of the defective memory cell, the class identification bit of the defective memory cell is set to distinguish the class of the main array memory cell and the functional array memory cell in the defective memory cell. For example, the partial address is not the entire address of the failed memory cell, and may be the highest bits, the last bits, or the middle bits, and the occupation of the partial address in the address of the failed memory cell may be continuous or discontinuous.
And 103, establishing a mapping relation between the fault storage unit and the redundant storage unit.
In this embodiment, the mapping relationship between the failed storage unit and the redundant storage unit can be established by setting the failed storage unit and the redundant storage unit to share one logical address.
And 104, acquiring a repair enable bit corresponding to the memory cell to be accessed by comparing the address of the memory cell to be accessed with a part of addresses in the prestored failed memory cell address, wherein if the repair enable bit corresponding to the memory cell to be accessed is 1, the memory cell to be accessed is the failed memory cell to be repaired.
And acquiring a repair enable bit corresponding to the memory cell to be accessed by comparing the address of the memory cell to be accessed with a part of addresses in the prestored failed memory cell address, wherein the repair enable bit corresponding to the memory cell to be accessed is 1, and the memory cell to be accessed is the failed memory cell to be repaired. The repair enable bit corresponding to the memory cell to be accessed is 1, which indicates that the address of the memory cell to be accessed also contains a partial address, and the partial address occupies the same place as the address of the memory cell to be accessed and the address of the previously stored failed memory cell.
And 105, when the repair enable bit corresponding to the memory cell to be accessed is 1, comparing the address of the memory cell to be accessed with the address of the fault memory cell stored in advance, and if the address of the memory cell to be accessed is matched with the address of the fault memory cell stored in advance, selecting a redundant memory cell corresponding to the fault memory cell from the redundant memory cells to replace the fault memory cell according to the mapping relation and the type identification bit of the fault memory cell.
On the basis of the above steps, it is confirmed that the memory cell to be accessed is a defective memory cell that needs to be repaired, and step 105 repairs the defective memory cell by replacement (selecting a redundant memory cell corresponding to the defective memory cell to replace the defective memory cell).
According to the technical scheme of the embodiment, the address of the storage fault storage unit and the type identification bit of the storage fault storage unit are recorded, and the storage unit which has a mapping relation with the storage fault units in the main array storage unit and the functional array storage unit in the redundant storage unit is used for replacing the storage fault unit, so that the purpose of repairing the storage fault unit is achieved. Because the category identification bits of the fault storage units are recorded, the fault storage units can be repaired by using a group of redundant storage units, and whether the main array storage units or the functional array storage units are repaired can be distinguished, so that the product yield and the utilization rate of the redundant storage units are improved.
Optionally, in the above technical solution, if the faulty memory cell is located in the main array memory cell and the functional array memory cell, and the functional array memory cell is an error correction array memory cell, the category identification bit of the faulty memory cell of the main array memory cell is 1, and the category identification bit of the faulty memory cell of the functional array memory cell is 0.
Illustratively, if the defective memory cell is located in the main array memory cell and the functional array memory cell, and the functional array memory cell includes an error correction array memory cell, an encryption array memory cell, and a decryption array memory cell, the class identification bit of the defective memory cell of the main array memory cell is 11, the class identification bit of the defective memory cell of the error correction array memory cell is 00, the class identification bit of the defective memory cell of the encryption array memory cell is 01, and the class identification bit of the defective memory cell of the decryption array memory cell is 10.
It should be noted that, if there are a plurality of functional array memory units, the defective memory unit in the functional array memory unit and the defective memory unit in the main array memory unit can be distinguished by increasing the bit width of the category identification bit.
Example two
On the basis of the above embodiments, the embodiments of the present invention provide a method for repairing a NOR-type memory bit line fault, and referring to fig. 2, the method includes the following steps:
And 204, acquiring a repair enable bit corresponding to the memory cell to be accessed by comparing the address of the memory cell to be accessed with a part of addresses in the prestored failed memory cell address, wherein if the repair enable bit corresponding to the memory cell to be accessed is 1, the memory cell to be accessed is the failed memory cell to be repaired.
In step 205, the repair sequence of the failed memory cell in the main array memory cell and the failed memory cell in the functional array memory cell can be set by the type identification bit of the failed memory cell. For example, in order to save repair resources (the number of redundant memory cells), repair may be performed through the same set of redundant memory cells, and the main array memory cells are repaired preferentially; for the case that both the main array memory cell and the functional array memory cell have a faulty memory cell, the faulty memory cell of the main array memory cell can be repaired preferentially by selecting the address and the class identification bit of the faulty memory cell that only records the main array memory cell, so as to ensure the data correctness. In order to solve the above problem, in the technical solution of this embodiment, it can be distinguished whether the main array memory cell or the functional array memory cell is repaired by recording the class flag of the failed memory cell.
In the technical solution of this embodiment, in addition to the above-described technique of the embodiment, the repair order of the failed memory cell in the main array memory cell and the failed memory cell in the functional array memory cell can be set by the type flag of the failed memory cell.
EXAMPLE III
Fig. 3 is a schematic structural diagram of a device for repairing a NOR-type memory bit line fault according to an embodiment of the present invention, where the device may be implemented by hardware, and as shown in fig. 3, the device includes:
a detection module 301, configured to detect whether bit lines of the main array memory cell and the functional array memory cell are abnormal, find a memory cell connected to a faulty bit line, and mark the memory cell as a faulty memory cell;
a latch module 302, where the latch module 302 is connected to the detection module 301, and is configured to store the address of the failed memory cell, the repair enable bit of the failed memory cell, and the class identification bit of the failed memory cell, and set the repair enable bit of the failed memory cell to be 0 or 1 according to a part of addresses in the address of the failed memory cell;
the mapping relation establishing module 303, the mapping relation establishing module 303 is connected with the latch module 302, and is used for establishing a mapping relation between the failure storage unit and the redundant storage unit;
a confirm-repair module 304, where the confirm-repair module 304 is connected to the latch module 302, and is configured to obtain a repair enable bit corresponding to a memory cell to be accessed by comparing an address of the memory cell to be accessed with a part of addresses in the previously stored failed memory cell address, and if the repair enable bit corresponding to the memory cell to be accessed is 1, the memory cell to be accessed is the failed memory cell to be repaired;
a repair module 305, where the repair module 305 is connected to the confirm repair module 304 and the mapping relationship establishing module 303, respectively, and is configured to compare an address of the memory cell to be accessed with a pre-stored address of the failed memory cell when a repair enable bit corresponding to the memory cell to be accessed is 1, and select, from the redundant memory cells, the redundant memory cell corresponding to the failed memory cell to replace the failed memory cell according to the mapping relationship and a category identification bit of the failed memory cell if the address of the memory cell to be accessed matches the pre-stored address of the failed memory cell.
Optionally, on the basis of the foregoing technical solution, referring to fig. 4, the repair module 305 further includes a repair order setting unit 3051, where the repair order setting unit is configured to set a repair order of a failed storage unit in the main array storage unit and a failed storage unit in the functional array storage unit according to the class identification bit of the failed storage unit;
the repair module 305 is configured to select a redundant memory cell corresponding to the failed memory cell to replace the failed memory cell according to the repair sequence and the mapping relationship.
According to the technical scheme of the embodiment, the address of the storage fault storage unit and the type identification bit of the storage fault storage unit are recorded, and the storage unit which has a mapping relation with the storage fault units in the main array storage unit and the functional array storage unit in the redundant storage unit is used for replacing the storage fault unit, so that the purpose of repairing the storage fault unit is achieved. Because the category identification bits of the fault storage units are recorded, the fault storage units can be repaired by using a group of redundant storage units, and whether the main array storage units or the functional array storage units are repaired can be distinguished, so that the product yield and the utilization rate of the redundant storage units are improved.
Optionally, on the basis of the above technical solution, the functional array storage unit includes one or more of an encryption array storage unit, a decryption array storage unit, or an error correction array storage unit.
Optionally, on the basis of the above technical solution, if the faulty storage unit is located in the main array storage unit and the functional array storage unit, and the functional array storage unit is an error correction array storage unit, the category identification bit of the faulty storage unit of the main array storage unit is 1, and the category identification bit of the faulty storage unit of the functional array storage unit is 0.
The NOR-type memory bit line fault repairing device provided in the above embodiments can execute the NOR-type memory bit line fault repairing method provided in any embodiment of the present invention, and has corresponding functional modules and beneficial effects for executing the method. Technical details that are not elaborated in the above embodiments may be referred to a method for repairing a NOR-type memory bit line failure provided by any embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (8)
1. A method for repairing a NOR type memory bit line fault, comprising:
detecting whether bit lines of the main array memory unit and the functional array memory unit are abnormal or not, finding out a memory unit connected with a fault bit line, and marking as a fault memory unit;
storing the address of the failed storage unit, the repair enable bit of the failed storage unit and the class identification bit of the failed storage unit, setting the repair enable bit of the failed storage unit to be 0 or 1 according to part of the addresses of the failed storage unit, wherein the class identification bit of the failed storage unit is used for distinguishing the classes of a main array storage unit and a functional array storage unit in the failed storage unit;
establishing a mapping relation between the fault storage unit and the redundant storage unit;
obtaining a repair enable bit corresponding to a memory cell to be accessed by comparing an address of the memory cell to be accessed with a part of addresses stored in advance in the address of the failed memory cell, wherein if the repair enable bit corresponding to the memory cell to be accessed is 1, the memory cell to be accessed is the failed memory cell to be repaired;
and when the repair enable bit corresponding to the memory cell to be accessed is 1, comparing the address of the memory cell to be accessed with the address of the fault memory cell stored in advance, and if the address of the memory cell to be accessed is matched with the address of the fault memory cell stored in advance, selecting the redundant memory cell corresponding to the fault memory cell from the redundant memory cells to replace the fault memory cell according to the mapping relation and the type identification bit of the fault memory cell.
2. The repair method according to claim 1,
the selecting, from the redundant storage units according to the mapping relationship and the category identification bits of the faulty storage units, the redundant storage unit corresponding to the faulty storage unit to replace the faulty storage unit specifically includes:
setting a repair sequence of the fault storage units in the main array storage unit and the fault storage units in the functional array storage unit according to the class identification bits of the fault storage units;
and selecting the redundant storage unit corresponding to the fault storage unit to replace the fault storage unit according to the repair sequence and the mapping relation.
3. The repair method according to claim 1,
the functional array memory unit includes one or more of an encryption array memory unit, a decryption array memory unit, or an error correction array memory unit.
4. The repair method according to claim 3,
if the fault storage unit is located in the main array storage unit and the functional array storage unit, and the functional array storage unit is an error correction array storage unit, the class identification bit of the fault storage unit of the main array storage unit is 1, and the class identification bit of the fault storage unit of the functional array storage unit is 0.
5. A NOR-type memory bit line failure repair apparatus, comprising:
the detection module is used for detecting whether the bit lines of the main array storage unit and the functional array storage unit are abnormal or not, finding out the storage unit connected with the fault bit line and marking as the fault storage unit;
the latch module is connected with the detection module and is used for storing the address of the fault storage unit, the repair enabling bit of the fault storage unit and the class identification bit of the fault storage unit, the repair enabling bit of the fault storage unit is set to be 0 or 1 according to part of the address of the fault storage unit, and the class identification bit of the fault storage unit is used for distinguishing the class of a main array storage unit and the class of a functional array storage unit in the fault storage unit;
the mapping relation establishing module is connected with the latching module and used for establishing the mapping relation between the fault storage unit and the redundant storage unit;
the confirmation and repair module is connected with the latch module and used for obtaining a repair enable bit corresponding to the memory unit to be accessed by comparing the address of the memory unit to be accessed with a part of prestored addresses in the fault memory unit address, and if the repair enable bit corresponding to the memory unit to be accessed is 1, the memory unit to be accessed is the fault memory unit to be repaired;
and the repair module is respectively connected with the repair confirmation module and the mapping relation establishment module and is used for comparing the address of the memory unit to be accessed with the address of the fault memory unit stored in advance when the repair enable bit corresponding to the memory unit to be accessed is 1, and selecting the redundant memory unit corresponding to the fault memory unit from the redundant memory units to replace the fault memory unit according to the mapping relation and the type identification bit of the fault memory unit if the address of the memory unit to be accessed is matched with the address of the fault memory unit stored in advance.
6. The apparatus of claim 5,
the repair module further comprises a repair sequence setting unit, wherein the repair sequence setting unit is used for setting the repair sequence of the fault storage unit in the main array storage unit and the fault storage unit in the functional array storage unit according to the type identification bit of the fault storage unit;
and the repair module is used for selecting the redundant storage unit corresponding to the fault storage unit to replace the fault storage unit according to the repair sequence and the mapping relation.
7. The prosthetic device of claim 5,
the functional array memory unit includes one or more of an encryption array memory unit, a decryption array memory unit, or an error correction array memory unit.
8. The prosthetic device of claim 7,
if the fault storage unit is located in the main array storage unit and the functional array storage unit, and the functional array storage unit is an error correction array storage unit, the class identification bit of the fault storage unit of the main array storage unit is 1, and the class identification bit of the fault storage unit of the functional array storage unit is 0.
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| CN111428280B (en) * | 2020-06-09 | 2020-11-17 | 浙江大学 | SoC (System on chip) security chip key information integrity storage and error self-repairing method |
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