CN109427541A - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN109427541A CN109427541A CN201710753428.7A CN201710753428A CN109427541A CN 109427541 A CN109427541 A CN 109427541A CN 201710753428 A CN201710753428 A CN 201710753428A CN 109427541 A CN109427541 A CN 109427541A
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- semiconductor devices
- forming method
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02098—Cleaning only involving lasers, e.g. laser ablation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Optics & Photonics (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a kind of forming methods of semiconductor devices, comprising: provides substrate；It anneals to the substrate, to eliminate the pollutant of the substrate surface；After the annealing steps, the anti-reflecting layer for being located at the substrate surface is formed；Form the photoresist layer for being located at the anti-reflecting layer.By being made annealing treatment to substrate before forming anti-reflecting layer, the pollutant for being likely to be present in the substrate surface is eliminated, the yield for the figure that etched substrate obtains is finally improved, has better met customer requirement.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of forming method of semiconductor devices.
Background technique
As the integrated level of semiconductor devices improves, the line width of semiconductor devices is smaller and smaller, the control of critical size
More and more important, the requirement to photoetching process is also higher and higher.In order to meet the requirement of photoetching, in addition in terms of lithographic equipment
Other than upgrading, anti-reflecting layer (Anti-Reflective Coating, ARC) technology is also applied to improve in photoetching
The precision of photoetching.The effect of anti-reflecting layer is main are as follows: prevents light by reflecting after photoresist at wafer interface.And it reflects
Light can be interfered with incident light, cause photoresist to be unable to uniform exposure.Anti-reflecting layer have passed through top anti-reflective layer
(Top Anti-Reflective Coating, TARC) and bottom anti-reflection layer (Bottom Anti-Reflective
Coating, BARC) two stages.Currently, mainly using bottom anti-reflection layer.
Referring to FIG. 1, existing photoetching process generally includes: forming bottom anti-reflection layer 110 on substrate 100；The bottom of at
Photoresist layer (not shown) is formed on portion's anti-reflecting layer 110；To photoresist layer exposure, development, photoetching offset plate figure is formed
120.Later using the photoresist for being formed with the photoetching offset plate figure as mask etching substrate, corresponding figure is formed.But existing shape
Usually there are many defects at photoetching offset plate figure, the figure resulted in the substrate is not well positioned to meet customer requirement, good
Rate is low.
The prior art needs a kind of forming method of new semiconductor devices, is formed in the figure of the substrate with raising
Yield better meets customer requirement.
Summary of the invention
The purpose of the present invention is to provide a kind of can be improved to be formed in the yield of the figure of the substrate, more preferably meets client
It is required that semiconductor devices forming method.
The present invention provides a kind of forming methods of semiconductor devices, comprising:
Substrate is provided；It anneals to the substrate, to eliminate the pollutant of the substrate surface；In the annealing steps
Afterwards, the anti-reflecting layer for being located at the substrate surface is formed；Form the photoresist layer for being located at the anti-reflecting layer.
Optionally, described to be annealed into high temperature rapid thermal annealing, the temperature of the high temperature rapid thermal annealing is more than or equal to 1000 DEG C, when
Between be less than or equal to 950 μ s.
Optionally, described to be annealed into laser annealing.
Optionally, the method for the laser annealing are as follows: the entire substrate of laser beam flying.
Optionally, the laser beam successively substrate described in uniform speed scanning, until eliminating the pollutant of the substrate surface.
Optionally, the process parameters range of the laser annealing are as follows: 2.5KW-4KW, the speed of laser beam flying are 80nm/
μs-150nm/μs。
Optionally, further includes: using the photoresist layer as exposure mask, etch the substrate.
Optionally, the substrate includes metal layer and the interlayer dielectric layer for covering the metal layer.
Optionally, the interlayer dielectric layer is single-layer or multi-layer stacked structure.
Optionally, the formation process of the anti-reflecting layer is spin coating proceeding.
In the inventive solutions, it due to being made annealing treatment to substrate before forming anti-reflecting layer, eliminates
It is likely to be present in the pollutant of the substrate surface, avoiding has bubble, the anti-reflective of formation inside the anti-reflecting layer to be formed
The quality for penetrating layer is preferable, and the graphical quality for the photoresist layer being subsequently formed is also preferable, subsequent preferable using the graphical quality
When photoresist is mask etching substrate, the yield of the figure obtained on substrate is also higher, can better meet customer requirement.
Further, it using laser annealing to being that substrate is handled, can quickly and effectively eliminate described in being likely to be present in
The pollutant of substrate surface, without being damaged to substrate.While the yield of the figure obtained on improving substrate, also improve
Production efficiency.
Detailed description of the invention
Fig. 1 is the schematic diagram of the section structure of the forming process of the photoetching process of the prior art；
Fig. 2 is the contaminated substrate schematic diagram of the prior art；
Fig. 3 to Fig. 7 is the schematic diagram of the section structure of the forming process of the semiconductor devices of the embodiment of the present invention.
Specific embodiment
As previously mentioned, the photoetching offset plate figure that the prior art is formed usually there are many defects, result in the substrate
Figure is not well positioned to meet customer requirement, and yield is low.
It has been investigated that the reason of causing the above problem are as follows: be formed in the bottom anti-reflection layer 110 on 100 surface of substrate
There are problems for quality, internal to result in containing bubble 115 (bublle defect, shown in Fig. 1) in the bottom anti-reflective
In post-exposure, the photoresist under-exposure with the bubble corresponding region forms defect and (does not show the photoresist on 110 surface of layer
Out), when subsequent use forms the defective photoresist etching substrate, yield is affected naturally.
It finds why will form bubble inside bottom anti-reflection layer 110 after further study, is because of substrate 100
Before forming bottom anti-reflection layer 110, other series of processes are usually had been carried out, in these preamble techniques, there are parts
Residue, such as organic matter (organic), reaction residual gas (outgassing), particulate matter (particle) etc., or
There are pollutant inside base station for placing the substrate, these pollutants further polluted substrate, so as to cause
When the substrate surface being contaminated forms bottom anti-reflection layer, bubble is produced inside bottom anti-reflection layer.Especially adopt
When forming bottom anti-reflection layer 110 with spin coating proceeding, the range of pollutant 105 is further enlarged, and is such as scattered in entire substrate
100 peripheries, as shown in Figure 2.
In order to solve this problem, the present invention provides a kind of forming methods of semiconductor devices, comprising: is forming antireflection
Before layer, the substrate of its bottom is made annealing treatment, to eliminate the pollutant of the substrate surface.
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should be understood that unless in addition specific
Illustrate, the component and the positioned opposite of step, numerical expression and numerical value otherwise illustrated in these embodiments is not understood that
For limitation of the scope of the invention.
In addition, it should be understood that for ease of description, the size of all parts shown in attached drawing is not necessarily according to reality
The proportionate relationship on border is drawn, such as certain layers of thickness or width can be exaggerated relative to other layers.
The description of exemplary embodiment is merely illustrative below, in any sense all not as to the present invention and
Its any restrictions applied or used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of these technologies, method and apparatus, these technologies, method and apparatus should be considered as a part of this specification.
It should be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined or illustrates in attached drawing, then will not need that it is further discussed in the explanation of subsequent attached drawing.
Referring to FIG. 3, providing substrate.
The substrate is for the basis as subsequent etching processes.The substrate includes semiconductor, metal and/or other materials
Matter.The substrate can be single-layer or multi-layer stacked structure.In an embodiment of the present invention, the substrate includes metal layer 201
With the interlayer dielectric layer 202 for covering the metal layer 201.
Wherein, the metal layer 201 can be etched in the subsequent process, to form interconnection metallization lines or other structures.Institute
The material for stating metal layer 201 is one of Cu, aluminium, Al-Si etc. or a variety of.In the embodiment of the present invention, the metal layer 201
Material be Cu, subsequent etching formed interconnection metallization lines.
The interlayer dielectric layer 202 is for the subsequent metal layer 201 that bottom is isolated and is formed in 202 surface of interlayer dielectric layer
Conductive layer.The interlayer dielectric layer 202 can be single-layer or multi-layer stacked structure.In an embodiment of the present invention, the layer
Between dielectric layer 202 be multilayer lamination structure, including covering described in the first interlayer dielectric layer 202a and the covering of the metal layer 201
The second interlayer dielectric layer 202b of first interlayer dielectric layer 202a.Wherein, the first interlayer dielectric layer 202a is porous, loose
Silica, with meet compared with low-k requirement；Second interlayer dielectric layer 202b is more than the first interlayer dielectric layer 202a
Fine and close silica, generallys use TEOS (silester) technique and is formed.
It should be noted that in other embodiments of the invention, can also be adulterated in the first interlayer dielectric layer 202a
To reduce the impurity of dielectric constant, details are not described herein.
Referring to FIG. 4, annealing to the substrate, to eliminate the pollutant of the substrate surface.
As previously mentioned, in some preamble techniques, there are Certain residues, such as organic matter (organic), reaction
Residual gas (outgassing), particulate matter (particle) etc., or the base station inside presence for placing the substrate
Pollutant, these pollutants further polluted substrate.In order to avoid the pollutant is further to the anti-reflective being subsequently formed
It penetrates layer to impact, must first eliminate the pollutant.
The pollutant annealed for eliminating the substrate surface.It is described to be annealed into high temperature rapid thermal annealing, the high temperature
The temperature of short annealing is more than or equal to 1000 DEG C, and the time is less than or equal to 950 μ s.For example, in a wherein example, the high temperature
The temperature of short annealing is 1250 DEG C, and annealing time is 800 μ s；In another example, the temperature of the high temperature rapid thermal annealing
It is 1300 DEG C, annealing time is 750 μ s.From the foregoing, it will be observed that the temperature and annealing time annealed when the high temperature rapid thermal annealing are at anti-
Than that is, temperature is higher, and annealing time is shorter.Under above-mentioned hot conditions, the pollutant of substrate surface is instantaneously eliminated, Bu Huizai
Subsequent technique is impacted.Moreover, because annealing time is shorter, also have not enough time to the semiconductor component (example formed
Such as substrate) it impacts, thus the performance of finally formed semiconductor devices can't be impacted.
In an embodiment of the present invention, described to be annealed into laser annealing, the method for the laser annealing are as follows: to use laser beam
210 scan the entire substrate surface.Preferably, the laser beam 210 successively substrate described in uniform speed scanning, until described in eliminating
The pollutant of substrate surface.
In the embodiment of the present invention, the process parameters range of the laser annealing are as follows: power 2.5KW-4KW, laser beam
The speed of scanning is 80nm/ μ s-150nm/ μ s.For example, in a wherein example, laser power 3KW, laser beam flying
Speed is 100nm/ μ s；In another example, laser power 2.7KW, the speed of laser beam flying are 90nm/ μ s；And or
In another example, laser power 3.5KW, the speed of laser beam flying is 120nm/ μ s to person.From the foregoing, it will be observed that in above-mentioned ginseng
In number range, the power of laser and the speed of laser beam flying are proportional, when laser power is larger, select faster scanning speed
Degree can reach the purpose eliminating above-mentioned pollutant and not impacting to base substrate.Referring to FIG. 5, being walked in the annealing
After rapid, the anti-reflecting layer 220 for being located at the substrate surface is formed.
The auxiliary layer when anti-reflecting layer 220 is used for as the exposure of subsequent photoresist, to improve the exposure effect of photoresist
Fruit, thus have zero defect inside the anti-reflecting layer 220, directly affect subsequent photoresist exposure effect, and the photoetching formed
The accuracy of glue pattern.
Since aforementioned annealing steps have eliminated the pollutant of the substrate surface, the anti-reflecting layer formed
220 quality is preferable, and the bubble as caused by aforementioned contaminants is not present in the anti-reflecting layer 220.In the embodiment of the present invention
In, the formation process of the anti-reflecting layer 220 is spin coating proceeding.
Referring to FIG. 6, forming the photoresist layer 230 for being located at the anti-reflecting layer 220.
The photoresist layer 230 is used for as subsequent as substrate described in mask etching.The material of the photoresist layer 230
For photoresist.The photoresist layer 230 can be positive photoresist or anti-glue.In an embodiment of the present invention, the shape of the photoresist layer 230
It include spin coating, baking, exposure, development etc. at technique, details are not described herein.
Referring to FIG. 7, being exposure mask with the photoresist layer 230, the substrate is etched.
The quality of the anti-reflecting layer 220 of auxiliary layer when due to exposing as photoresist is preferable, thus the photoetching
Glue-line 230 can obtain more accurate figure, the subsequent photoresist using this with precise pattern in exposure process
Layer 230 is used as exposure mask, and the available product for being more able to satisfy customer requirement after etched substrate improves the yield of product, and
Formation efficiency is improved.
In an embodiment of the present invention, the substrate includes metal layer 201 and the inter-level dielectric for covering the metal layer 201
Layer 202, the purpose of etched substrate are in order to which the metal wire of adjacent layer to be connected to.Therefore the etching process includes that etching interlayer is situated between
Matter layer 202 is until expose the metal layer 201.It is subsequent filling conductive material to form conductive hole into the hole after etching or lead
Electric plug, to be connected to the metal wire of adjacent layer.As it was noted above, due to the exposure matter of the photoresist layer 230 as exposure mask
Preferably, the figure of the photoresist layer 230 of formation is more accurate for amount, and the position of the conductive hole or conductive plunger that are subsequently formed is also more
Accurately, the metal wire of adjacent layer can be effectively connected to.
It should be noted that in other embodiments of the invention, the etching process can also include etching the gold
Belong to layer 201, with formed metal wire or other, details are not described herein.
So far, the present invention is described in detail.In order to avoid covering design of the invention, it is public that this field institute is not described
The some details known.Those skilled in the art as described above, completely it can be appreciated how implementing technology disclosed herein
Scheme.
Although some specific embodiments of the invention are described in detail by example, the skill of this field
Art personnel it should be understood that above example merely to being illustrated, the range being not intended to be limiting of the invention.The skill of this field
Art personnel are it should be understood that can without departing from the scope and spirit of the present invention modify to above embodiments.This hair
Bright range is defined by the following claims.
Claims (10)
1. a kind of forming method of semiconductor devices characterized by comprising
Substrate is provided；
It anneals to the substrate, to eliminate the pollutant of the substrate surface；
After the annealing steps, the anti-reflecting layer for being located at the substrate surface is formed；
Form the photoresist layer for being located at the anti-reflecting layer.
2. the forming method of semiconductor devices as described in claim 1, which is characterized in that the high temperature that is annealed into quickly moves back
Fire, the temperature of the high temperature rapid thermal annealing are more than or equal to 1000 DEG C, and the time is less than or equal to 950 μ s.
3. the forming method of semiconductor devices as described in claim 1, which is characterized in that described to be annealed into laser annealing.
4. the forming method of semiconductor devices as claimed in claim 3, which is characterized in that the method for the laser annealing are as follows:
The entire substrate surface of laser beam flying.
5. the forming method of semiconductor devices as claimed in claim 4, which is characterized in that the laser beam successively uniform speed scanning
The substrate, until eliminating the pollutant of the substrate surface.
6. the forming method of semiconductor devices as claimed in claim 4, which is characterized in that the technological parameter of the laser annealing
Range are as follows: power 2.5KW-4KW, the speed of laser beam flying are 80nm/ μ s-150nm/ μ s.
7. the forming method of semiconductor devices as described in claim 1, which is characterized in that further include: with the photoresist layer
For exposure mask, the substrate is etched.
8. the forming method of semiconductor devices as claimed in claim 7, which is characterized in that the substrate includes metal layer and covers
Cover the interlayer dielectric layer of the metal layer.
9. the forming method of semiconductor devices as claimed in claim 8, which is characterized in that the interlayer dielectric layer be single layer or
Multilayer lamination structure.
10. the forming method of semiconductor devices as described in claim 1, which is characterized in that the formation work of the anti-reflecting layer
Skill is spin coating proceeding.
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| CN201710753428.7A CN109427541A (en) | 2017-08-29 | 2017-08-29 | The forming method of semiconductor devices |
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| CN201710753428.7A CN109427541A (en) | 2017-08-29 | 2017-08-29 | The forming method of semiconductor devices |
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| CN1430790A (en) * | 2000-05-23 | 2003-07-16 | 先进微装置公司 | Method for forming bottom anti-reflective coating using rapid thermal anneal with oxidizing gas |
| CN101123210A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Making method for metal interconnection layer |
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