CN109326591A - A kind of power device protection chip and its manufacturing method - Google Patents
A kind of power device protection chip and its manufacturing method Download PDFInfo
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- CN109326591A CN109326591A CN201811168564.0A CN201811168564A CN109326591A CN 109326591 A CN109326591 A CN 109326591A CN 201811168564 A CN201811168564 A CN 201811168564A CN 109326591 A CN109326591 A CN 109326591A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000009792 diffusion process Methods 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000013078 crystal Substances 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 4
- 230000005611 electricity Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention discloses a kind of power device protection chip, it includes the silicon single crystal of the first conduction type, silicon single crystal includes front and the back side opposite with front, front and back is etched with several grooves, in front, the side wall of the back side and groove is each formed with oxide layer, the bottom of groove is formed with the first diffusion region of the first conduction type, the epitaxial layer of the second conduction type is filled in groove, the second diffusion region of the second conduction type is formed on epitaxial layer, the first metal layer is formed in positive oxide layer and the second diffusion region, second metal layer is formed on oxide layer overleaf and the second diffusion region.The present invention also provides power device protection chip manufacturing method, there is this method to prepare above-mentioned power device protection chip defect it is few, leak electricity small and good reliability.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of power device that double-face epitaxial is two-way to protect chip.
Background technique
As semiconductor devices increasingly tends to miniaturization, high density and multi-functional, electronic device becomes increasingly susceptible to electricity
The influence for pressing surge, even results in fatal harm.Power device protection chip, which is that one kind is widely used, to be used to protect sensitivity
Semiconductor devices destroys it and specially designed solid-state semiconductor device from transient voltage surge, it has clamp coefficient
It is small, small in size, response is fast, leakage current is small and high reliability, and various voltage surges such as from static discharge to lightning
Transient current spikes can be induced, power device protection chip is commonly used to protect sensitive circuit not by the impact of surge.And
Existing power device protection chip that there are chip areas is excessive, the low disadvantages such as low with unfailing performance of Surge handling capability.
Summary of the invention
In view of this, the power that the present invention provides a kind of defects is few, small and good reliability the double-face epitaxial of electric leakage is two-way
Device protects chip and its manufacturing method.
The technological means that the present invention uses is as follows:
A kind of power device protects chip comprising the silicon single crystal of the first conduction type, the silicon single crystal include front and
The opposite back side with front, the front and the back side are etched with several grooves, in the front, the back side and institute
The side wall for stating groove is each formed with oxide layer, and the bottom of the groove is formed with the first diffusion region of the first conduction type, described
It is filled with the epitaxial layer of the second conduction type in groove, is formed with the second diffusion of the second conduction type on said epitaxial layer there
Area is formed with the first metal layer in the positive oxide layer and the second diffusion region, in the oxide layer at the back side and second
Second metal layer is formed on diffusion region.
Power device provided by the invention protects chip, by the equal etching groove of the front and back of silicon single crystal, in groove
Interior filling epitaxial layer, wherein silicon single crystal 1 is different from the conduction type of epitaxial layer 5, forms one group of longitudinal direction diode structure, and PN junction is adopted
It being formed with filling epitaxial layer in the trench, the interface of PN junction is maintained in silicon single crystal, and defect is few, it leaks electricity small, power device protection
Chip reliability is good.
Another aspect of the present invention provides a kind of manufacturing method of power device protection chip, includes at least following step
It is rapid:
The silicon single crystal with first conduction type in front and the back side opposite with front is provided, described positive and described
The quantity of several grooves of back-etching, the front groove is equal with the quantity of the backside trench；
Oxide layer is formed in the inner sidewall of the front, the back side, the groove；
The first diffusion region of the first conduction type is formed in the bottom of the groove；
The epitaxial layer of the second conduction type is filled in the groove；
The second diffusion region of the second conduction type is formed on said epitaxial layer there；
And the first metal layer is formed in the positive oxide layer and the second diffusion region, the oxide layer at the back side
Second metal layer is formed on the second diffusion region.
The manufacturing method of the two-way power device protection chip of double-face epitaxial provided by the invention, manufacturing process difficulty is low,
It only needs an etching groove and primary filling epitaxial layer that can complete, reduces device manufacturing cost.
Detailed description of the invention
Fig. 1 is equivalent circuit diagram of the invention；
Fig. 2~Fig. 8 is each step schematic diagram that power device of the invention protects manufacturing method of chip；
Fig. 9 is that the power device of the embodiment of the present invention two protects chip structure schematic diagram；
Wherein: silicon single crystal 1；Groove 2；Oxide layer 3；First diffusion region 4；Epitaxial layer 5；Second diffusion region 6；The first metal layer
7；Second metal layer 8.
Specific embodiment
The technological means that the present invention uses is as follows:
A kind of power device protects chip comprising the silicon single crystal 1 of the first conduction type, silicon single crystal 1 include front and with
The opposite back side in front, front and back are etched with several grooves 2, are each formed in the side wall of front, the back side and groove 2
Oxide layer 3, the bottom of groove 2 are formed with the first diffusion region 4 of the first conduction type, are filled with the second conduction type in groove 2
Epitaxial layer 5, the second diffusion region 6 of the second conduction type is formed on epitaxial layer 5, is expanded in positive oxide layer 3 and second
It dissipates and is formed with the first metal layer 7 in area 6, be formed with second metal layer 8 on oxide layer 3 overleaf and the second diffusion region 6.
Power device provided by the invention protects chip, by the equal etching groove 2 of the front and back of silicon single crystal 1, in ditch
Epitaxial layer 5 is filled in slot 2, wherein silicon single crystal 1 is different from the conduction type of epitaxial layer 5, forms one group of longitudinal direction diode structure, PN
Knot is maintained in silicon single crystal 1 using the formation of epitaxial layer 5, the interface of PN junction is filled in groove 2, and defect is few, and leak electricity small, power device
Part protects chip reliability good.
The other side of the present embodiment provides a kind of manufacturing method of power device protection chip, includes at least following step
It is rapid:
The silicon single crystal 1 for having first conduction type in front and the back side opposite with front is provided, is carved in front and back
Several grooves 2 are lost, the quantity of front groove 2 is equal with the quantity of backside trench 2；
Oxide layer 3 is formed in the inner sidewall of front, the back side, groove 2；
The first diffusion region 4 of the first conduction type is formed in the bottom of groove 2；
The epitaxial layer 5 of the second conduction type is filled in groove 2；
The second diffusion region 6 of the second conduction type is formed on epitaxial layer 5；
And the first metal layer 7 is formed in positive oxide layer 3 and the second diffusion region 6, oxide layer 3 overleaf and the
Second metal layer 8 is formed on two diffusion regions 6.
The manufacturing method of the two-way power device protection chip of double-face epitaxial provided by the invention, manufacturing process difficulty is low,
It only needs an etching groove 2 and primary filling epitaxial layer 5 that can complete, reduces device manufacturing cost.
The equivalent circuit diagram of chip is protected for power device of the invention as shown in Figure 1, wherein two PN connect mutually up and down
Symmetrically.
Embodiment one:
As shown in figure 8, the present embodiment provides a kind of power devices to protect chip comprising the silicon single crystal of the first conduction type
1, silicon single crystal 1 includes front and the back side opposite with front, and front and back is etched with several grooves 2, in front, the back side
And the side wall of groove 2 is each formed with oxide layer 3, the bottom of groove 2 is formed with the first diffusion region 4 of the first conduction type, groove 2
It is inside filled with the epitaxial layer 5 of the second conduction type, the second diffusion region 6 of the second conduction type is formed on epitaxial layer 5, just
It is formed with the first metal layer 7 on the oxide layer 3 in face and the second diffusion region 6, shape in oxide layer 3 overleaf and the second diffusion region 6
At there is second metal layer 8.
Wherein the quantity of positive groove 2 is no less than 3, the quantity phase of the quantity of backside trench 2 and positive groove 2
Deng horizontal spacing between groove 2 is greater than the width of groove 2.2 quantity of groove and back-etching of front etching in the present embodiment
Groove 2 quantity it is consistent, guarantee that front and back mutually forms 1 group of longitudinal direction diode structure.And the groove 2 of every one side
No less than 3, can guarantee that element leakage is smaller in this way, guarantee groove 2 between horizontal spacing be greater than groove 2 width be for
Guarantee the uniformity of current density distribution.
More specifically, the width of groove 2 of the horizontal spacing between groove 2 greater than 3 times.
Positive groove 2 and the groove 2 at the back side are staggered.The present embodiment uses interlaced arrangement mode, front
Groove 2 and the back side groove 2 in forming process, intersect to form groove 2, the staggered groove 2 of the present embodiment can be with
The thickness of device is effectively reduced, and the depth of groove 2 can simultaneously increased.
First diffusion region 4 diffuses to form after the ion by the first conduction type of injection.
In the present embodiment, the first conduction type is N-type conductive material, and the second conduction type is P-type conduction material.
Embodiment two:
As shown in figure 9, the present embodiment provides a kind of power devices to protect chip, the wherein function of the present embodiment and embodiment one
Rate device protects chip structure essentially identical, the difference is that 2 face of groove at positive groove 2 and the back side arranges.At this
A kind of different modes that front and back groove 2 etches are provided in embodiment, 2 face of groove in front and the back side in the present embodiment
It is corresponding, more grooves 2 can be etched on same area in this way, improve the reliability of device.Wherein when front and the back side
2 face of groove to it is corresponding when mutual corresponding two grooves 2 be not in contact with each other, and the first diffusion region 4 of 2 bottom of groove is also mutually
It does not contact, keeps spacing.
Embodiment three:
The present embodiment provides the manufacturing methods of a kind of above-described embodiment one and the power device of embodiment two protection chip, until
Less the following steps are included:
The silicon single crystal 1 for having first conduction type in front and the back side opposite with front is provided, is carved in front and back
Several grooves 2 are lost, the quantity of front groove 2 is equal with the quantity of backside trench 2；
Oxide layer 3 is formed in the inner sidewall of front, the back side, groove 2；
The first diffusion region 4 of the first conduction type is formed in the bottom of groove 2；
The epitaxial layer 5 of the second conduction type is filled in groove 2；
The second diffusion region 6 of the second conduction type is formed on epitaxial layer 5；
And the first metal layer 7 is formed in positive oxide layer 3 and the second diffusion region 6, oxide layer 3 overleaf and the
Second metal layer 8 is formed on two diffusion regions 6.
The manufacturing method of the two-way power device protection chip of double-face epitaxial provided by the invention, manufacturing process difficulty is low,
It only needs primary etching and an extension that can complete, reduces device manufacturing cost.
The manufacturing method of power device protection chip in the present embodiment, is mutually handed over front groove 2 and backside trench 2
It is illustrated for mistake arrangement, and front groove 2 and the manufacturing method of the arrangement facing each other of backside trench 2 are almost the same therewith, it is different
When place is etching groove 2, the arrangement mode of groove 2 is different.It is specific the following steps are included:
S1. the silicon single crystal 1 with first conduction type in front and the back side opposite with front is provided, in front and back
Several grooves 2 are etched, the quantity of front groove 2 is equal with the quantity of backside trench 2, as shown in Figure 2；
Specifically, the present embodiment use, which is dry-etched in 1 obverse and reverse of silicon single crystal, forms groove 2, and front groove 2
Quantity it is equal with the quantity of backside trench 2, form 1 group of longitudinal direction diode structure between front and the back side in this way, and require
Horizontal spacing between groove 2 is greater than the width of groove 2, and the horizontal spacing between more specific groove 2 is greater than 3 times of groove 2
Width, can guarantee that element leakage is smaller in this way, and guarantee current density distribution uniformity.
Wherein the first conduction type is N-type conductive material, and the second conduction type is P-type conduction material.
S2. oxide layer 3 is formed in the inner sidewall of front, the back side, groove 2, as shown in Figure 3；
Specifically, in this step, by by 1 thermal oxide of silicon single crystal front, the back side, groove 2 interior side-wall surface shape
At silicon oxide layer, wherein oxidate temperature is 1100 DEG C~1200 DEG C, removes the oxygen of 2 bottom of groove by dry etching again later
SiClx layer exposes 2 bottom of groove with spare, as shown in Figure 4.
S3. the first diffusion region 4 of the first conduction type is formed in the bottom of groove 2, as shown in Figure 5；
Specifically, in this step, first forming first in the ion implanting that the bottom of groove 2 carries out the first conduction type and leading
The injection region of electric type, then nitrogen and hydrogen it is mixed gas protected under carry out at 1200 DEG C at least 60 minutes thermal annealings,
Form the first diffusion region 4, wherein the ion implantation dosage of the first conduction type is greater than 1E15, and energy is greater than 30KeV, is less than
120KeV.Wherein the first conduction type is N-type conductive material.
S4. the epitaxial layer 5 of the second conduction type is filled in groove 2, as shown in Figure 6；
Specifically, forming epitaxial layer using the material that the common method in this field fills the second conduction type in groove 2
5, wherein the second conduction type is P-type conduction material.P-type extension is formed namely in groove 2.
S5. the second diffusion region 6 of the second conduction type is formed on epitaxial layer 5, as shown in Figure 7；
Specifically, the top of the p-type extension in groove 2, continues to spread, condition be temperature be 800 DEG C~
1000 DEG C and time are the diffusion that p-type is carried out under conditions of 30~40 minutes, form the second diffusion region 6 of p-type.
S6. the first metal layer 7, oxide layer 3 overleaf and in positive oxide layer 3 and the second diffusion region 6 are formed
With on the second diffusion region 6 formed second metal layer 8, as shown in Figure 8.
Specifically, the present invention is respectively formed the first metal layer in the front and back of device using the conventional method of this field
7 and second metal layer 8, wherein the first metal layer 7 covers the positive oxide layer 3 for not performing etching groove 2 and of device
Two diffusion regions 6, second metal layer 8 cover the oxide layer 3 for not performing etching groove 2 and second diffusion region 6 at the back side of device,
The first metal layer 7 of the invention and second metal layer 8 are using conventional method preparation.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent substitution, improvement and etc. done be should be included within the scope of the present invention.
Claims (10)
1. a kind of power device protects chip, which is characterized in that it includes the silicon single crystal of the first conduction type, the silicon single crystal packet
Front and the back side opposite with front are included, the front and the back side are etched with several grooves, described positive, described
The side wall of the back side and the groove is each formed with oxide layer, and the bottom of the groove is formed with the first diffusion of the first conduction type
Area is filled with the epitaxial layer of the second conduction type in the groove, is formed with the of the second conduction type on said epitaxial layer there
Two diffusion regions are formed with the first metal layer in the positive oxide layer and the second diffusion region, the oxide layer at the back side
Second metal layer is formed with on the second diffusion region.
2. power device according to claim 1 protects chip, which is characterized in that the quantity of the positive groove is many
Horizontal spacing between 3, the quantity of the backside trench groove equal with the quantity of the positive groove
Greater than the width of the groove.
3. power device according to claim 1 protects chip, which is characterized in that the positive groove and the back side
Groove be staggered.
4. power device according to claim 1 protects chip, which is characterized in that the positive groove and the back side
Groove face arrangement.
5. power device according to claim 1 protects chip, which is characterized in that first diffusion region passes through injection the
It is diffuseed to form after the ion of one conduction type.
6. a kind of manufacturing method of power device protection chip, which is characterized in that at least include the following steps:
The silicon single crystal with first conduction type in front and the back side opposite with front is provided, at the front and the back side
Several grooves are etched, the quantity of the front groove is equal with the quantity of the backside trench；
Oxide layer is formed in the inner sidewall of the front, the back side, the groove；
The first diffusion region of the first conduction type is formed in the bottom of the groove；
The epitaxial layer of the second conduction type is filled in the groove；
The second diffusion region of the second conduction type is formed on said epitaxial layer there；
And the first metal layer is formed in the positive oxide layer and the second diffusion region, in the oxide layer at the back side and
Second metal layer is formed on two diffusion regions.
7. the manufacturing method of power device according to claim 6 protection chip, which is characterized in that using being dry-etched in
The front and several described grooves of the back-etching, the horizontal spacing between the groove are greater than the width of the groove
Degree.
8. the manufacturing method of power device protection chip according to claim 6, which is characterized in that in the front, institute
State the back side, the groove inner sidewall formed oxide layer the step of in, by the way that the silicon single crystal thermal oxide is formed on its surface
Silicon oxide layer, wherein oxidate temperature is 1100 DEG C~1200 DEG C, then removes the described of the channel bottom by dry etching
Silicon oxide layer.
9. the manufacturing method of power device protection chip according to claim 6, which is characterized in that at the bottom of the groove
Portion was formed in the step of first diffusion region, was first formed in the ion implanting that the bottom of the groove carries out the first conduction type
The injection region of first conduction type, then nitrogen and hydrogen it is mixed gas protected under carry out at 1200 DEG C at least 60 minutes heat
Annealing forms first diffusion region, wherein the ion implantation dosage of the first conduction type is greater than 1E15, and energy is greater than
30KeV is less than 120KeV.
10. the manufacturing method of power device protection chip according to claim 6, which is characterized in that in the epitaxial layer
It is upper to be formed in second diffusion region step, under conditions of temperature is 800 DEG C~1000 DEG C and the time is 30~40 minutes into
The diffusion of the second conduction type of row forms second diffusion region of the second conduction type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811168564.0A CN109326591B (en) | 2018-10-08 | 2018-10-08 | Power device protection chip and manufacturing method thereof |
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|---|---|---|---|
| CN201811168564.0A CN109326591B (en) | 2018-10-08 | 2018-10-08 | Power device protection chip and manufacturing method thereof |
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| CN109326591B CN109326591B (en) | 2020-09-22 |
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| CN109326591B (en) | 2020-09-22 |
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