CN109285762B - Edge processing technology for silicon wafer for gallium nitride epitaxy - Google Patents
Edge processing technology for silicon wafer for gallium nitride epitaxy Download PDFInfo
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Abstract
The invention discloses a silicon wafer edge processing technology for gallium nitride epitaxy. After the silicon single crystal is sliced, the first coarse chamfering is carried out by a 1000-mesh grinding wheel to remove the damage of the edge slicing processing, and then grinding and corrosion are carried out, so that the silicon wafer has better edge quality; the surface is protected by the back-sealed silicon dioxide, so that surface damage and contamination caused by a sucking disc and a grinding wheel during secondary chamfering are avoided, and meanwhile, the stress of the edge is released in a high-temperature process; and a grinding wheel of 2000 meshes is adopted for secondary fine chamfering, so that the chamfering surface width reaches the maximum and a finer surface is provided, and surface damage and edge stress are removed through slight corrosion of 50% potassium hydroxide solution, and the optimal chamfering edge quality is obtained. The method is simple and easy to realize, and can effectively improve the quality of the chamfer edge area of the silicon single crystal polished wafer.
Description
Technical Field
The invention relates to a semiconductor material processing technology, in particular to a silicon wafer edge processing technology for gallium nitride epitaxy.
Background
Gallium nitride has the characteristics of high saturated electron rate, breakdown voltage, high temperature resistance and the like, can be used for manufacturing high-temperature high-frequency high-power electronic devices (FET, HEMT) which operate in extremely severe environment, and is applied to the fields of wireless communication (wireless station), satellite communication and the like. Especially in the last decade, wide bandgap semiconductor materials and devices represented by GaN have been developed rapidly and have been a great impetus for the development and application of information science and technology. Therefore, the preparation of GaN epitaxial materials and devices is a popular research topic at present, and various domestic research institutions and universities focus on the research of epitaxial technology and the improvement of device performance, and have made a breakthrough as the most promising silicon-based gallium nitride epitaxial technology and applied to production. And silicon substrates, particularly 6-inch silicon substrate materials, which are special materials, are currently heavily dependent on imports. Most of domestic large silicon wafer manufacturers concentrate on discrete device silicon wafers and silicon epitaxial substrate wafers, the particularity of gallium nitride epitaxy is not sufficiently known, corresponding design experience and unified technical standard are lacked, and the improvement of the preparation level of the substrate is seriously restricted.
At present, the main problems of the gallium nitride epitaxial wafer for the domestic power device are mostly concentrated in the edge region of the polished wafer, which is shown as serious edge slip lines, edge epitaxial layer melting, edge mechanical damage and the like, and has a direct relation with the quality of the chamfer edge region of the silicon substrate polished wafer before epitaxy. The common chamfer is formed by processing a coarse chamfer of an 800# grinding wheel and a fine chamfer of a 1500# grinding wheel, the removal amount is 50-60 mu m after chamfering, the edge impact during grinding causes the edge of the chamfer to be newly damaged, and the chamfer width is reduced by about 100 mu m; when chemical etching is carried out, the chamfer edge area is a combination of a plurality of crystal orientation crystal faces, the consistency of the etching rate is poor, the mechanical damage etching pits on the edge are easily enlarged, the edge chamfer outline becomes sharp, the surface width is further reduced, and the quality of the edge area after polishing is further poor. After the high-temperature epitaxy of gallium nitride, the serious slip lines and even splinters are caused by serious lattice mismatch and difficult stress relief. How to reduce the mechanical damage of the chamfer edge, ensure the maximum value of the chamfer width as far as possible and release the edge processing stress becomes a difficult problem for developing the silicon substrate for the gallium nitride epitaxy. The quality control of the chamfer edge is a system project which relates to multiple processes of slicing, rounding, chamfering, grinding, corrosion, polishing and the like, is difficult to realize only by improving the chamfering process, and the whole processing process needs to be redesigned.
Disclosure of Invention
In view of the prior art, the invention provides a simple, effective and easily realized edge processing process for a high-quality silicon substrate for gallium nitride epitaxy aiming at the particularity of the silicon substrate for gallium nitride epitaxy. According to the invention, the damage of edge slicing processing is removed through the coarse chamfer, and then grinding and corrosion are carried out, so that the silicon wafer has better edge quality; the surface is protected by the back-sealed silicon dioxide, so that surface damage and contamination caused by twice chamfering are avoided, and the stress of the edge is released in the high-temperature process; and performing secondary fine chamfering to enable the chamfer breadth to reach the initial chamfer design value and have a more fine surface, and removing surface damage and edge stress through light corrosion to achieve the best surface quality.
The technical scheme adopted by the invention is as follows: a process for processing the edge of a silicon wafer for gallium nitride epitaxy is characterized in that: the silicon single crystal is cut into a silicon wafer and then is subjected to first coarse chamfering processing, then the silicon wafer is ground and chemically corroded, the silicon wafer is ground and corroded and then is subjected to back sealing silicon dioxide as a surface protection layer, then secondary fine chamfering is carried out, alkali solution is adopted for light corrosion after the fine chamfering, the surface is protected from being contaminated, meanwhile, the chamfer width of a polished wafer is increased to the maximum extent, and edge damage is avoided, and the process is as follows:
(1) and carrying out outer diameter rounding on the silicon single crystal, wherein the rounding diameter is as follows: 151.2 + -0.2 mm.
(2) And carrying out multi-wire cutting on the silicon single crystal, wherein the slicing thickness is as follows: 1100 μm. + -. 20 μm.
(3) And carrying out coarse chamfering on the silicon slice by adopting a full-automatic chamfering machine, wherein the ring removal amount is 0.2 mm.
(4) And carrying out double-sided grinding by adopting alumina powder, wherein the grinding removal amount is 50 +/-5 microns.
(5) And performing double-sided corrosion by adopting an acid corrosion process, wherein the corrosion removal amount is 30 +/-5 mu m.
(6) Adopting LPCVD technology to seal silicon dioxide on both sides, wherein the back sealing temperature is 700 ℃, and the thickness of the silicon dioxide layer is as follows: 3000 +/-1000A.
(7) And carrying out secondary fine chamfering on the silicon wafer with the silicon dioxide back sealed on the two sides by adopting a full-automatic chamfering machine, wherein the ring removing amount is 0.1 mm.
(8) And carrying out alkali corrosion by adopting a potassium hydroxide solution with the concentration of 50% +/-5%.
(9) And etching off the silicon dioxide on the surface by adopting hydrofluoric acid solution with the concentration of 49 +/-10%, and polishing the single surface after cleaning.
In the step (3), rough chamfering is performed, a 1000-mesh R-shaped chamfering grinding wheel is adopted, and the R value is as follows: 0.508mm, angle 22 ° ± 1 °, grinding wheel speed: 4000 ± 500RPM, suction cup speed: 10 + -2 mm/s, chamfer diameter: 150.4 +/-0.2 mm.
In the step (4), alumina powder with the particle size of 8 +/-0.5 microns is adopted for double-side grinding.
In the step (7), the second fine chamfering is performed, a 2000-mesh R-type chamfering grinding wheel is adopted, and the R value is as follows: 0.508mm, angle 22 ° ± 1 °, grinding wheel speed: 4000 ± 500RPM, suction cup speed: 10 + -2 mm/s, chamfer diameter: 150.0 +/-0.2 mm.
In the step (8), the alkali corrosion is carried out, and the corrosion temperature is as follows: 90 +/-5 ℃ and the corrosion time is 10 s.
The invention has the advantages and beneficial effects that: by adopting the process, the precision processing of the silicon substrate chamfer edge for the gallium nitride can be realized on a general silicon product processing line, the consistency and the maximization of the surface width of the chamfer on the two sides are ensured, the surface contamination and scratch caused by a sucker and a grinding wheel during the second chamfering are avoided, the quality of the edge area of the polished wafer is optimal under the condition that the edge polishing cannot be realized, and the requirement of the quality of the epitaxial edge of the gallium nitride is met. The method can be widely applied to the processing of 4-6 inches of silicon substrate for gallium nitride.
Detailed Description
The invention is further illustrated by the following examples:
example (b): specification of silicon single crystal: p-type <111> boron doping with resistivity: 0.002-0.005 Ω · cm, diameter: ≧ 153 mm. The specific implementation steps are as follows:
(1) performing outer diameter rounding on the silicon single crystal, wherein the rounding diameter is as follows: 151.2 + -0.2 mm.
(2) Carrying out multi-wire cutting on the silicon single crystal, wherein the slicing thickness is as follows: 1100 μm. + -. 20 μm.
(3) Adopt full-automatic beveler to carry out coarse chamfering to the silicon section, adopt 1000 mesh R type chamfer emery wheel, R value: 0.508mm, angle 22 ° ± 1 °, grinding wheel speed: 4000RPM, suction cup speed: 10mm/s, the loop removal amount is 0.2mm, the loop removal amount refers to the removal amount of the silicon wafer rotating with the sucker for one circle, the total removal amount is 0.8mm, and the target diameter is as follows: 150.4 +/-0.2 mm.
(4) Double-side grinding is carried out by adopting 8-micron alumina powder, and the grinding removal amount is 50 microns.
(5) And performing double-sided corrosion by adopting an acid corrosion process, wherein the corrosion removal amount is 30 mu m.
(6) Adopting LPCVD technology to back seal silicon dioxide on both sides, wherein the back sealing temperature is 700 ℃, and the thickness of the silicon dioxide layer is as follows: 3000 +/-1000A.
(7) Adopting full-automatic beveler to carry out the fine chamfering of second time to the silicon chip of back sealing silica, adopting 2000 meshes R type chamfer emery wheel, R value: 0.508mm, angle 22 ° ± 1 °, grinding wheel speed: 4000RPM, suction cup speed: 10mm/s, loop removal 0.1mm, total removal 0.4mm, target diameter: 150.0 +/-0.2 mm.
(8) Carrying out alkali corrosion by adopting a potassium hydroxide solution with the concentration of 50%, wherein the corrosion temperature is as follows: and the corrosion time is 10s at 90 ℃.
(9) And etching off the silicon dioxide on the surface by adopting hydrofluoric acid solution with the concentration of 49%, and polishing the single surface after cleaning.
Through the process, after silicon single crystal is sliced, the damage of edge slicing processing is removed through a 1000-mesh grinding wheel for the first coarse chamfering, and then grinding and corrosion are carried out, so that the silicon wafer has better edge quality; the surface is protected by the back-sealed silicon dioxide, so that surface damage and contamination caused by a sucking disc and a grinding wheel during secondary chamfering are avoided, and meanwhile, the stress of the edge is released in a high-temperature process; and a grinding wheel of 2000 meshes is adopted for secondary fine chamfering, so that the chamfering surface width reaches the maximum and a finer surface is provided, and surface damage and edge stress are removed through slight corrosion of 50% potassium hydroxide solution, and the optimal chamfering edge quality is obtained. The method is simple and easy to realize, and can effectively improve the quality of the chamfer edge area of the silicon single crystal polished wafer.
And (3) technical effect inspection: and (3) inspecting after polishing the silicon wafer, wherein the surface of the polished wafer is qualified, the back surface of the polished wafer is free from dirt and scratches, the edge of the chamfer is smooth, a boundary area between the polished surface and the chamfer edge is free from dirt, damage and corrosion pits, the edge is observed to be smooth and not damaged under a microscope, the face width of the chamfer on the front surface is 480 mu m, the face width of the chamfer on the back surface is 530 mu m, and the edge of the gallium nitride after extension is free from melt back, slip lines and cracks.
The test results show that: the silicon dioxide back seal is adopted for surface protection, and secondary fine chamfering is carried out after corrosion, so that the quality of the chamfer edge area of the polished wafer can be greatly improved, and the method has important application significance in special product processes.
Claims (5)
1. A process for processing the edge of a silicon wafer for gallium nitride epitaxy is characterized in that: the silicon single crystal is cut into a silicon wafer and then is subjected to first coarse chamfering processing, then the silicon wafer is ground and chemically corroded, the silicon wafer is ground and corroded and then is subjected to back sealing silicon dioxide as a surface protection layer, then secondary fine chamfering is carried out, alkali solution is adopted for light corrosion after the fine chamfering, the surface is protected from being contaminated, meanwhile, the chamfer width of a polished wafer is increased to the maximum extent, and edge damage is avoided, and the process is as follows:
(1) and carrying out outer diameter rounding on the silicon single crystal, wherein the rounding diameter is as follows: 151.2 plus or minus 0.2 mm;
(2) and carrying out multi-wire cutting on the silicon single crystal, wherein the slicing thickness is as follows: 1100 microns +/-20 microns;
(3) performing coarse chamfering on the silicon slices by using a full-automatic chamfering machine, wherein the ring removal amount is 0.2 mm;
(4) carrying out double-sided grinding by adopting alumina powder, wherein the grinding removal amount is 50 +/-5 mu m;
(5) performing double-sided corrosion by adopting an acid corrosion process, wherein the corrosion removal amount is 30 +/-5 mu m;
(6) adopting LPCVD technology to seal silicon dioxide on both sides, wherein the back sealing temperature is 700 ℃, and the thickness of the silicon dioxide layer is as follows: 3000 +/-1000A;
(7) performing secondary fine chamfering on the silicon wafer with the silicon dioxide back-sealed on the two sides by using a full-automatic chamfering machine, wherein the ring removal amount is 0.1 mm;
(8) carrying out alkali corrosion by adopting a potassium hydroxide solution with the concentration of 50% +/-5%;
(9) and etching off the silicon dioxide on the surface by adopting hydrofluoric acid solution with the concentration of 49 +/-10%, and polishing the single surface after cleaning.
2. The process of claim 1, wherein the step of edge processing comprises: and (3) performing rough chamfering, wherein a 1000-mesh R-shaped chamfering grinding wheel is adopted, and the R value is as follows: 0.508mm, angle 22 ° ± 1 °, grinding wheel speed: 4000 ± 500RPM, suction cup speed: 10 + -2 mm/s, chamfer diameter: 150.4 +/-0.2 mm.
3. The process of claim 1, wherein the step of edge processing comprises: and (4) carrying out double-side grinding by adopting alumina powder with the particle size of 8 +/-0.5 microns.
4. The process of claim 1, wherein the step of edge processing comprises: and (3) carrying out secondary fine chamfering in the step (7), wherein a 2000-mesh R-shaped chamfering grinding wheel is adopted, and the R value is as follows: 0.508mm, angle 22 ° ± 1 °, grinding wheel speed: 4000 ± 500RPM, suction cup speed: 10 + -2 mm/s, chamfer diameter: 150.0 +/-0.2 mm.
5. The process of claim 1, wherein the step of edge processing comprises: performing alkali corrosion in the step (8), wherein the corrosion temperature is as follows: 90 +/-5 ℃ and the corrosion time is 10 s.
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| CN117116740A (en) * | 2023-08-02 | 2023-11-24 | 山东有研半导体材料有限公司 | Processing technology of large-size wafer edge |
| CN117161839B (en) * | 2023-11-01 | 2024-02-06 | 山东有研艾斯半导体材料有限公司 | Method for improving mechanical damage of edge of silicon polishing sheet |
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