CN108877627A

CN108877627A - Shift register cell and driving method, gate driving circuit, display device

Info

Publication number: CN108877627A
Application number: CN201810775889.9A
Authority: CN
Inventors: 冯雪欢; 李永谦
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2018-07-13
Filing date: 2018-07-13
Publication date: 2018-11-23
Anticipated expiration: 2038-07-13
Also published as: CN108877627B; US10923008B2; US20200020266A1

Abstract

A kind of shift register cell provided in an embodiment of the present invention and driving method, gate driving circuit, display device, are related to field of display technology, be able to solve existing GOA circuit because structure is complicated and be unable to satisfy display device to narrow frame demand the problem of；Output unit includes in the shift register cell：The first output module being connect with the first signal output end, the second output module being connect with second signal output end；First signal output end and second signal output end are for connecting different grid lines；Drop-down unit includes：First pull-down module, the second pull-down module；Output unit is connect with pull-up node, and drop-down unit is connect with pull-down node；Pull-up node is sequentially output the first working signal and the second working signal for controlling the first signal output end and second signal output end；Pull-down node stops the first working signal of output and the second working signal for controlling the first signal output end and second signal output end.

Description

Shift register cell and driving method, gate driving circuit, display device

Technical field

The present invention relates to field of display technology more particularly to a kind of shift register cells and driving method, gate driving Circuit, display device.

Background technique

(Thin Film Transistor Liquid Crystal Display, Thin Film Transistors-LCD are aobvious by TFT-LCD Show device) and OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode), it is applied to more and more In high-performance display field, and in order to improve the screen accounting of display device, gate driving in the prior art as far as possible Circuit is usually arranged as GOA (Gate Driver on Array, the driving of array substrate row) circuit.

Shift register cell in existing GOA circuit includes detection unit, display unit and connection unit, in this way The structure of circuit is extremely complex, and area occupied is larger, to be unable to satisfy demand of the high-definition display device to narrow frame.

Summary of the invention

The embodiment of the present invention provides a kind of shift register cell and driving method, gate driving circuit, display device, Be able to solve existing GOA circuit because structure is complicated and be unable to satisfy display device to narrow frame demand the problem of.

In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that：

The embodiment of the present invention provides a kind of shift register cell, and the shift register cell includes：Pull-up control is single Member, drop-down control unit, output unit, drop-down unit；The output unit includes：First connect with the first signal output end Output module, the second output module being connect with second signal output end；First signal output end and the second signal Output end is for connecting different grid lines；The drop-down unit includes：The first drop-down being connect with first signal output end Module, the second pull-down module being connect with the second signal output end；First output module in the output unit It is connect with pull-up node with second output module, first pull-down module and described second in the drop-down unit Pull-down module is connect with pull-down node；The pull-up control unit and the pull-up node, the pull-down node, signal input End connection, the pull-up control unit is for controlling the pull-up node；The drop-down control unit and the drop-down save Point, the pull-up node, the connection of the first reset signal end, the drop-down control unit is for controlling the pull-down node； The pull-up node is sequentially output the first work letter for controlling first signal output end and the second signal output end Number and the second working signal；The pull-down node is used to control first signal output end and the second signal output end stops Only export first working signal and second working signal；The pull-up control unit is by controlling the pull-up section Point, so control first working signal that first signal output end and the second signal output end are sequentially output and Second working signal is respectively：First scanning signal and the second scanning signal.

Optionally, the shift register cell further includes：Detect control unit；The detecting control unit and it is described on Node, signal input part connection are drawn, for controlling the pull-up node；The detecting control unit passes through control The pull-up node, and then control first signal output end and the second signal output end are sequentially output described first Working signal and second working signal are respectively：First detection signal and the second detection signal.

Optionally, the output unit further includes：Cascaded-output module；The drop-down unit further includes：Cascade lower drawing-die Block；The cascaded-output module is connect with the pull-up node, cascade signal output end, for the control in the pull-up node Under, first working signal and described second are sequentially output in first signal output end and the second signal output end While working signal, output cascade signal；The cascade pull-down module and the pull-down node, the cascade signal output end Connection, for stopping under the control of the pull-down node in first signal output end and the second signal output end While exporting first working signal and second working signal, controls the cascade signal output end and stop output institute State cascade signal；Wherein, the cascade signal output end is for cascading multiple shift register cells.

Optionally, the pull-up control unit includes：First pull-up control module, the second pull-up control module, first are answered Position module, the first energy-storage module；Wherein, the first pull-up control module and the signal input part, first voltage end, described Pull-up node connection, under the control of the signal input part by the voltage output at the first voltage end to the pull-up Node；The second pull-up control module is connect with the pull-down node, the pull-up node, second voltage end, in institute Under the control for stating pull-down node, by the voltage output at the second voltage end to the pull-up node；First reseting module It is connect with the second voltage end, the pull-up node, first reset signal end, at first reset signal end Control under, by the voltage output at the second voltage end to the pull-up node；First energy-storage module and the pull-up Node connection, for storing the voltage of the pull-up node, or discharges to the pull-up node.

Optionally, the drop-down control unit includes：First pull-down control module, the second pull-down control module；Wherein, institute It states the first pull-down control module to connect with the pull-down node and first control signal end, at the first control signal end Control under, the first control signal at the first control signal end is exported to the pull-down node；The second drop-down control Molding block is connect with the pull-up node, the pull-down node, the second voltage end, for the control in the pull-up node Under, by the voltage output at the second voltage end to the pull-down node.

Optionally, in the case where the shift register cell includes detecting control unit, the detecting control unit Including：Detect input module, the second energy-storage module, energy storage control module and the second reseting module；Wherein, the detecting inputs mould Block is connect with the signal input part, second clock signal end, first node, for the control in the second clock signal end Under, the signal of the signal input part is exported to the first node；Second energy-storage module and the first node connect It connects, for storing the voltage of the first node, or discharges the first node；The energy storage controls mould Block is connect with the first clock signal terminal, third clock signal terminal, the first node, the pull-up node, for described the Under the control of one node and first clock signal terminal, the third clock signal of the third clock signal terminal is exported to institute State pull-up node；Second reseting module is connect with the pull-up node, the second voltage end, the second reset signal end, For the control at second reset signal end by the voltage output at the second voltage end to the pull-up node.

Optionally, in the output unit, the cascaded-output module and the pull-up node, the 4th clock signal terminal, Cascade signal output end connection, under the control of the pull-up node, by the 4th of the 4th clock signal terminal the Clock signal is exported to the cascade signal output end；First output module and the pull-up node, the 5th clock signal End, first signal output end connection, under the control of the pull-up node, by the of the 5th clock signal terminal Five clock signals are exported to first signal output end；Second output module and the pull-up node, the 6th clock are believed Number end, second signal output end connection, under the control of the pull-up node, by the 6th clock signal terminal 6th clock signal is exported to the second signal output end.

Optionally, in the drop-down unit, the cascade pull-down module and the pull-down node, the second voltage end, Cascade signal output end connection, under the control of the pull-down node, by the voltage output at the second voltage end To the cascade signal output end；First pull-down module and the pull-down node, the tertiary voltage end, first letter Number output end connection, under the control of the pull-down node, by the voltage output at the tertiary voltage end to described first Signal output end；Second pull-down module and the pull-down node, the tertiary voltage end, the second signal output end connect It connects, under the control of the pull-down node, by the voltage output at the tertiary voltage end to the second signal output end.

Optionally, in the pull-up control unit：The first pull-up control module includes the first transistor；Described The grid of one transistor and the signal input part, the first pole and the first voltage end, the second pole and the pull-up node connect It connects；The second pull-up control module includes second transistor；The grid of the second transistor and the pull-down node, first Pole is connect with the second voltage end, and the second pole is connect with the pull-up node；First reseting module includes third crystal Pipe；The grid of the third transistor is connect with first reset signal end, and the first pole is connect with the second voltage end, the Two poles are connect with the pull-up node；The energy-storage module includes first capacitor；One end of the first capacitor and the pull-up Node connection, the other end are connect with the cascade signal output end.

Optionally, in the drop-down control unit：First pull-down control module includes the 4th transistor；Described The grid of four transistors is connect with the first pole with the first control signal end, and the second pole is connect with the pull-down node；It is described Second pull-down control module includes the 5th transistor, and the grid of the 5th transistor is connect with the pull-up node, the first pole It is connect with the second voltage end, the second pole is connect with the pull-down node.

Optionally, in the detecting control unit：The detecting input module includes the 6th transistor；Described 6th is brilliant The grid of body pipe is connect with the second clock signal end, and the first pole is connect with the signal input part, the second pole and first segment Point connection；Second energy-storage module includes the second capacitor, and the first end of second capacitor is connect with the first node, the Two ends are connect with the second voltage end；The energy storage control module includes：7th transistor, the 8th transistor；Described seven is brilliant The grid of body pipe is connect with the first node, and the first pole is connect with the third clock signal terminal, the second pole and the described 8th First pole of transistor connects；The grid of 8th transistor is connect with first clock signal terminal, the second pole with it is described Pull-up node connection；Second reseting module includes the 9th transistor；The grid of 9th transistor is multiple with described second Position signal end connection, the first pole are connect with the second voltage end, and the second pole is connect with the pull-up node.

Optionally, in the output unit：The first output mould includes the tenth transistor；Tenth transistor Grid is connect with the pull-up node, and the first pole is connect with the 5th clock signal terminal, the second pole and first signal output end Connection；Second output module includes the 11st transistor；The grid of 11st transistor and the pull-up node connect It connects, the first pole is connect with the 6th clock signal terminal, and the second pole is connect with the second signal output end；The cascaded-output module Including the 14th transistor；The grid of 14th transistor is connect with the pull-up node, and the first pole and the 4th clock are believed Number end connection, the second pole is connect with the cascade signal output end.

Optionally, in the drop-down unit：First pull-down module includes the tenth two-transistor；Described 12nd is brilliant The grid of body pipe is connect with the pull-down node, and the first pole is connect with the tertiary voltage end, the second pole and first signal Output end connection；Second pull-down module includes the 13rd transistor；The grid of 13rd transistor and the drop-down Node connection, the first pole are connect with the tertiary voltage end, and the second pole is connect with the second signal output end；Under the cascade Drawing-die block includes the 15th transistor；The grid of 15th transistor is connect with the pull-down node, the first pole and second Voltage end connection, the second pole is connect with the cascade signal output end.

Optionally, the output unit further includes：Third output module and the 4th output module；The drop-down unit is also wrapped It includes：Third pull-down module and the 4th pull-down module；The third output module includes the 16th transistor；16th crystal The grid of pipe is connect with the pull-up node, and the first pole is connect with the 7th clock signal terminal, and the second pole and the first additional signal are defeated Outlet connection；And the first additional signal output end and first signal output end are corresponding with a line sub-pix for connecting In different grid lines；4th output module includes the 17th transistor；The grid of 17th transistor and it is described on Node connection is drawn, the first pole is connect with the 8th clock signal terminal, and the second pole is connect with the second additional signal output end；And described Two additional signal output ends and the second signal output end are corresponding with the different grid lines in a line sub-pix for connecting；It is described Third pull-down module includes the 18th transistor；The grid of 18th transistor is connect with the pull-down node, the first pole It is connect with the tertiary voltage end, the second pole is connect with the first additional signal output end；4th pull-down module includes 19th transistor；The grid of 19th transistor is connect with the pull-down node, the first pole and the tertiary voltage end Connection, the second pole is connect with the second additional signal output end.

Optionally, the drop-down control unit further includes：First drop-down control replacement module；The first drop-down control is replaced Changing the mold block includes replacement transistor；The grid of the replacement transistor and the first pole are connect with replacement control signal end, the second pole It is connect with the pull-down node；When the replacement control signal of the replacement control signal end is high potential, the first control letter Number end first control signal be low potential；When the replacement control signal of the replacement control signal end is low potential, described the The first control signal of one control signal end is high potential.

Optionally, the second voltage end is different voltage ends from the tertiary voltage end；The second voltage end with The tertiary voltage end is low level voltage end, and the voltage at the second voltage end is less than the electricity at the tertiary voltage end Pressure.

The embodiment of the present invention also provides a kind of gate driving circuit, the shift LD as the aforementioned including at least two-stage cascade Device unit；The signal input part of first order shift register cell is connected with initial signal end；In addition to the first order shifts Other than register cell, the first signal output end of upper level shift register cell and the letter of next stage shift register cell Number input terminal is connected；Other than afterbody shift register cell, the first signal of next stage shift register cell Output end is connected with the first reset signal end of upper level shift register cell；Alternatively, in the grade shift register list In the case that member includes cascade signal output end, other than the first order shift register cell, upper level shift LD The cascade signal output end of device unit is connected with the signal input part of next stage shift register cell；In addition to afterbody moves Other than bit register unit, cascade signal output end and the upper level shift register cell of next stage shift register cell First reset signal end is connected；First reset signal end of the afterbody shift register cell and termination signal end phase Connection.

Optionally, in the case where the shift register cell includes four clock signal terminal, positioned at the shifting of odd level 4th clock signal terminal of bit register unit is connect with the 4th clock signal terminal of the shift register cell for being located at even level The 4th different clock cables.

The embodiment of the present invention also provides a kind of display device, including gate driving circuit above-mentioned；In the display device The grid line being arranged successively according to two one group, be divided into the multiple grid line groups being arranged successively, and in each grid line group include according to The first grid line and the second grid line of secondary arrangement；In the gate driving circuit successively cascade shift register cell respectively with institute State the grid line group connection being arranged successively in display device.

The embodiment of the present invention also provides a kind of for driving the driving method of shift register cell as the aforementioned, an image Frame includes display stage and the reconnaissance phase after the display stage；

Within the display stage, the driving method includes：First stage, to signal input part input the first input letter Number；First pull-up control module under the control of first input signal by the voltage output at first voltage end to pull up section Point, and stored by the first energy-storage module；Under the control of the pull-up node, by the inoperative electricity of the 5th clock signal terminal Pressure output exports the nonoperating voltage of the 6th clock signal terminal to second signal output end to the first signal output end, by the The nonoperating voltage of four clock signal terminals is exported to cascade signal output end, to be reset.

Second stage, the first energy storage mould discharge to the pull-up node, and under the control of the pull-up node, It exports the operating voltage of the 5th clock signal terminal as the first scanning signal to first signal output end, it will be described The operating voltage of 6th clock signal terminal is exported as the second scanning signal to the second signal output end, when by the described 4th The operating voltage of clock signal end is exported as cascade signal to the cascade signal output end.

Phase III inputs the first reset signal to the first reset signal end, and in the control of first reset signal The lower voltage output by second voltage end to the pull-up node resets；To first control signal end input the first control letter Number, the first control signal is exported to drop-down and is saved under the control of the first control signal by the first pull-down control module Point, and under the control of the pull-down node, by the voltage output at tertiary voltage end to first signal output end and described Binary signal output end, by the voltage output at second voltage end to the cascade signal output end, to be resetted.

In the reconnaissance phase, the driving method further includes：

Fourth stage inputs the first clock signal to the first clock signal terminal, when inputting third to third clock signal terminal Clock signal, and the second energy storage mould discharges to first node, in the control of the first node and first clock signal Under system, energy storage control module exports the third clock signal to the pull-up node；And under the control of the pull-up node, It exports the operating voltage of the 5th clock signal terminal as the first detection signal to first signal output end, it will be described The operating voltage of 6th clock signal terminal is exported as the second detection signal to the second signal output end.

5th stage inputted the second reset signal to the second reset signal end, under the control of second reset signal, Second reseting module is by the voltage output at second voltage end to the pull-up node；To first control signal end input first Control signal, the first pull-down control module under the control of the first control signal, by the first control signal export to The pull-down node, and under the control of the pull-down node, the voltage output at tertiary voltage end to first signal is exported End and the second signal output end, by the voltage output at second voltage end to the cascade signal output end, to be resetted.

The embodiment of the present invention provides a kind of shift register cell and driving method, gate driving circuit, display device, should Shift register cell includes：Output unit, drop-down unit, pull-up control unit, drop-down control unit；Output unit includes： The first output module being connect with the first signal output end, the second output module being connect with second signal output end；First letter Number output end and second signal output end are for connecting different grid lines；Drop-down unit includes：It is connect with the first signal output end The first pull-down module, the second pull-down module being connect with second signal output end；The first output module in output unit and Second output module is connect with pull-up node, the first pull-down module and the second pull-down module and pull-down node in drop-down unit Connection；Pull-up control unit is connect with pull-up node, pull-down node, signal input part, which is used for pull-up Node is controlled；Drop-down control unit is connect with pull-down node, pull-up node, the first reset signal end, and drop-down control is single Member is for controlling pull-down node；Pull-up node is successively defeated for controlling the first signal output end and second signal output end First working signal and the second working signal out；Pull-down node is stopped for controlling the first signal output end and second signal output end Only export the first working signal and the second working signal；Pull-up control unit controls the first letter by control pull-up node The first working signal and the second working signal that number output end and second signal output end are sequentially output be respectively：First scanning letter Number and the second scanning signal.

In summary, it is to be understood that need to be separately provided displacement for each grid line in compared with the prior art and post Storage unit, cause GOA circuit structure complicated and for being unable to satisfy display device to the narrow frame demand the problem of, in the present invention By by two shift register cells in for control pull-up node, the pull-up control unit of pull-down node, drop-down control Unit carries out shared, and forming a tool can so meet there are two the new shift register cell of signal output end While normally exporting scanning signal step by step to grid line, GOA circuit can be simplified, so that the narrow frame for being conducive to display device is set Meter.

Detailed description of the invention

In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with It obtains other drawings based on these drawings.

Fig. 1 is a kind of module diagram of shift register cell provided in an embodiment of the present invention；

Fig. 2 is the module diagram of another shift register cell provided in an embodiment of the present invention；

Fig. 3 is a kind of circuit diagram of shift register cell provided in an embodiment of the present invention；

Fig. 4 is the circuit diagram of another shift register cell provided in an embodiment of the present invention；

Fig. 5 is a kind of cascade schematic diagram of gate driving circuit provided in an embodiment of the present invention；

Fig. 6 is the cascade schematic diagram of another gate driving circuit provided in an embodiment of the present invention；

Fig. 7 a is the cascade schematic diagram of another gate driving circuit provided in an embodiment of the present invention；

Fig. 7 b is the cascade schematic diagram of another gate driving circuit provided in an embodiment of the present invention；

Fig. 8 a is a kind of control sequential signal graph of shift register cell provided in an embodiment of the present invention

Fig. 8 b is a kind of control sequential signal graph of shift register cell provided in an embodiment of the present invention.

Appended drawing reference：

10- output unit；The first output module of 101-；The second output module of 102-；103- cascaded-output module；104- Three output modules；The 4th output module of 105-；20- drop-down unit；The first pull-down module of 201-；The second pull-down module of 202-； 203- cascades pull-down module；204- third pull-down module；The 4th pull-down module of 205-；30- pull-up control unit；On 301- first Draw control module；302- second pulls up control module；The first reseting module of 303-；The first energy-storage module of 304-；40- drop-down control Unit；The first pull-down control module of 401-；401 '-the first drop-down control replacement modules；The second pull-down control module of 402-；50- Detect control unit；501- detects input module；The second energy-storage module of 502-；503- energy storage control module；504- second resets Module；RS- shift register cell；PU- pull-up node；PD- pull-down node；N1- first node；VDD- first voltage end； VGL1- second voltage end；VGL2- tertiary voltage end；INPUT- signal input part；The first signal output end of OUTPUT1-； OUTPUT2- second signal output end；OUTPUT '-cascade signal output end；OUTPUT1 ' the-the first additional signal output end； OUTPUT2 ' the-the second additional signal output end；The first clock signal terminal of CLKA-；CLKB- second clock signal end；CLKC- third Clock signal terminal；The 4th clock signal terminal of CLKD-；The 5th clock signal terminal of CLKE-；The 6th clock signal terminal of CLKF-；CLKG- 7th clock signal terminal；The 8th clock signal terminal of CLKH-；CLKM- first control signal end；CLKN- replaces control signal end； The first reset signal of RESET1- end；The second reset signal of RESET2- end.

Specific embodiment

Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.

Unless otherwise defined, technical term or scientific term used in the embodiment of the present invention are should be belonging to the present invention The ordinary meaning that personage in field with general technical ability is understood." first ", " second " used in the embodiment of the present invention with And similar word is not offered as any sequence, quantity or importance, and be used only to distinguish different component parts." packet Including " element or object that either the similar word such as "comprising" means to occur before the word cover and appear in the word presented hereinafter Element perhaps object and its equivalent and be not excluded for other elements or object.The similar word such as " connection " or " connected " It is not limited to physics or mechanical connection, but may include electrical connection, it is either direct or indirect. "upper", "lower", "left", "right" etc. are only used for indicating relative positional relationship, after the absolute position for being described object changes, then should Relative positional relationship may also correspondingly change.

The embodiment of the present invention provides a kind of shift register cell, as shown in Figure 1, shift register cell RS includes： Output unit 10, drop-down unit 20, pull-up control unit 30, drop-down control unit 40.

Wherein, output unit 10 includes：The first output module 101 being connect with the first signal output end OUTPUT1, with Second output module 102 of binary signal output end OUTPUT2 connection；First signal output end OUTPUT1 and second signal output End OUTPUT2 is for connecting different grid lines (being generally preferably the corresponding two different grid lines of adjacent rows sub-pix).

Drop-down unit 20 includes：The first pull-down module 201 being connect with the first signal output end OUTPUT1, with the second letter Second pull-down module 202 of number output end OUTPUT2 connection.

First output module 101 and the second output module 102 are connect with pull-up node PU in output unit 10, and drop-down is single First pull-down module 201 and the second pull-down module 202 are connect with pull-down node PD in member 20.

Pull-up control unit 30 is connect with pull-up node PU, pull-down node PD, signal input part INPUT, pull-up control Unit 30 be used to control pull-up node PU (be in different current potentials in the different stages including control pull-up node PU, For example, high potential and low potential).

Drop-down control unit 40 is connect with pull-down node PD, pull-up node PU, the first reset signal end RESET1, the drop-down Control unit 40 is used to control pull-down node PD (is in different electricity including control pull-down node PD in the different stages Position, for example, high potential and low potential), it should, of course, be understood that shift register cell is in normal work, pull-up node PU In pull-down node PD, one is in high potential, then another is in low potential.

Pull-up node PU is successively defeated for controlling the first signal output end OUTPUT1 and second signal output end OUTPUT2 First working signal and the second working signal out；That is, pull-up node PU passes through the first output module 101 and the second output respectively Module 102 controls the first signal output end OUTPUT1 and exports the first working signal, second signal output end OUTPUT2 output the Two working signals.

Pull-down node PD is defeated for controlling the first signal output end OUTPUT1 and second signal output end OUTPUT2 stopping First working signal and the second working signal out；Namely pull-down node PD passes through the first pull-down module 201 and the second drop-down respectively Module 202 controls the first signal output end OUTPUT1 and stops the first working signal of output, the second signal output end OUTPUT2 stops the second working signal of output.

Wherein, in pull-up control unit 30 by control pull-up node PU, and then it is defeated to control the first signal output end The first working signal and the second working signal that OUTPUT1 and second signal output end OUTPUT2 are sequentially output be respectively：First Scanning signal and the second scanning signal.

That is, two signal output ends of two grid lines of connection are provided in shift register cell in the present invention, and And under control of the pull-up control unit to pull-up node, two signal output ends is enabled to be sequentially output the first scanning signal With the second scanning signal, to open two grid lines being correspondingly connected with, line by line normally to be shown；Certainly, in the present invention Control by drop-down control unit to pull-down node can stop two signal output end output the first scanning signals and second Scanning signal, to be resetted, noise reduction etc..

Herein it should be noted that the emphasis in the present invention is provided with the two of two grid lines of connection in shift register cell A signal output end, and for the specific set-up mode of pull-up control unit in shift register cell and drop-down control unit (layout of internal transistor, capacitor etc.), the present invention is not especially limited, and can select to be arranged according to the actual needs, as long as Above-mentioned signal output end is realized in control by the pull-up control unit and drop-down control unit to pull-up node and pull-down node Normal output.

In addition, two signal output ends are arranged as a preferred option in a shift register cell in the present invention, but It is that three or four signal output ends also can be set in practice, should all covers in the present invention.

In addition, should also be understood that first herein, for above-mentioned first working signal and the second working signal, and It is not limited to only the first scanning signal and the second scanning signal, in practice according to the specific setting shape of shift register cell Formula, first working signal and the second working signal can also include other signals, for example, the first detection signal (or claim For the first detecting scanning signal) and the second detection signal (or referred to as second detecting scanning signal), it is correspondingly connected with unlatching Two grid lines, with detecting to (in display panel) drive transistor threshold voltage；After specific reconnaissance phase can refer to The related content that continuous embodiment provides.

Second, above-mentioned pull-up control unit 30 includes two states to the control of pull-up node PU, and one kind is in working condition, Such as high potential (or low potential)；Another kind is off working state, such as low potential (or high potential)；Above-mentioned drop-down control Control of the unit 40 to pull-down node PD includes equally two states, and one kind is in working condition, such as high potential；Another kind is Off working state, such as low potential.It is understood that pull-up node PU is controlled by pull-up control unit 30, into And control output module output scanning signal；Drop-down control unit 40 controls pull-down node PD, and then controls output mould Block stops output scanning signal.

On this basis, those skilled in the art it is to be understood that for for OLED display panel GOA circuit and Speech, needs to be arranged special circuit for detecting in the prior art so as to the driving transistor in pixel-driving circuit in display panel Threshold voltage detected；It also needs that various control modules, pull-up node, pull-down node etc. is arranged in circuit for detecting, from And cause entire GOA circuit structure complicated.

In order to solve the above-mentioned technical problem, in the present invention, in order to further simplify GOA circuit (namely shift register Unit), it is preferred that as shown in Fig. 2, further including on the basis of shift register cell RS above-mentioned：Detect control unit 50。

Wherein, detecting control unit 50 is connect with pull-up node PU, signal input part INPUT, for pull-up node PU It is controlled；With aforementioned, which includes two states to the control of pull-up node PU, and one kind is in working condition, Such as high potential (or low potential)；Another kind is off working state, such as low potential (or high potential).

Specifically, the detecting control unit 50 is by controlling pull-up node PU, and then the first signal output end of control The first working signal and the second working signal output difference that OUTPUT1 and second signal output end OUTPUT2 are sequentially output：For First detection signal and the second detection signal.

So, for shift register cell, by the member control circuit in original circuit for detecting (under such as Draw control unit) carried out with display portion circuit (namely pull-up control unit 30 and lower 40 part of control unit) it is shared, and The two can share the circuit (such as 20 part of output unit 10 and drop-down unit) of output circuit part, thus further letter Shift register cell circuit is changed, namely has simplified GOA circuit, more conducively the narrow frame design of display device.

On this basis, gate driving circuit is usually and is made of cascade multiple shift register cells, specific In " cascade ", by the way that signal of the signal output end of the same level shift register cell as upper level shift register cell is arranged The signal input part of reset terminal, next stage shift register cell, but since signal output end itself needs to connect with grid line, Scanning signal (namely when signal output end output scanning signal, there is certain load) is exported, so as to cause the scanning of output The waveform of signal is not the square wave of standard, namely (upper level, next stage) cascade received reset of shift register cell Signal and input signal are not the square waves of standard, so as to cause cannot effectively answer the shift register cell of upper level Position, and cannot effectively open next stage shift register cell.

In order to solve the above-mentioned technical problem, as shown in Figure 2, it is preferred that in the shift register cell RS in the present invention, on Stating output unit 10 further includes：Cascaded-output module 103；Above-mentioned drop-down unit 20 further includes：Cascade pull-down module 203.

Wherein, cascaded-output module 103 connect the (cascade signal with pull-up node PU, cascade signal output end OUTPUT ' Output end is for cascading multiple shift register cells), it is defeated in the first signal under the control of pull-up node PU While outlet OUTPUT1 and second signal output end OUTPUT2 are sequentially output the first working signal and the second working signal, Output cascade signal (namely the unlatching of the reset signal, next stage shift register cell of upper level shift register cell is believed Number/input signal).

Cascade pull-down module 203 is connect with pull-down node PD, cascade signal output end OUTPUT ', in pull-down node Under the control of PD, stop the first working signal of output in the first signal output end OUTPUT1 and second signal output end OUTPUT2 While with the second working signal, control cascade signal output end OUTPUT ' stops output cascade signal.

So, it is cascaded by the way that cascade signal output end OUTPUT ' is separately provided, can be avoided and use and connection The signal output end (OUTPUT1 or OUTPUT2) of grid line is cascaded, thus ensure that the validity of cascade signal, that is, Next stage shift register cell is effectively resetted and effectively opened to upper level shift register cell.

In summary, it is to be understood that in the present invention, to the tool of each unit, module in above-mentioned shift register cell Body setting is not especially limited；Illustrated below, with reference to Fig. 3, one is provided to each unit, module in above-mentioned shift register cell The preferred specific set-up mode of kind.

Specifically, as shown in figure 3, pull-up control unit 30 may include：First pull-up control module 301, second pulls up Control module 302, the first reseting module 303, the first energy-storage module 304.

Wherein, the first pull-up control module 301 and signal input part INPUT, first voltage end VDD, pull-up node PU connect Connect, under the control of signal input part INPUT by the voltage output of first voltage end VDD to pull-up node PU.

Signal, with reference to Fig. 3, which may include the first transistor M1；The first transistor The grid and signal input part INPUT of M1, the first pole and first voltage end VDD, the second pole is connect with pull-up node PU.

Second pull-up control module 302 is connect with pull-down node PD, pull-up node PU, second voltage end VGL1, is used for Under the control of pull-down node PD, by the voltage output of second voltage end VGL1 to pull-up node PU.

Signal, with reference to Fig. 3, which may include second transistor M2；The second transistor The grid and pull-down node PD of M2, the first pole are connect with second voltage end VGL1, and the second pole is connect with pull-up node PU.

First reseting module 303 is connect with second voltage end VGL1, pull-up node PU, the first reset signal end RESET1, For under the control of the first reset signal end RESET1, by the voltage output of second voltage end VGL1 to pull-up node PU.

Signal, with reference to Fig. 3, which includes third transistor M3；The grid of third transistor M3 with First reset signal end RESET1 connection, the first pole are connect with second voltage end VGL1, and the second pole is connect with pull-up node PU.

First energy-storage module 304 is connect with pull-up node PU, is stored for the voltage to pull-up node PU or right Pull-up node PU discharges.

Signal, with reference to Fig. 3, which includes first capacitor C1；One end of first capacitor C1 and pull-up save Point PU connection, the other end connect with cascade signal output end OUTPUT ' and (can certainly connect with ground terminal).

Drop-down control unit 40 may include：First pull-down control module 401, the second pull-down control module 402.

Wherein, the first pull-down control module 401 is connect with pull-down node PD and first control signal end CLKM, for the Under the control of one control signal end CLKM, the first control signal signal of first control signal end CLKM is exported to pull-down node PD。

Signal, with reference to Fig. 3, which may include the 4th transistor M4；4th transistor The grid of M4 is connect with the first pole with first control signal end CLKM, and the second pole is connect with pull-down node PD.

Second pull-down control module 402 is connect with pull-up node PU, pull-down node PD, second voltage end VGL1, is used for Under the control of pull-up node PU, by the voltage output of second voltage end VGL1 to pull-down node PD.

Signal, with reference to Fig. 3, which includes the 5th transistor M5；5th transistor M5's Grid is connect with pull-up node PU, and the first pole is connect with second voltage end VGL1, and the second pole is connect with pull-down node PD.

With reference to Fig. 3, detecting control unit 50 may include：Detect input module 501, the second energy-storage module 502, energy storage control Molding block 503 and the second reseting module 504.

Wherein, detecting input module 501 and signal input part INPUT, second clock signal end CLKB, first node N1 connect It connects, the signal under the control of second clock signal end CLKB, inputting a signal into end INPUT is exported to first node N1.

Signal, with reference to Fig. 3, which includes the 6th transistor M6；The grid of 6th transistor M6 It is connect with second clock signal end CLKB, the first pole is connect with signal input part INPUT, and the second pole is connect with first node N1.

Second energy-storage module 502 is connect with first node N1, for storing or right the voltage of first node N1 First node N1 discharges.

Signal, with reference to Fig. 3, which may include the second capacitor C2, the first end of the second capacitor C2 It is connect with first node N1, second end connect (it is of course also possible to connecting with ground terminal) with second voltage end VGL1.

Energy storage control module 503 and the first clock signal terminal CLKA, third clock signal terminal CLKC, first node N1, on Node PU connection is drawn, under the control of first node N1 and the first clock signal terminal CLKA, by third clock signal terminal The third clock signal of CLKC is exported to pull-up node PU.

Signal, with reference to Fig. 3, which may include：7th transistor M7, the 8th transistor M8.

Wherein, the grid of the 7th transistor M7 is connect with first node N1, and the first pole and third clock signal terminal CLKC connect It connects, the second pole is connect with the first pole of the 8th transistor M8；The grid of 8th transistor M8 and the first clock signal terminal CLKA connect It connects, the second pole is connect with pull-up node PU.

Second reseting module 504 is connect with pull-up node PU, second voltage end VGL1, the second reset signal end RESET2, For the control in the second reset signal end RESET2 by the voltage output of second voltage end VGL1 to pull-up node PU.

Signal, with reference to Fig. 3, which may include the 9th transistor M9；9th transistor M9's Grid is connect with the second reset signal end RESET2, and the first pole is connect with second voltage end VGL1, the second pole and pull-up node PU Connection.

With reference to Fig. 3, in output unit 10：

First output module 101 and pull-up node PU, the 5th clock signal terminal CLKE, the first signal output end OUTPUT1 Connection, under the control of pull-up node PU, the 5th clock signal of the 5th clock signal terminal CLKE to be exported to the first letter Number output end OUTPUT1.

Signal, with reference to Fig. 3, which may include the tenth transistor M10；Tenth transistor M10's Grid is connect with pull-up node PU, and the first pole is connect with the 5th clock signal terminal CLKE, the second pole and the first signal output end OUTPUT1 connection.

Second output module 102 and pull-up node PU, the 6th clock signal terminal CLKF, second signal output end OUTPUT2 Connection, under the control of pull-up node PU, the 6th clock signal of the 6th clock signal terminal CLKF to be exported to the second letter Number output end OUTPUT2.

Signal, with reference to Fig. 3, which may include the 11st transistor M11；11st transistor The grid of M11 is connect with pull-up node PU, and the first pole is connect with the 6th clock signal terminal CLKF, and the second pole and second signal export Hold OUTPUT2 connection.

Cascaded-output module 103 and pull-up node PU, the 4th clock signal terminal CLKD, cascade signal output end OUTPUT ' Connection, for the 4th clock signal of the 4th clock signal terminal CLKD being exported to cascade and is believed under the control of pull-up node PU Number output end OUTPUT '.

Signal, with reference to Fig. 3, which may include the 14th transistor M14；14th crystal The grid of pipe M14 is connect with pull-up node PU, and the first pole is connect with the 4th clock signal terminal CLKD, and the second pole and cascade signal are defeated Outlet OUTPUT ' connection.

In drop-down unit 20：

First pull-down module 201 is connect with pull-down node PD, tertiary voltage end VGL2, the first signal output end OUTPUT1, For under the control of pull-down node PD, by the voltage output of tertiary voltage end VGL2 to the first signal output end OUTPUT1.

Signal, with reference to Fig. 3, which may include the tenth two-transistor of the tenth two-transistor M12 The grid of M12 is connect with pull-down node PD, and the first pole is connect with tertiary voltage end VGL2, the second pole and the first signal output end OUTPUT1 connection.

Second pull-down module 202 is connect with pull-down node PD, tertiary voltage end VGL2, second signal output end OUTPUT2, For under the control of pull-down node PD, by the voltage output of tertiary voltage end VGL2 to second signal output end OUTPUT2.

Signal, with reference to Fig. 3, which may include the 13rd transistor M13, the 13rd transistor The grid of M13 is connect with pull-down node PD, and the first pole is connect with tertiary voltage end VGL2, the second pole and second signal output end OUTPUT2 connection.

Cascade pull-down module 203 is connect with pull-down node, second voltage end VGL1, cascade signal output end OUTPUT ', is used Under the control in pull-down node PD, by the voltage output of second voltage end VGL1 to cascade signal output end OUTPUT '.

Signal, with reference to Fig. 3, which may include the 15th transistor M15；15th crystal The grid of pipe M15 is connect with pull-down node PD, and the first pole is connect with second voltage end VGL1, the second pole and cascade signal output end OUTPUT ' connection.

It should be noted that above-mentioned first capacitor C1 and the second capacitor C2 can be parasitic capacitance, it is also possible to external electricity Hold, the present invention is not especially limited this.

On this basis, it is contemplated that two different grid lines, and two are set for colleague's sub-pix in the display panel of part The unlatching timing of grid line is different, and (for example, a grid line opens the input for being used for pixel data, another grid line is opened for mending Repay the input of data), in the case, for the shift register in gate driving circuit, need to be arranged two signals Output end, to export two different gated sweep signals for two grid lines with a line sub-pix.

Based on this, as shown in figure 4, the output unit 10 of shift register cell RS can also include：Third exports mould Block 104 and the 4th output module 105；Drop-down unit 20 further includes：Third pull-down module 204 and the 4th pull-down module 205.

Specifically, third output module 104 may include the 16th transistor M16 with reference to Fig. 4；16th transistor The grid of M16 is connect with pull-up node PU, and the first pole is connect with the 7th clock signal terminal CLKG, the second pole and the first additional signal Output end OUTPUT1 ' connection；Wherein, the first additional signal output end OUTPUT1 ' and the first signal output end OUTPUT1 are used for Connection is corresponding with the different grid lines in a line sub-pix.

4th output module 105 includes the 17th transistor M17；The grid and pull-up node of 17th transistor M17 PU connection, the first pole are connect with the 8th end clock signal clk H, and the second pole is connect with the second additional signal output end OUTPUT2 '； The second additional signal output end OUTPUT2 ' and second signal output end OUTPUT2 is corresponding in a line sub-pix for connecting Different grid lines.

Third pull-down module 204 includes the 18th transistor M18；The grid and pull-down node of 18th transistor M18 PD connection, the first pole are connect with tertiary voltage end VGL2, and the second pole is connect with the first additional signal output end OUTPUT1 '.

4th pull-down module 205 includes the 19th transistor M19；The grid and pull-down node of 19th transistor M19 PD connection, the first pole are connect with tertiary voltage end VGL2, and the second pole is connect with the second additional signal output end OUTPUT2 '.

So, it can be controlled by the timing of the signal inputted to each signal end, so that the shift register In unit, the first signal output end OUTPUT1 and the first additional signal output end OUTPUT1 ' are sub- to same a line connected to it Different grid lines in pixel input corresponding signal, second signal output end OUTPUT2 and the second additional signal output end respectively Different grid lines of the OUTPUT2 ' into same a line sub-pix connected to it input corresponding signal respectively.

On this basis, the first control signal in order to avoid being connect in pull-down control module 401 with the 4th transistor M4 The first control signal inputted in the CLKM of end is in same current potential (can specifically refer to Fig. 8) and leads to the 4th transistor for a long time The problems such as M4 is damaged, in practice preferably, as shown in figure 4, further including in the drop-down control unit 40 of the shift register cell： First drop-down control replacement module 401 '.

Specifically, the first drop-down control replacement module 401 ' includes replacement transistor M4 ', replacement transistor M4's ' Grid and the first pole are connect with replacement control signal end CLKN, and the second pole is connect with pull-down node PD.

Wherein, when the replacement control signal for replacing control signal end CLKN is high potential, first control signal end CLKM's First control signal is low potential；When the replacement control signal for replacing control signal end CLKN is low potential, first control signal The first control signal end for holding CLKM is high potential.That is, the first pull-down control module 401 and the first drop-down control replacement module The phenomenon that 401 ' the two alternately work, damage so as to avoid transistor therein；Also, replace control signal end The replacement control signal of CLKN and the first control signal of first control signal end CLKM can be low-frequency clock signal, can also be with It is replaced with direct current signal.

Further, as shown in Figure 3 and Figure 4, for the present invention, above-mentioned second voltage end VGL1 and tertiary voltage end VGL2 can be same voltage end, or different voltage ends；The generation of leaky in order to prevent in practice, preferably , second voltage end VGL1 and tertiary voltage end VGL2 are different voltage ends.

Signal, by taking each transistor in above-mentioned shift register cell RS is N-type transistor as an example, then above-mentioned second Voltage end VGL1 and tertiary voltage end VGL2 is low level voltage end (direct current signal), and the voltage of second voltage end VGL1 is small In the voltage of tertiary voltage end VGL2.

The embodiment of the present invention also provides a kind of gate driving circuit, as shown in Figure 5 or Figure 6, including at least two-stage cascade Shift register cell RS as the aforementioned.

Wherein, the signal input part INPUT of first order shift register cell RS is connected with initial signal end STU；When So, the initial signal of initial signal end STU input can be the pulse signal being separately provided, and be also possible to empty using previous stage The output signal of quasi- (Dummy) unit.

With reference to Fig. 5, other than first order shift register cell, the first signal of upper level shift register cell is defeated Outlet OUTPUT1 is connected with the signal input part INPUT of next stage shift register cell；In addition to afterbody shift LD Other than device unit, the first signal output end OUTPUT1 and upper level shift register cell of next stage shift register cell The first reset signal end RESET1 be connected.

Alternatively, in the case where grade shift register cell RS includes cascade signal output end OUTPUT ':

With reference to Fig. 6, other than first order shift register cell, the cascade signal of upper level shift register cell is defeated Outlet OUTPUT ' is connected with the signal input part INPUT of next stage shift register cell；In addition to afterbody shift LD Other than device unit, the cascade signal output end OUTPUT ' and upper level shift register cell of next stage shift register cell The first reset signal end RESET1 be connected.

Certainly, the first reset signal end RESET1 of afterbody shift register cell is connected with termination signal end STD It connects；Certainly, the termination signal of termination signal end STD input, can be the pulse signal being separately provided, and also can use virtual (Dummy) output signal of unit.

It should here be understood that arriving, for detecting the signal input part of control module connection in first order shift register cell The signal input part connected with pull-up control unit can be same initial signal STU, or different initial signal (examples Such as, STU1 and STU2).

In practice, it is generally preferable to, using the cascade side with cascade signal output end OUTPUT ' shown in Fig. 6 The gate driving circuit of formula；Also, in the case, for the shift register cell that such as Fig. 3 is provided, each cascade shifting It include the 4th clock signal terminal CLKD in bit register unit, it is contemplated that actual scan control (guaranteeing scan frequency) is such as schemed Shown in 7a or Fig. 7 b, it is preferred that in the gate driving circuit：

It can will be located at the 4th clock signal terminal CKLD of the shift register cell of odd level and the shifting for being located at even level 4th clock signal terminal CKLD of bit register unit connects different the 4th clock cables (CKLD_A and CKLD_B), so as to Cascade signal is exported to the signal of next stage shift register cell by the 4th clock cable (CKLD_A and CKLD_B) Output end, while guaranteeing that scanning signal is sequentially output line by line.

In addition, it is necessary to explanation, in shift register cells at different levels in gate driving circuit, second clock signal The connection type for holding CLKB and third clock signal terminal CLKC, can be configured, according to the actual needs certainly, in connection side In the case that formula is different, corresponding clock signal may need to be adjusted correspondingly.

Signal, for example, can be as shown in Figure 7a, the second clock signal of the shift register cell of odd level will be located at End CLKB is connect with second clock signal wire CLKB (L2), third clock signal terminal CLKC and third clock cable CLKC (L3) Connection；The second clock signal end CLKB and third clock cable CLKC (L3) of the shift register cell of even level will be located at Connection, third clock signal terminal CLKC are connect with second clock signal wire CLKB (L2)；Certainly, under the connection type when Sequence control signal can refer to Fig. 8 a and the corresponding part of subsequent embodiment.

In another example can be as shown in Figure 7b, by the second clock signal end CLKB of the shift register cell of every level-one with Second clock signal wire CLKB (L2) connection, when the third clock signal terminal CLKC of the shift register cell of every level-one is with third Clock signal wire CLKC (L3) connection；Fig. 8 b and subsequent reality can be referred to certainly for the timing control signal under the connection type Apply the corresponding part of example.

It should, of course, be understood that as shown in figs. 7 a and 7b, being connect by certain signal end and with the signal end in the present invention Signal wire use identical or corresponding appended drawing reference, merely to simple and clear, the present invention will be described, without It should be counted as unclear.

In addition, for other signal end connection types, it can be with reference to the corresponding connection of signal end relevant in Fig. 7 a, Fig. 7 b Mode, no longer attached drawing and text repeats one by one herein.

The embodiment of the present invention also provides a kind of display device, including gate driving circuit above-mentioned；In the display device The grid line G being arranged successively is divided into the multiple grid line groups being arranged successively according to two one group, and in each grid line group F include according to First grid line of secondary arrangement and the second grid line (with reference to the G1 and G2 and G3 and G4 etc. in Fig. 7 a).

In the gate driving circuit successively cascade shift register cell respectively with the institute that is arranged successively in display device State the connection of grid line group.

Specifically, successively cascade shift register cell RS passes through the first signal output end OUTPUT1 and second signal Output end OUTPUT2, in the grid line group F that is arranged successively in display device the first grid line and the second grid line correspond and connect It connects；For example, first order shift register cell the first signal output end OUTPUT1 and second signal output end OUTPUT2 and The first grid line and the second grid line in one grid line group F are sequentially connected respectively, and shift register cell the first signal in the second level is defeated Outlet OUTPUT1 and second signal output end OUTPUT2 and the first grid line in second grid line group F and the second grid line respectively according to Secondary connection etc..

It in practice, can be by the way of bilateral driving, namely in display panel grid line for the driving of display panel Gate driving circuit above-mentioned is respectively set in two sides；For example, the gate driving circuit of side carries out the driving of odd-numbered line, it is another Gate driving circuit carries out the driving of even number line, so, so that it may guarantee the enough detecting time.

The embodiment of the present invention also mention it is a kind of for driving the driving method of aforementioned shift register unit, in conjunction with the shifting of Fig. 3 Bit register unit and Fig. 8 a (connection type of corresponding diagram 7a), the corresponding timing control of Fig. 8 b (connection type of corresponding diagram 7b) Shown in figure, in actual display, a picture frame includes display stage Display and is located at after display stage Display Reconnaissance phase Blank.

In display stage Display, which includes：

First stage S1：

The first input signal is inputted to signal input part INPUT (to input the signal of first order shift register cell End INPUT is connect with initial signal end STU)；First pull-up control module 301 is under the control of the first input signal by the first electricity The voltage output of pressure side VDD is stored to pull-up node PU, and by the first energy-storage module 304；In the control of pull-up node PU Under system, the nonoperating voltage of the 5th clock signal terminal CLKE is exported to the first signal output end OUTPUT1, the 6th clock is believed Number end CLKF nonoperating voltage export to second signal output end OUTPUT2, by the inoperative of the 4th clock signal terminal CLKD Voltage output is to cascade signal output end OUTPUT ', to be reset.

Specifically, in this stage, inputting the first input signal (for first to signal input part INPUT in conjunction with Fig. 3 The signal input part INPUT of grade shift register cell is connect with initial signal end STU), the first transistor M1 conducting, by first The voltage output of voltage end VDD is stored into first capacitor C1 to pull-up node PU；And in the control of pull-up node PU Under, the tenth transistor M10 conducting is defeated to the first signal by nonoperating voltage (low potential) output of the 5th clock signal terminal CLKE Outlet OUTPUT1；11st transistor M11 conducting, the nonoperating voltage (low potential) of the 6th clock signal terminal CLKF is exported To second signal output end OUTPUT2；14th transistor M11 conducting, by the nonoperating voltage of the 4th clock signal terminal CLKD (low potential) is exported to cascade signal output end OUTPUT ', to be reset.

Certainly, it should be noted that before entering the stage, input first control signal in first control signal end CLKM Control under so that the 4th transistor M4 is in the conductive state, the high potential of first control signal is exported to pull-down node PD, Guarantee that pull-down node PD is in high potential.

Second stage S2：

First energy storage mould 304 discharges to pull-up node PU, and under the control of pull-up node PU, and the 5th clock is believed Number end CLKE operating voltage export as the first scanning signal scan1 to the first signal output end OUTPUT1, by the 6th clock The operating voltage of signal end CLKF is exported as the second scanning signal scan2 to second signal output end OUTPUT2, when by the 4th The operating voltage of clock signal end CLKD is exported as cascade signal to cascade signal output end OUTPUT '.

Specifically, in conjunction with Fig. 3, in the stage, first capacitor C1 discharges to pull-up node PU, so that pull-up node PU Current potential further promoted, at this point, under the control of pull-up node PU, the tenth transistor M10 conducting, by the 5th clock signal The operating voltage (high level) of end CLKE is exported as the first scanning signal scan1 to the first signal output end OUTPUT1；Tenth One transistor M11 conducting, the operating voltage (high level) of the 6th clock signal terminal CLKF is defeated as the second scanning signal scan2 Out to second signal output end OUTPUT2；14th transistor M14 conducting, by the operating voltage of the 4th clock signal terminal CLKD (high level) is exported as cascade signal to cascade signal output end OUTPUT '.

It should be noted that at this stage, Fig. 8 a or Fig. 8 b can be referred to, need to guarantee in the 4th clock signal terminal CLKD It is correspondingly outputting to the period t0 of the operating voltage of cascade signal output end OUTPUT ', it should cover the 5th clock signal terminal CLKE It is correspondingly outputting to the corresponding output of period t1 and the 6th clock signal terminal CLKF of the operating voltage of the first signal output end OUTPUT1 To the period t2 of the operating voltage of second signal output end OUTPUT2；And it should also ensure that second signal output end OUTPUT2 Operating voltage be correspondingly outputting to the operating voltage of the first signal output end OUTPUT1 extremely relative to the 5th clock signal terminal CLKE Postpone a pixel data less and pulsewidth is written.

Phase III S3：

The first reset signal is inputted to the first reset signal end RESET1, and under the control of the first reset signal RESET1 The voltage output of second voltage end VGL2 to pull-up node PU is resetted.

First control signal is inputted to first control signal end CLKM, the first pull-down control module 401 is in the first control letter Number control under, first control signal is exported to pull-down node PD, and under the control of pull-down node PD, by tertiary voltage end The voltage output of VGL2 is to the first signal output end OUTPUT1 and second signal output end OUTPUT2, by second voltage end VGL1 Voltage output to cascade signal output end OUTPUT ', to be resetted.

Specifically, at this stage, inputting the first reset signal to the first reset signal end RESET1, third is brilliant in conjunction with Fig. 3 Body pipe M3 conducting, the voltage output of second voltage end VGL1 to pull-up node PU is resetted.

And at this stage, first control signal end CLKM inputs the first control signal of high potential, and this first is controlled Signal processed is exported to pull-down node PD；Under the control of pull-down node PD, the tenth two-transistor M12 conducting, by tertiary voltage end The voltage (low potential) of VGL2 is exported to the first signal output end OUTPUT1；13rd transistor M13 conducting, by tertiary voltage Hold the voltage output of VGL2 to second signal output end OUTPUT2；15th transistor M15 conducting, by second voltage end VGL1 Voltage output to cascade signal output end OUTPUT ', to be resetted.

In reconnaissance phase blank, which further includes：

Fourth stage S4：

The first clock signal is inputted to the first clock signal terminal CLKA, inputs third clock to third clock signal terminal CLKC Signal, and the second energy storage mould 502 discharges to first node N1, first node N1's and the first clock signal terminal CLKA Under control, energy storage control module 503 exports third clock signal to pull-up node PU, will under the control of pull-up node PU The operating voltage (high level) of 5th clock signal terminal CLKE is exported to the first signal as the first detection signal sense1 and is exported Hold OUTPUT1, by the operating voltage (high level) of the 6th clock signal terminal CLKF as the second detection signal sense2 export to Second signal output end OUTPUT2；The operating voltage (high level) of 4th clock signal terminal CLKD is exported as cascade signal To cascade signal output end OUTPUT '.

Specifically, at this stage, the second capacitor C2 discharges to first node N1, to the first clock signal in conjunction with Fig. 3 CLKA is held to input the first clock signal, the 7th transistor M7 and the 8th transistor M8 conducting, third clock signal terminal CLKC is defeated The third clock signal entered is exported to pull-up node PU；Under the control of pull-up node PU, the tenth transistor M10 conducting, by the The operating voltage of five clock signal terminal CLKE is exported as the first detection signal to the first signal output end OUTPUT1；11st Transistor M11 conducting, exports defeated to second signal using the operating voltage of the 6th clock signal terminal CLKF as the second detection signal Outlet OUTPUT2.

Herein it should be noted that in the stage, for above-mentioned " the second capacitor C2 discharges to first node N1 " Speech, during display, with reference to Fig. 8 a or Fig. 8 b, for first frame picture frame 1F, in the first stage when S1, to the Two clock signal terminal CLKB export second clock signal, while inputting initial signal STU to signal output end INPUT, so that the Six transistor M6 conducting, and initial signal STU is stored into the second capacitor C2, thus this picture frame fourth stage S4 into Row electric discharge.

For the picture frame (such as second picture frame 2F, third picture frame 3F ...) in addition to first frame picture frame 1F, When second capacitor C2 can be in running order in the reconnaissance phase of previous image frame (namely the first detection signal sense1 of output When with the second detection signal sense2), second clock signal is inputted to second clock signal end CLKB, while to signal output end INPUT input signal (cascade signal), and the signal output end INPUT signal inputted is stored into the second capacitor C2, it maintains Fourth stage S4 to next image frame discharges.

Herein it should be noted that connection type compared to Fig. 7 b, second clock signal end CLKB exists in corresponding diagram 8b When in running order in the reconnaissance phase of each picture frame (namely the first detection signal sense1 of output and the second detection signal When sense2), second clock signal is exported to second clock signal end CLKB, that is, can guarantee reconnaissance phase in next image frame For normal work, under the connection type of Fig. 7 a, due to second clock signal end in the shift register cell of adjacent level CLKB and third clock signal terminal CLKC is alternately and under second signal line CLKB (L2) and third signal wire CLKC (L3), signal , with reference to Fig. 8 a, start output first in the fourth stage S4 in the reconnaissance phase blank of previous image frame (the first picture frame) It is defeated to third clock signal terminal CLKC in previous stage (first order) shift register cell when detection signal and the second detection signal The third clock signal entered, can be simultaneously as second clock signal end CLKB in next stage (second level) shift register cell Second clock signal, to ensure that the normal work of reconnaissance phase in next (second) picture frame.

5th stage S5：

The second reset signal is inputted to the second reset signal end RESET2, under the control of the second reset signal, second is multiple Position module 504 resets the voltage output of second voltage end VGL1 to pull-up node PU to pull-up node PU.

Specifically, at this stage, the second reset signal is inputted to the second reset signal end RESET2 in conjunction with Fig. 3 and Fig. 8, 9th transistor M9 conducting, the voltage output of second voltage end VGL1 to pull-up node PU resets pull-up node PU.

The first control signal of first control signal end CLKM input high level, the 4th transistor M4 conducting, by this first Control signal is exported to pull-down node PD, under the control of pull-down node PD, by the voltage (low potential) of tertiary voltage end VGL2 It exports to the first signal output end OUTPUT1；13rd transistor M13 conducting, extremely by the voltage output of tertiary voltage end VGL2 Second signal output end OUTPUT2；15th transistor M15 conducting, by the voltage output of second voltage end VGL1 to cascading letter Number output end OUTPUT ', to be resetted.

Herein it should be noted that in Fig. 8 a, Fig. 8 b only be signal give gate driving shown in Fig. 7 a, Fig. 7 b Circuit is during driving, the relevant control timing of preceding 4 picture frame (1F, 2F, 3F, 4F), wherein it can be understood that CLKB, CLKC, CLKD, CLKE, CLKF are pulsewidth relationship adjustable clock signal, and CLKM, CLKN are that low-frequency clock signal (can of course be used Direct current signal replacement), CLKD signal includes CLKD_A, CLKD_B of alternately connection control, and wherein CLKD_A is as the 1st, 3,5, The CLKD of 7 ... odd level shift register cell, the even level shift register list that CLKD_B is as the 2nd, 4,5,8 ... The CLKD of member；Certainly, other relevant control signals, for example, VGL1 and VGL2 is direct current low-potential signal, the numerical value of the two can It can not also be waited with equal, the current potential of preferred VGL1 is less than the electricity of VGL2；VDD is direct current high potential signal etc., herein not It specifically repeats again.

In addition, also being had been shown in particular in Fig. 8, the tool of the relevant clock signal terminal of first order shift register cell RS1 Body input signal (CLKD_A, CLKE_1H, CLKF_2H), output signal (OUTPUT1_1H, OUTPUT2_2H)；Pull-up node PU (1) current potential, the relevant timing control signal such as current potential of first node N1 (1) and second level shift register cell RS2 Relevant clock signal terminal specific input signal (CLKD_B, CLKE_3H, CLKF_4H), the output signal of output end (OUTPUT1_3H, OUTPUT2_3H), the current potential of pull-up node PU (2), the relevant timing control such as current potential of first node N1 (2) Signal processed and other relevant signals, wherein 1H, 2H, 3H, 4H respectively with the first row grid line, the second row grid line, the third line Grid line, the corresponding coherent signal of fourth line grid line；It certainly, can for the input of other grade of shift register cell, output signal To refer to Fig. 7 and content above-mentioned, no longer repeat one by one herein.

Herein it should also be noted that, the switching process of transistor is using all transistors as N-type crystalline substance in above-described embodiment It is illustrated for body pipe, when all transistors are p-type, needs to overturn control signal each in Fig. 8, and will Even be respectively connected to low potential with the first voltage end VDD module being connected or transistor in Fig. 3, with second voltage end VGL1 and The module or transistor that tertiary voltage end VGL2 is connected connect high potential, and preferred, and the voltage at tertiary voltage end is high Voltage in second voltage end.

The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.

Claims

1. a kind of shift register cell, which is characterized in that the shift register cell includes：Pull-up control unit, drop-down Control unit, output unit, drop-down unit；

The output unit includes：The first output module connecting with the first signal output end, connect with second signal output end The second output module；First signal output end and the second signal output end are for connecting different grid lines；

The drop-down unit includes：The first pull-down module being connect with first signal output end, it is defeated with the second signal Second pull-down module of outlet connection；

First output module and second output module in the output unit are connect with pull-up node, under described First pull-down module and second pull-down module in unit is drawn to connect with pull-down node；

The pull-up control unit is connect with the pull-up node, the pull-down node, signal input part, the pull-up control unit For controlling the pull-up node；The drop-down control unit is answered with the pull-down node, the pull-up node, first Position signal end connection, the drop-down control unit is for controlling the pull-down node；

The pull-up node is used to control first signal output end and the second signal output end is sequentially output the first work Make signal and the second working signal；The pull-down node is for controlling first signal output end and second signal output End stops exporting first working signal and second working signal；

The pull-up control unit controls first signal output end and described second by controlling the pull-up node First working signal and second working signal that signal output end is sequentially output be respectively：First scanning signal and Two scanning signals.

2. shift register cell according to claim 1, which is characterized in that

The shift register cell further includes：Detect control unit；

The detecting control unit is connect with the pull-up node, the signal input part, for carrying out to the pull-up node Control；

The detecting control unit controls first signal output end and described second by controlling the pull-up node First working signal and second working signal that signal output end is sequentially output be respectively：First detection signal and Two detection signals.

3. shift register cell according to claim 1 or 2, which is characterized in that

The output unit further includes：Cascaded-output module；The drop-down unit further includes：Cascade pull-down module；

The cascaded-output module is connect with the pull-up node, cascade signal output end, for the control in the pull-up node Under system, first working signal and described are sequentially output in first signal output end and the second signal output end While two working signals, output cascade signal；

The cascade pull-down module is connect with the pull-down node, the cascade signal output end, in the pull-down node Control under, stop exporting first working signal and institute in first signal output end and the second signal output end While stating the second working signal, controls the cascade signal output end and stop exporting the cascade signal；

Wherein, the cascade signal output end is for cascading multiple shift register cells.

4. shift register cell according to claim 3, which is characterized in that

The pull-up control unit includes：First pull-up control module, the second pull-up control module, the first reseting module, first Energy-storage module；

Wherein, the first pull-up control module is connect with the signal input part, first voltage end, the pull-up node, is used By the voltage output at the first voltage end to the pull-up node under the control in the signal input part；

The second pull-up control module is connect with the pull-down node, the pull-up node, second voltage end, for described Under the control of pull-down node, by the voltage output at the second voltage end to the pull-up node；

First reseting module is connect with the second voltage end, the pull-up node, first reset signal end, is used for Under the control at first reset signal end, by the voltage output at the second voltage end to the pull-up node；

First energy-storage module is connect with the pull-up node, for the voltage of the pull-up node to be stored, or It discharges the pull-up node；

The drop-down control unit includes：First pull-down control module, the second pull-down control module；

Wherein, first pull-down control module is connect with the pull-down node and first control signal end, for described the Under the control of one control signal end, the first control signal at the first control signal end is exported to the pull-down node；

Second pull-down control module is connect with the pull-up node, the pull-down node, the second voltage end, is used for Under the control of the pull-up node, by the voltage output at the second voltage end to the pull-down node；

In the case where the shift register cell includes detecting control unit, the detecting control unit includes：It detects defeated Enter module, the second energy-storage module, energy storage control module and the second reseting module；

Wherein, the detecting input module is connect with the signal input part, second clock signal end, first node, is used for Under the control of the second clock signal end, the signal of the signal input part is exported to the first node；

Second energy-storage module is connect with the first node, for the voltage of the first node to be stored, or It discharges the first node；

The energy storage control module and the first clock signal terminal, third clock signal terminal, the first node, the pull-up node Connection, under the control of the first node and first clock signal terminal, by the of the third clock signal terminal Three clock signals are exported to the pull-up node；

Second reseting module is connect with the pull-up node, the second voltage end, the second reset signal end, in institute The control at the second reset signal end is stated by the voltage output at the second voltage end to the pull-up node；

In the output unit,

The cascaded-output module is connect with the pull-up node, the 4th clock signal terminal, the cascade signal output end, is used for Under the control of the pull-up node, the 4th clock signal of the 4th clock signal terminal is exported defeated to the cascade signal Outlet；

First output module is connect with the pull-up node, the 5th clock signal terminal, first signal output end, is used for Under the control of the pull-up node, the 5th clock signal of the 5th clock signal terminal is exported defeated to first signal Outlet；

Second output module is connect with the pull-up node, the 6th clock signal terminal, the second signal output end, is used for Under the control of the pull-up node, the 6th clock signal of the 6th clock signal terminal is exported defeated to the second signal Outlet；

In the drop-down unit,

The cascade pull-down module is connect with the pull-down node, the second voltage end, the cascade signal output end, is used for Under the control of the pull-down node, by the voltage output at the second voltage end to the cascade signal output end；

First pull-down module is connect with the pull-down node, the tertiary voltage end, first signal output end, is used for Under the control of the pull-down node, by the voltage output at the tertiary voltage end to first signal output end；

Second pull-down module is connect with the pull-down node, the tertiary voltage end, the second signal output end, is used for Under the control of the pull-down node, by the voltage output at the tertiary voltage end to the second signal output end.

5. shift register cell according to claim 4, which is characterized in that

In the pull-up control unit：

The first pull-up control module includes the first transistor；The grid of the first transistor and the signal input part, First pole and the first voltage end, the second pole is connect with the pull-up node；

The second pull-up control module includes second transistor；The grid of the second transistor and the pull-down node, the One pole is connect with the second voltage end, and the second pole is connect with the pull-up node；

First reseting module includes third transistor；The grid of the third transistor and first reset signal end connect It connects, the first pole is connect with the second voltage end, and the second pole is connect with the pull-up node；

The energy-storage module includes first capacitor；One end of the first capacitor is connect with the pull-up node, the other end and institute State the connection of cascade signal output end；

In the drop-down control unit：

First pull-down control module includes the 4th transistor；The grid of 4th transistor and the first pole and described first Control signal end connection, the second pole is connect with the pull-down node；

Second pull-down control module includes the 5th transistor, and the grid of the 5th transistor and the pull-up node connect It connects, the first pole is connect with the second voltage end, and the second pole is connect with the pull-down node；

In the detecting control unit：

The detecting input module includes the 6th transistor；The grid and the second clock signal end of 6th transistor connect It connects, the first pole is connect with the signal input part, and the second pole is connect with first node；

Second energy-storage module includes the second capacitor, and the first end of second capacitor is connect with the first node, and second End is connect with the second voltage end；

The energy storage control module includes：7th transistor, the 8th transistor；The grid and the first segment of seven transistor Point connection, the first pole are connect with the third clock signal terminal, and the second pole is connect with the first pole of the 8th transistor；It is described The grid of 8th transistor is connect with first clock signal terminal, and the second pole is connect with the pull-up node；

Second reseting module includes the 9th transistor；The grid of 9th transistor and second reset signal end connect It connects, the first pole is connect with the second voltage end, and the second pole is connect with the pull-up node；

In the output unit：

The first output mould includes the tenth transistor；The grid of tenth transistor is connect with the pull-up node, and first Pole is connect with the 5th clock signal terminal, and the second pole is connect with first signal output end；

Second output module includes the 11st transistor；The grid of 11st transistor and the pull-up node connect It connects, the first pole is connect with the 6th clock signal terminal, and the second pole is connect with the second signal output end；

The cascaded-output module includes the 14th transistor；The grid of 14th transistor and the pull-up node connect It connects, the first pole is connect with the 4th clock signal terminal, and the second pole is connect with the cascade signal output end；

In the drop-down unit：

First pull-down module includes the tenth two-transistor；The grid of tenth two-transistor and the pull-down node connect It connects, the first pole is connect with the tertiary voltage end, and the second pole is connect with first signal output end；

Second pull-down module includes the 13rd transistor；The grid of 13rd transistor and the pull-down node connect It connects, the first pole is connect with the tertiary voltage end, and the second pole is connect with the second signal output end；

The cascade pull-down module includes the 15th transistor；The grid of 15th transistor and the pull-down node connect It connects, the first pole is connect with second voltage end, and the second pole is connect with the cascade signal output end.

6. shift register cell according to claim 5, which is characterized in that

The output unit further includes：Third output module and the 4th output module；

The drop-down unit further includes：Third pull-down module and the 4th pull-down module；

The third output module includes the 16th transistor；The grid of 16th transistor and the pull-up node connect It connects, the first pole is connect with the 7th clock signal terminal, and the second pole is connect with the first additional signal output end；And described first adds letter Number output end and first signal output end are corresponding with the different grid lines in a line sub-pix for connecting；

4th output module includes the 17th transistor；The grid of 17th transistor and the pull-up node connect It connects, the first pole is connect with the 8th clock signal terminal, and the second pole is connect with the second additional signal output end；And described second adds letter Number output end and the second signal output end are corresponding with the different grid lines in a line sub-pix for connecting；

The third pull-down module includes the 18th transistor；The grid of 18th transistor and the pull-down node connect It connects, the first pole is connect with the tertiary voltage end, and the second pole is connect with the first additional signal output end；

4th pull-down module includes the 19th transistor；The grid of 19th transistor and the pull-down node connect It connects, the first pole is connect with the tertiary voltage end, and the second pole is connect with the second additional signal output end.

7. shift register cell according to claim 5 or 6, which is characterized in that

The drop-down control unit further includes：First drop-down control replacement module；

The first drop-down control replacement module includes replacement transistor；The grid of the replacement transistor and the first pole and replacement Control signal end connection, the second pole is connect with the pull-down node；

When the replacement control signal of the replacement control signal end is high potential, the first control letter at the first control signal end Number be low potential；When the replacement control signal of the replacement control signal end is low potential, the of the first control signal end One control signal is high potential.

8. shift register cell according to claim 4, which is characterized in that

The second voltage end is different voltage ends from the tertiary voltage end；

The second voltage end and the tertiary voltage end are low level voltage end, and the voltage at the second voltage end is less than The voltage at the tertiary voltage end.

9. a kind of gate driving circuit, which is characterized in that including at least two-stage cascade as claim 1-8 it is described in any item Shift register cell；

The signal input part of first order shift register cell is connected with initial signal end；

Other than the first order shift register cell, the first signal output end of upper level shift register cell is under The signal input part of level-one shift register cell is connected；Other than afterbody shift register cell, next stage is moved First signal output end of bit register unit is connected with the first reset signal end of upper level shift register cell；

Alternatively, in the case where the grade shift register cell includes cascade signal output end, in addition to the first order shifts Other than register cell, the cascade signal output end of upper level shift register cell and the letter of next stage shift register cell Number input terminal is connected；Other than afterbody shift register cell, the cascade signal of next stage shift register cell Output end is connected with the first reset signal end of upper level shift register cell；

First reset signal end of the afterbody shift register cell is connected with termination signal end.

10. gate driving circuit according to claim 9, which is characterized in that in the shift register cell include the In the case where four clock signal terminals,

The 4th clock signal terminal positioned at the shift register cell of odd level and the shift register cell positioned at even level 4th clock signal terminal connects the 4th different clock cables.

11. a kind of display device, which is characterized in that including the gate driving circuit as described in claim 9 or 10；

The grid line being arranged successively in the display device is divided into the multiple grid line groups being arranged successively according to two one group, and It include the first grid line and the second grid line being arranged successively in each grid line group；

In the gate driving circuit successively cascade shift register cell respectively be arranged successively in the display device The grid line group connection.

12. a kind of driving method for driving such as the described in any item shift register cells of claim 4-8, feature exist In a picture frame includes display stage and the reconnaissance phase after the display stage；

Within the display stage, the driving method includes：

First stage inputs the first input signal to signal input part；First pull-up control module is in first input signal Control under stored by the voltage output at first voltage end to pull-up node, and by the first energy-storage module；In the pull-up Under the control of node, the nonoperating voltage of the 5th clock signal terminal is exported to the first signal output end, by the 6th clock signal The nonoperating voltage at end is exported to second signal output end, and the nonoperating voltage of the 4th clock signal terminal is exported to cascade signal Output end, to be reset；

Second stage, the first energy storage mould discharge to the pull-up node, and under the control of the pull-up node, by institute The operating voltage for stating the 5th clock signal terminal is exported as the first scanning signal to first signal output end, by the described 6th The operating voltage of clock signal terminal is exported as the second scanning signal to the second signal output end, and the 4th clock is believed Number end operating voltage export as cascade signal to the cascade signal output end；

Phase III inputs the first reset signal to the first reset signal end, and will under the control of first reset signal The voltage output at second voltage end to the pull-up node is resetted；

First control signal, control of first pull-down control module in the first control signal are inputted to first control signal end Under, the first control signal is exported to pull-down node, and under the control of the pull-down node, by the voltage at tertiary voltage end Output is to first signal output end and the second signal output end, by the voltage output at second voltage end to the cascade Signal output end, to be resetted；

In the reconnaissance phase, the driving method further includes：

Fourth stage inputs the first clock signal to the first clock signal terminal, to third clock signal terminal input third clock letter Number, and the second energy storage mould discharges to first node, under the control of the first node and first clock signal, Energy storage control module exports the third clock signal to the pull-up node；And under the control of the pull-up node, by institute The operating voltage for stating the 5th clock signal terminal is exported as the first detection signal to first signal output end, by the described 6th The operating voltage of clock signal terminal is exported as the second detection signal to the second signal output end；

5th stage inputted the second reset signal to the second reset signal end, described under the control of second reset signal Second reseting module is by the voltage output at second voltage end to the pull-up node；

First control signal, control of first pull-down control module in the first control signal are inputted to first control signal end Under, the first control signal is exported to the pull-down node, and under the control of the pull-down node, by tertiary voltage end Voltage output is to first signal output end and the second signal output end, by the voltage output at second voltage end to described Cascade signal output end, to be resetted.