CN108666367B - Fin type field effect transistor and forming method thereof - Google Patents
Fin type field effect transistor and forming method thereof Download PDFInfo
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- CN108666367B CN108666367B CN201710198362.XA CN201710198362A CN108666367B CN 108666367 B CN108666367 B CN 108666367B CN 201710198362 A CN201710198362 A CN 201710198362A CN 108666367 B CN108666367 B CN 108666367B
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- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 7
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a fin field effect transistor and a forming method thereof, wherein the forming method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a plurality of discrete fin parts; forming a first isolation layer on the semiconductor substrate exposed out of the fin portion, wherein the first isolation layer covers part of the side wall of the fin portion, and the top of the first isolation layer is lower than the top of the fin portion; forming a protective layer on the side wall of the fin part exposed out of the first isolation layer; forming a second isolation layer between the fin parts, wherein the second isolation layer covers the top of the first isolation layer and the side wall of the protection layer; after the second isolation layers are formed, removing part of or all of the fin parts with the thickness between the second isolation layers to form an opening; cleaning the opening; and after cleaning the opening, forming a channel layer which is filled in the opening. The electrical performance of the fin field effect transistor formed by the invention is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a fin type field effect transistor and a forming method thereof.
Background
With the rapid development of semiconductor technology, the feature size of semiconductor devices is continuously shrinking. The reduction in feature size of semiconductor devices places higher demands on the performance of semiconductor devices.
Currently, the size of metal-oxide semiconductor field effect transistors (MOSFETs) is becoming smaller. To accommodate the reduction in process nodes, the channel length of MOSFET fets is also being reduced. The reduction of the channel length has the advantages of increasing the die density of the chip, increasing the switching speed of the MOSFET field effect transistor, and the like.
However, the reduction of the channel length is likely to cause the problem of poor control capability of the gate to the channel, so that the difficulty of pinching off (ping off) the channel by the gate voltage is increased, and further, the sub-threshold leakage phenomenon, i.e. short-channel effects (SCE), occurs.
Therefore, in order to better meet the requirements of scaling down the device size, semiconductor processes are gradually shifting from planar MOSFET transistors to three-dimensional transistors (e.g., finfet transistors) with higher performance. The fin field effect transistor has good channel control capability and can reduce short channel effect.
The prior art has the problem that the electrical property of a fin field effect transistor can not meet the technical development requirement in the field of semiconductors. Therefore, how to improve the electrical performance of the finfet becomes an urgent problem to be solved.
Disclosure of Invention
The invention aims to provide a fin field effect transistor and a forming method thereof, and the electrical performance of the fin field effect transistor is improved.
In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, including: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a plurality of discrete fin parts; forming a first isolation layer on the semiconductor substrate exposed out of the fin portion, wherein the first isolation layer covers part of the side wall of the fin portion, and the top of the first isolation layer is lower than the top of the fin portion; forming a protective layer on the side wall of the fin part exposed out of the first isolation layer; forming a second isolation layer between the fin parts, wherein the second isolation layer covers the top of the first isolation layer and the side wall of the protection layer; after the second isolation layers are formed, removing part of or all of the fin parts with the thickness between the second isolation layers to form an opening, wherein the protection layer is positioned on the side wall of the opening; cleaning the opening; after the opening is cleaned, a channel layer filled in the opening is formed, and the material of the channel layer is different from that of the fin portion; after the channel layer is formed, removing part of the thickness of the second isolation layer, so that the top of the rest second isolation layer is higher than the bottom of the channel layer; and removing the protective layer exposed by the residual second isolation layer after removing part of the second isolation layer.
Optionally, the step of forming the protective layer includes: forming a protective film on the first isolation layer, wherein the protective film covers the fin part higher than the top of the first isolation layer; and removing the protective films positioned on the tops of the first isolation layer and the fin portion to form the protective layer.
Optionally, in a direction parallel to the surface of the semiconductor substrate and perpendicular to the extending direction of the fin portion, the thickness of the protection layer is: 20 angstroms to 60 angstroms.
Optionally, the process for forming the protective layer includes: and (5) an atomic layer deposition process.
Optionally, the process of performing the cleaning treatment on the opening includes: SiCoNi process.
Optionally, the step of forming the channel layer includes: forming a channel epitaxial layer in the opening, wherein the top of the channel epitaxial layer is higher than the top of the second isolation layer; and carrying out planarization treatment on the channel epitaxial layer, and removing the channel epitaxial layer higher than the top of the second isolation layer to form the channel layer.
Optionally, the channel layer is made of SiGe, Ge, or InAs.
Optionally, the hardness of the material of the protective layer is greater than that of the material of the first isolation layer; the material hardness of the protective layer is greater than that of the second isolation layer.
Optionally, the material of the protective layer includes one or more of SiN, SiBCN, SiOCN, or SiCN.
Optionally, the step of forming the second isolation layer includes: forming a second isolation film covering the fin portion, wherein the top of the second isolation film is higher than that of the fin portion; and carrying out planarization treatment on the second isolation film to expose the top of the fin part and form the second isolation layer.
Optionally, in a direction perpendicular to the surface of the semiconductor substrate, the height of the channel layer is: 5nm to 8 nm.
Optionally, in the step of removing the second isolation layer with a partial thickness, the thickness of the second isolation layer is removed in a range from 300 angstroms to 700 angstroms.
Optionally, the process of removing the protection layer exposed by the remaining second isolation layer includes: and (5) dry etching process.
Optionally, the semiconductor substrate includes a first region for forming an NMOS device and a second region for forming a PMOS device.
Optionally, the channel layer is located in the first region; the process steps for forming the opening include: forming a pattern layer on the second isolation layer of the first region, wherein the pattern layer also covers the top of the fin part of the first region; and removing part or all of the fin part with the thickness between the second isolation layers of the second region by taking the pattern layer as a mask to form the opening.
Correspondingly, the invention also provides a fin field effect transistor, which comprises: a semiconductor substrate having a plurality of discrete fin portions thereon; the first isolation layer is positioned on the semiconductor substrate with the exposed fin portion, covers the side wall of the fin portion, and is lower than the top of the fin portion in top; the channel layer is positioned on the top of the fin part, and the material of the channel layer is different from that of the fin part; a second isolation layer located on the first isolation layer, wherein the second isolation layer covers part of the side wall of the channel layer, and the top of the second isolation layer is higher than the bottom of the channel layer; a protective layer between the second isolation layer and the channel layer sidewall.
Optionally, the hardness of the material of the protective layer is greater than that of the material of the first isolation layer; the material hardness of the protective layer is greater than that of the second isolation layer.
Optionally, the material of the channel layer includes: SiGe, Ge or InAs.
Optionally, in a direction perpendicular to the surface of the semiconductor substrate, the height of the channel layer is: 5nm to 8 nm.
Optionally, the material of the protective layer includes one or more of SiN, SiBCN, SiOCN, or SiCN.
Compared with the prior art, the technical scheme of the invention has the following advantages:
forming a protective layer on the fin portion exposed by the first isolation layer, and forming a channel layer filled in the opening after the protective layer is formed, wherein the channel layer is made of a material different from that of the fin portion. According to the invention, the protective layer is formed on the fin part exposed out of the first isolation layer, so that the protective layer protects the second isolation layer in the cleaning process, the influence of the corrosion of the side wall of the second isolation layer by a cleaning solution is improved, and the problem of the increase of the size of the opening is avoided. Therefore, after the opening is cleaned, a channel layer is formed to fill the opening, and the size of the channel layer is the same as that of the opening. The technical scheme of the invention improves the problem of size increase of the channel layer, thereby improving the electrical performance of the fin field effect transistor.
In an optional technical solution, the thickness of the protection layer is 20 to 60 angstroms in a direction parallel to the surface of the semiconductor substrate and perpendicular to the extending direction of the fin portion. If the thickness of the protective layer is too small, the protective effect of the protective layer on the second isolation layer is poor in the process of cleaning the opening; if the thickness of the opening is too large, the difficulty of the subsequent process for removing the protective layer is large. Therefore, the protective layer of the present invention has a thickness ranging from 20 angstroms to 60 angstroms, so that the aforementioned problems are alleviated, thereby further improving the electrical performance of the finfet.
Drawings
Fig. 1 to 9 are schematic structural diagrams corresponding to respective steps of a finfet formation method;
fig. 10 to 22 are schematic structural views corresponding to steps of a method for forming a finfet device according to an embodiment of the present invention.
Detailed Description
The electrical performance of the finfet formed according to the background art needs to be improved. Now, the reason why the electrical performance of the fin field effect transistor needs to be improved is analyzed by combining a method for forming the fin field effect transistor.
Referring to fig. 1 to 9, schematic structural diagrams corresponding to steps of a finfet formation method are shown.
Referring to fig. 1, a semiconductor substrate 100 is provided, the semiconductor substrate 100 having a plurality of discrete fins 110 thereon, the fins 110 having a hard mask 111 on top thereof; the semiconductor substrate 100 includes a first region I for forming NMOS devices and a second region II for forming PMOS devices.
Referring to fig. 2, an isolation layer 120 is formed on the semiconductor substrate 100 where the fins 110 are exposed, and the top of the isolation layer 120 is flush with the top of the hard mask 111.
Referring to fig. 3, the isolation layer 120 is removed to expose the top of the fin 110, and the hard mask 111 (see fig. 2) on the top of the fin 110 is removed during the process of removing the isolation layer 120.
Referring to fig. 4, a pattern layer 131 is formed on top of the isolation layer 120 in the first region I, and the pattern layer 131 also covers the top of the fin 110 in the first region I.
Referring to fig. 5, the pattern layer 131 is used as a mask to remove a portion of the thickness of the fin 110 between the isolation layers 120 in the second region II, thereby forming an opening 140.
Referring to fig. 6, after the opening 140 is formed, a cleaning process is performed on the opening 140.
Referring to fig. 7, a channel epitaxial layer 150 is formed to fill the opening 140, and the top of the channel epitaxial layer 150 is higher than the top of the isolation layer 120.
Referring to fig. 8, the channel epitaxial layer 150 is planarized, and the channel epitaxial layer 150 above the top of the isolation layer 120 is removed to form a channel layer 151; the pattern layer 131 is removed during the planarization process of the channel epitaxial layer 150 (refer to fig. 7).
Referring to fig. 9, a portion of the thickness of the isolation layer 120 is removed such that the top of the remaining isolation layer 120 is higher than the bottom of the channel layer 151.
The electrical performance of the fin field effect transistor formed by the forming method needs to be improved.
The analysis shows that the reasons for the improvement of the electrical performance of the finfet include: after the opening 140 is formed, in the step of performing the cleaning process on the opening 140, since the material of the isolation layer 120 has a low hardness, it is easily corroded by the cleaning solution, so that the size of the opening 140 (refer to fig. 5 and 6 in combination) is increased. Accordingly, the size of the channel layer 151 formed to fill the opening 140 may be large due to the opening 140 providing a process basis for the subsequent formation of the channel layer 151, thereby reducing the electrical performance of the finfet.
In order to solve the above technical problem, the present invention provides a method for forming a fin field effect transistor, including: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a plurality of discrete fin parts; forming a first isolation layer on the semiconductor substrate exposed out of the fin portion, wherein the first isolation layer covers part of the side wall of the fin portion, and the top of the first isolation layer is lower than the top of the fin portion; forming a protective layer on the side wall of the fin part exposed out of the first isolation layer; forming a second isolation layer between the fin parts, wherein the second isolation layer covers the top of the first isolation layer and the side wall of the protection layer; after the second isolation layers are formed, removing part of or all of the fin parts with the thickness between the second isolation layers to form an opening, wherein the protection layer is positioned on the side wall of the opening; cleaning the opening; after the opening is cleaned, a channel layer filled in the opening is formed, and the material of the channel layer is different from that of the fin portion; after the channel layer is formed, removing part of the thickness of the second isolation layer, so that the top of the rest second isolation layer is higher than the bottom of the channel layer; and removing the protective layer exposed by the residual second isolation layer after removing part of the second isolation layer.
Before the step of forming the opening, the protective layer is formed on the fin part exposed out of the first isolation layer, so that the protective layer can protect the second isolation layer in the cleaning process, the influence of the corrosion of the side wall of the second isolation layer by the cleaning solution is improved, and the problem of the increase of the size of the opening is avoided.
After the opening is cleaned, a channel layer is formed to fill the opening, the size of the channel layer is the same as that of the formed opening, and due to the protective layer arranged on the side wall of the opening, the size of the opening is not increased due to corrosion of a cleaning solution in the process of cleaning the opening, and correspondingly, the size of the formed channel layer is kept unchanged. Compared with the technical scheme that the protective layer is not formed, the channel layer structure solves the problem that the size of the channel layer is enlarged, and therefore the electrical performance of the fin field effect transistor is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 10 to 22 are schematic structural views corresponding to steps of a method for forming a finfet device according to an embodiment of the present invention.
Referring to fig. 10, a semiconductor substrate 200 is provided, the semiconductor substrate 200 having a plurality of discrete fins 210 thereon.
In this embodiment, the semiconductor substrate 200 includes a first region I for forming an NMOS device and a second region II for forming a PMOS device, and accordingly, the formed finfet is a CMOS device. In other embodiments of the present invention, the semiconductor substrate may include only one of the first region for forming an NMOS device or the second region for forming a PMOS device, and accordingly, the formed fin field effect transistor is an NMOS device or a PMOS device.
In this embodiment, the material of the semiconductor substrate 200 is silicon. In other embodiments of the present invention, the material of the semiconductor substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In other embodiments, the semiconductor substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the fin 210 is made of silicon. In other embodiments of the present invention, the material of the fin portion may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the fin fet further includes: a hard mask 211 on top of the fin 210. The hard mask 211 is used to protect the top of the fin 210 in a subsequent process of forming a first isolation layer.
In this embodiment, the hard mask 211 is made of silicon nitride; in other embodiments of the present invention, the material of the hard mask may also be silicon oxynitride, silicon carbide, or boron nitride.
Referring to fig. 11 and 12 in combination, a first isolation layer 221 is formed on the semiconductor substrate 200 exposed by the fin 210 (as shown in fig. 12), the first isolation layer 221 covers a portion of the sidewall of the fin 210, and the top of the first isolation layer 221 is lower than the top of the fin 210.
Referring to fig. 11, an initial first isolation film is formed on the semiconductor substrate 200 exposed by the fin 210, and the top of the initial first isolation film is higher than the top of the fin 210; and performing planarization treatment on the top of the initial first isolation film to expose the top of the hard mask 211, thereby forming a first isolation film 220.
The first isolation film 220 provides a process foundation for the subsequent formation of the first isolation layer.
In this embodiment, the first isolation film 220 is made of SiO2。
Referring to fig. 12, after the first isolation film 220 (see fig. 11) is planarized, the first isolation film 220 is etched back to remove a portion of the thickness thereof, so as to form a first isolation layer 221, where the first isolation layer 221 covers a portion of the sidewall of the fin 210, and the top of the first isolation layer 221 is lower than the top of the fin 210.
The first isolation layer 221 may function to electrically isolate adjacent fins 210.
In this embodiment, the first isolation layer 221 is made of SiO2。
The process of etching back to remove a portion of the thickness of the first isolation film 220 includes: dry etching or wet etching. In this embodiment, the process of removing the first isolation film 220 with a part of the thickness by back etching is dry etching.
Referring to fig. 13 and 14, a protection layer 231 is formed on the sidewalls of the fin 210 exposed by the first isolation layer 221.
The step of forming the protective layer 231 will be described in detail below with reference to the accompanying drawings.
Referring to fig. 13, a protection film 230 is formed on the first isolation layer 221, and the protection film 230 covers the fin 210 higher than the top of the first isolation layer 221.
The protective film 230 provides a process base for forming a protective layer in a subsequent process.
In this embodiment, the material of the protection film 230 is SiN; in other embodiments of the present invention, the material of the protection film 230 may also be one or more of SiBCN, SiOCN, or SiCN.
The process of forming the protective film 230 includes: physical vapor deposition, chemical vapor deposition, or atomic layer deposition. In this embodiment, the protective film 230 is formed by an atomic layer deposition process, so that the deposition effect of the protective film 230 is improved. Accordingly, the quality of the subsequently formed protection layer 230 is also improved.
Referring to fig. 14, the protective film 230 on top of the first isolation layer 221 and on top of the fin 210 is removed to form a protective layer 231.
The protection layer 231 is used for protecting a second isolation layer formed subsequently in a subsequent step of cleaning the opening, so as to avoid or reduce the problem that the opening is enlarged due to the corrosion influence of the cleaning solution on the second isolation layer. Accordingly, since the channel layer is formed to fill the opening after the opening is cleaned, and the size of the channel layer is the same as that of the opening, the protection layer 231 solves the problem of size increase of the subsequently formed channel layer, thereby improving the electrical performance of the fin field effect transistor.
In order to exert the protective effect of the protective layer 231 well, the protective layer 231 is made of a material having high hardness and being less susceptible to washing and corrosion. Since the first isolation layer 221 and the second isolation layer formed later have lower hardness and are susceptible to corrosion by a cleaning solution, the material of the protection layer 231 is different from that of the first isolation layer 221, and the material of the protection layer 231 is also different from that of the second isolation layer formed later.
The material hardness of the protection layer 231 is greater than that of the first isolation layer 221, and the material hardness of the protection layer 231 is also greater than that of a second isolation layer to be formed later. Therefore, in this embodiment, the material of the protection layer 231 is SiN with a relatively high hardness; in other embodiments of the present invention, the material of the protection layer may also be one or more of SiBCN, SiOCN, or SiCN.
It should be noted that the thickness of the protection layer 231 in the direction parallel to the surface of the semiconductor substrate 200 and perpendicular to the extending direction of the fin 210 cannot be too large or too small. If the thickness of the protection layer 231 is too small, the protection effect of the protection layer 231 on a subsequently formed second isolation layer is poor in the subsequent process of cleaning the opening, and even the protection effect of the second isolation layer on being corroded by the cleaning solution cannot be achieved; if the thickness of the protection layer 231 is too large, the subsequent process for removing the protection layer 231 is difficult, and the process material is wasted. Therefore, in the present embodiment, the thickness of the protection layer 231 is in the range of 20 to 60 angstroms in the direction parallel to the surface of the semiconductor substrate 200 and perpendicular to the extending direction of the fin 210.
Referring to fig. 15, a second isolation layer 240 is formed between the fins 210, and the second isolation layer 240 covers the top of the first isolation layer 221 and the sidewalls of the protection layer 231.
The second isolation layer 240 and the first isolation layer 221 both function to electrically isolate adjacent fins 210; and the second isolation layer 240 can also provide a process foundation for the subsequent formation of an opening and the filling of the channel layer in the opening.
In this embodiment, the material of the second isolation layer 240 is SiO2. The step of forming the second isolation layer 240 includes: forming a second isolation film on the first isolation layer 221 exposed out of the fin portion 210, wherein the top of the second isolation film is higher than that of the fin portion 210; after the second isolation film is formed, the top of the second isolation film is planarized until the top of the fin 210 is exposed, so as to form the second isolation layer 240, and the second isolation layer 240 covers the top of the first isolation layer 221 and the sidewall of the protection layer 231.
With reference to fig. 16 to 18, after forming the second isolation layers 240, the fin 210 located between the second isolation layers 240 is removed by a portion of the thickness to form an opening 260, and the protection layer 231 is located on the sidewall of the opening 260; the opening 260 is subjected to a cleaning process.
The steps of forming the opening 260 and performing the cleaning process on the opening 260 will be described in detail with reference to the accompanying drawings.
Referring to fig. 16, a patterned film 250 is formed on the second isolation layer 240, and the patterned film 250 covers the top of the fin 210.
The graphic film 250 provides a process basis for graphic processing for the subsequent formation of a graphic layer.
In this embodiment, the pattern film 250 is made of SiN. In other embodiments of the present invention, the material of the pattern film may also be a photoresist, a bottom anti-reflective coating, or a top anti-reflective coating.
Referring to fig. 17, the patterned film 250 is patterned to form a patterned layer 251 on the second isolation layer 240 in the first region I, where the patterned layer 251 also covers the top of the fin portion 210 in the first region I.
The pattern layer 251 is used as a mask for forming an opening in the following step, and is used to protect the fin portion 210 located in the first region I, so that in the step of forming the opening, only the fin portion 210 located between the second isolation layers 240 in the second region II is removed, thereby forming the opening in the second region II.
In this embodiment, the step of performing the patterning process on the graphic film 250 includes: forming a patterned photoresist layer on the pattern film 250; and etching the graphic film 250 by using the patterned photoresist layer as a mask to form a graphic layer 251 on the second isolation layer 240 in the first region I.
In this embodiment, the pattern layer 251 is made of SiN. In other embodiments of the present invention, the material of the pattern layer 251 may also be photoresist, bottom anti-reflective coating, or top anti-reflective coating.
Referring to fig. 18, the pattern layer 251 is used as a mask to remove the fin portion 210 located between the second isolation layers 240 in the second region II with a partial thickness, so as to form an opening 260; after the opening 260 is formed, a cleaning process is performed on the opening 260.
The opening 260 provides a spatial location for a subsequently formed channel layer filling the opening 260, so that the size of the subsequently formed channel layer is consistent with the size of the opening 260.
In this embodiment, the pattern layer 251 is used as a mask, and only a portion of the fin portion 210 with a thickness between the second isolation layers 240 in the second region II is removed, so that the bottom of the formed opening 260 is higher than the top of the first isolation layer 221, and a protection layer 231 is formed on the sidewall of the opening 260. In other embodiments of the present invention, the pattern layer may be used as a mask to remove the fin portion with the whole thickness between the second isolation layers in the second region, so that the bottom of the opening is flush with the top of the first isolation layer, and a protection layer is formed on the sidewall of the opening.
The opening 260 is cleaned, so that the cleanliness of the opening 260 is improved, and the quality of a subsequently formed channel layer is improved. Since the protection layer 231 is formed on the sidewall of the opening 260, the protection layer 231 has a protection effect on the opening 260, so that the opening 260 is not easily affected by the cleaning solution, and the size of the opening 260 is maintained after the cleaning process.
In this embodiment, the process of cleaning the opening 260 includes: SiCoNi process. Specifically, the SiCoNi etching process comprises the following steps: with NF3And NH3The mixed gas of (2) is used as etching gas; by reacting the etching gas with impurities located in the opening 260, by-products are formed; sublimating and decomposing the by-product into gaseous products; and removing the gaseous product by air suction.
Referring to fig. 19 and 20 in combination, after the cleaning process is performed on the opening 260, a channel layer 271 filling the opening 260 is formed, and a material of the channel layer 271 is different from a material of the fin 210.
Referring to fig. 19, a channel epitaxial layer 270 is formed in the opening 260, and the top of the channel epitaxial layer 270 is higher than the top of the second isolation layer 240.
The channel epitaxial layer 270 provides a process foundation for the subsequent formation of a channel layer.
In this embodiment, the channel epitaxial layer 270 is formed by a selective epitaxial growth process. The material of the channel epitaxial layer 270 is SiGe. In other embodiments of the present invention, the material of the channel epitaxial layer may also be Ge or InAs.
Referring to fig. 20, the channel epitaxial layer 270 (see fig. 19) is planarized, and the channel epitaxial layer 270 above the top of the second isolation layer 240 is removed to form a channel layer 271.
In this embodiment, a protective layer 231 is further formed on the sidewall of the channel layer 271. Since the channel layer 271 is formed on the basis of filling the opening 260 (refer to fig. 18), accordingly, the size of the channel layer 271 is the same as that of the opening 260. In this embodiment, after the step of forming the opening 260 and before the step of forming the channel layer 271, the opening 260 is cleaned to improve the cleanliness of the opening 260, so that the quality of the channel epitaxial layer 270 is improved, and the quality of the channel layer 271 is improved.
It should be noted that, in the step of cleaning the opening 260, since the protective layer 231 is formed on the sidewall of the opening 260, the protective layer 231 can protect the second isolation layer 240, and the second isolation layer 240 is prevented from being corroded by the cleaning solution, so that the problem of size increase of the opening 260 is avoided or reduced, and the problem of size increase of the channel layer 271 is correspondingly avoided or reduced, thereby improving the electrical performance of the fin-type field effect transistor.
The channel layer 271 can improve the carrier mobility of the fin field effect transistor, so that the electrical performance of the fin field effect transistor is improved. Therefore, in this embodiment, the material of the channel layer 271 is a SiGe material capable of improving carrier mobility. In other embodiments of the present invention, the material of the channel layer may also be Ge or InAs.
The height of the channel layer 271 in a direction perpendicular to the surface of the semiconductor substrate 200 cannot be too large nor too small. If the height of the channel layer 271 is too large, the short channel effect of the fin field effect transistor is severe; if the height of the channel layer 271 is too small, the process requirement of the fin field effect transistor is not easily met in the subsequent process. Therefore, in the present embodiment, the height of the channel layer 271 in the direction perpendicular to the surface of the semiconductor substrate 200 is 5nm to 8 nm.
Referring to fig. 21, after the channel layer 271 is formed, a partial thickness of the second isolation layer 240 is removed such that the top of the remaining second isolation layer 240 is higher than the bottom of the channel layer 271.
The remaining second isolation layer 240 and the first isolation layer 221 can function to electrically isolate adjacent fins 210.
In the step of removing a part of the thickness of the second isolation layer 240, the thickness of the second isolation layer 240 is neither too large nor too small. If the thickness of the second isolation layer 240 is too large, the isolation effect of the remaining second isolation layer 240 is poor; if the thickness of the second isolation layer 240 is too small, the height of the channel layer 271 exposed by the remaining second isolation layer 240 is too small, so that the channel layer 271 cannot easily meet the process requirement of the fin field effect transistor in the subsequent process. Therefore, in the present embodiment, in the step of removing the second isolation layer 240 with a partial thickness, the thickness of the second isolation layer 240 is removed in a range from 300 angstroms to 700 angstroms.
Referring to fig. 22, after removing a portion of the thickness of the second isolation layer 240, the protection layer 231 exposed by the remaining second isolation layer 240 is removed.
The process of removing the protection layer 231 exposed by the remaining second isolation layer 240 includes a wet etching, dry etching, or ashing process. In this embodiment, the process of removing the protection layer 231 exposed by the remaining second isolation layer 240 is dry etching.
Correspondingly, the invention further provides a fin field effect transistor, and referring to fig. 22, a schematic structural diagram of an embodiment of the fin field effect transistor of the invention is shown. The fin field effect transistor includes: a semiconductor substrate 200, wherein the semiconductor substrate 200 has a plurality of discrete fins 210 thereon; a first isolation layer 221 located on the semiconductor substrate 200 exposed from the fin 210, wherein the first isolation layer 221 covers a sidewall of the fin 210, and a top of the first isolation layer 221 and a top of the fin 210 are lower than a top of the fin 210; a channel layer 271 located on top of the fin 210, and a material of the channel layer 271 is different from a material of the fin 210; a second isolation layer 240 on the first isolation layer 221, wherein the second isolation layer 240 covers a portion of the sidewall of the channel layer 271, and the top of the second isolation layer 240 is higher than the bottom of the channel layer 271; a protective layer 231 between the second isolation layer 240 and the sidewall of the channel layer 271.
In this embodiment, the semiconductor substrate 200 includes a first region I having an NMOS device and a second region II having a PMOS device, and accordingly, the formed fin field effect transistor is a CMOS device. In other embodiments of the present invention, the semiconductor substrate may include only one of the first region having an NMOS device or the second region having a PMOS device, and accordingly, the formed fin field effect transistor is an NMOS device or a PMOS device.
In this embodiment, the material of the semiconductor substrate 200 is silicon. In other embodiments of the present invention, the material of the semiconductor substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In other embodiments, the semiconductor substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the fin 210 is made of silicon. In other embodiments of the present invention, the material of the fin portion may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
The first isolation layer 221 may function to electrically isolate adjacent fins 210. In this embodiment, the first isolation layer 221 is made of silicon oxide.
In this embodiment, the top of the first isolation layer 221 is lower than the top of the fin 210. In other embodiments of the present invention, the top of the first isolation layer may be flush with the top of the fin.
In this embodiment, a protection layer 231 is disposed between the second isolation layer 240 and the sidewall of the channel layer 271, and the protection layer 231 is used to protect the second isolation layer 240. In this embodiment, the hardness of the material of the protection layer 231 is greater than that of the first isolation layer 221; the material hardness of the protection layer 231 is also greater than that of the second isolation layer 240. Specifically, SiN with high hardness is used as the material of the protective layer 231; in other embodiments of the present invention, the material of the protection layer may also be one or more of SiBCN, SiOCN, or SiCN.
The second isolation layer 240 and the first isolation layer 221 both function to electrically isolate adjacent fins 210. In this embodiment, the material of the second isolation layer 240 is silicon oxide.
The channel layer 271 can improve the carrier mobility of the fin field effect transistor, so that the electrical performance of the fin field effect transistor is improved. Therefore, in this embodiment, the material of the channel layer 271 is a SiGe material capable of improving carrier mobility. In other embodiments of the present invention, the material of the channel layer may also be Ge or InAs.
The height of the channel layer 271 in a direction perpendicular to the surface of the semiconductor substrate 200 cannot be too large nor too small. If the height of the channel layer 271 is too large, the short channel effect of the fin field effect transistor is severe; if the height of the channel layer 271 is too small, the requirement of the fin field effect transistor on the process manufacturing is not easily met. Therefore, in the present embodiment, the height of the channel layer 271 in the direction perpendicular to the surface of the semiconductor substrate 200 is 5nm to 8 nm.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A method for forming a fin field effect transistor (FinFET) is characterized by comprising the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a plurality of discrete fin parts;
forming a first isolation layer on the semiconductor substrate exposed out of the fin portion, wherein the first isolation layer covers part of the side wall of the fin portion, and the top of the first isolation layer is lower than the top of the fin portion;
forming a protective layer on the side wall of the fin part exposed out of the first isolation layer;
forming a second isolation layer between the fin parts, wherein the second isolation layer covers the top of the first isolation layer and the side wall of the protection layer;
after the second isolation layers are formed, removing part of or all of the fin parts with the thickness between the second isolation layers to form an opening, wherein the protection layer is positioned on the side wall of the opening;
cleaning the opening;
after the opening is cleaned, a channel layer filled in the opening is formed, and the material of the channel layer is different from that of the fin portion;
after the channel layer is formed, removing part of the thickness of the second isolation layer, so that the top of the rest second isolation layer is higher than the bottom of the channel layer;
and removing the protective layer exposed by the residual second isolation layer after removing part of the second isolation layer.
2. The method of claim 1, wherein forming the protective layer comprises:
forming a protective film on the first isolation layer, wherein the protective film conformally covers the fin part higher than the top of the first isolation layer;
and removing the protective films positioned on the tops of the first isolation layer and the fin portion to form the protective layer.
3. The method of claim 1, wherein a thickness of the protective layer in a direction parallel to the surface of the semiconductor substrate and perpendicular to a fin extension direction is: 20 angstroms to 60 angstroms.
4. The method of claim 1, wherein forming the protective layer comprises: and (5) an atomic layer deposition process.
5. The method of claim 1, wherein the step of cleaning the opening comprises: SiCoNi process.
6. The method of claim 1, wherein forming the channel layer comprises:
forming a channel epitaxial layer in the opening, wherein the top of the channel epitaxial layer is higher than the top of the second isolation layer;
and carrying out planarization treatment on the channel epitaxial layer, and removing the channel epitaxial layer higher than the top of the second isolation layer to form the channel layer.
7. The method of claim 1, wherein the channel layer is formed of SiGe, Ge, or InAs.
8. The method of claim 1, wherein a material hardness of the protective layer is greater than a material hardness of the first isolation layer; the material hardness of the protective layer is greater than that of the second isolation layer.
9. The method of claim 8, wherein a material of the protective layer comprises one or more of SiN, SiBCN, SiOCN, or SiCN.
10. The method of claim 1, wherein forming the second isolation layer comprises:
forming a second isolation film covering the fin portion, wherein the top of the second isolation film is higher than that of the fin portion;
and carrying out planarization treatment on the second isolation film to expose the top of the fin part and form the second isolation layer.
11. The method of claim 1, wherein a height of the channel layer in a direction perpendicular to a surface of the semiconductor substrate is: 5nm to 8 nm.
12. The method of claim 1, wherein the removing the partial thickness of the second isolation layer comprises removing the second isolation layer to a thickness in a range from about 300 angstroms to about 700 angstroms.
13. The method of claim 1, wherein removing the exposed protective layer of the remaining second isolation layer comprises: and (5) dry etching process.
14. The method of claim 1, wherein the semiconductor substrate comprises a first region for forming an NMOS device and a second region for forming a PMOS device.
15. The method of claim 14, wherein the channel layer is located in the first region; the process steps for forming the opening include:
forming a pattern layer on the second isolation layer of the first region, wherein the pattern layer also covers the top of the fin part of the first region;
and removing part or all of the fin part with the thickness between the second isolation layers of the second region by taking the pattern layer as a mask to form the opening.
16. A fin field effect transistor, comprising:
a semiconductor substrate having a plurality of discrete fin portions thereon;
the first isolation layer is positioned on the fin portion exposed out of the semiconductor substrate, covers the side wall of the fin portion, and is lower than the top of the fin portion in top;
the channel layer is positioned on the top of the fin portion, the material of the channel layer is different from that of the fin portion, and the bottom of the channel layer is in contact with the top of the fin portion;
a second isolation layer located on the first isolation layer, wherein the second isolation layer covers part of the side wall of the channel layer, and the top of the second isolation layer is higher than the bottom of the channel layer;
a protective layer between the second isolation layer and the channel layer sidewall.
17. The finfet of claim 16, wherein the protective layer has a material hardness greater than a material hardness of the first isolation layer; the material hardness of the protective layer is greater than that of the second isolation layer.
18. The fin-fet of claim 16, wherein the channel layer material comprises: SiGe, Ge or InAs.
19. The fin-fet of claim 16, wherein a height of the channel layer in a direction perpendicular to a surface of the semiconductor substrate is: 5nm to 8 nm.
20. The fin field effect transistor of claim 16, wherein a material of the protective layer includes one or more of SiN, SiBCN, SiOCN, or SiCN.
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| US9257344B2 (en) * | 2009-12-03 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with different fin height and EPI height setting |
| CN105374874A (en) * | 2014-08-19 | 2016-03-02 | 台湾积体电路制造股份有限公司 | Structure and method and finfet device |
| US9324618B1 (en) * | 2015-06-01 | 2016-04-26 | Globalfoundries Inc. | Methods of forming replacement fins for a FinFET device |
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| KR100739658B1 (en) * | 2006-07-03 | 2007-07-13 | 삼성전자주식회사 | Method for manufacturing semiconductor device |
| CN104733312B (en) * | 2013-12-18 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin formula field effect transistor |
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|---|---|---|---|---|
| US9257344B2 (en) * | 2009-12-03 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with different fin height and EPI height setting |
| CN103325832A (en) * | 2012-03-20 | 2013-09-25 | 台湾积体电路制造股份有限公司 | FINFET with metal gate stressor |
| CN105374874A (en) * | 2014-08-19 | 2016-03-02 | 台湾积体电路制造股份有限公司 | Structure and method and finfet device |
| US9324618B1 (en) * | 2015-06-01 | 2016-04-26 | Globalfoundries Inc. | Methods of forming replacement fins for a FinFET device |
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