CN108269542B

CN108269542B - Display device

Info

Publication number: CN108269542B
Application number: CN201810003539.0A
Authority: CN
Inventors: 杨艳娜
Original assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Priority date: 2018-01-03
Filing date: 2018-01-03
Publication date: 2020-03-03
Anticipated expiration: 2038-01-03
Also published as: WO2019134616A1; US20200372869A1; US11132966B2; CN108269542A

Abstract

The sub-pixels of the display panel of the display device are electrically connected with the gate lines of the corresponding rows, the data lines are respectively and electrically connected with two adjacent sub-pixels of the same pixel, in the first pixel group, the first gate line and the third gate line are respectively and electrically connected with the sub-pixels of the same column, the second gate line and the fourth gate line are respectively and electrically connected with the sub-pixels of the same column, in the second pixel group, the first gate line and the fourth gate line are respectively and electrically connected with the sub-pixels of the same column, and the second gate line and the third gate line are respectively and electrically connected with the sub-pixels of the same column. In one frame time, the polarities of the data signals driving the same pixel through the nth data line and the (n +1) th data line are opposite, and the polarities of the data signals driving the two adjacent sub-pixels in the column direction of the same pixel group through the nth data line and the (n +1) th data line are the same. The application can improve the problem of vertical crosstalk.

Description

Display device

Technical Field

The present disclosure relates to a display device, and more particularly, to a display device capable of improving vertical crosstalk.

Background

With the progress of technology, flat panel display devices have been widely used in various fields, such as liquid crystal display devices, which have the excellent characteristics of light weight, low power consumption and no radiation, and thus have gradually replaced the conventional cathode ray tube display devices and are applied to various electronic products, such as mobile phones, portable multimedia devices, notebook computers, liquid crystal televisions and liquid crystal screens.

The liquid crystal display device mainly utilizes an electric field to control the rotation of liquid crystal molecules, so that light can pass through the liquid crystal molecules to display images. Among them, a sub-pixel arrangement (e.g., WRGB or other colors) having a pixel including four colors is currently accepted by the market due to the advantage of high transmittance, and manufacturers start to develop new technologies based on this. With the increasing resolution and scanning frequency of displays, in order to reduce the number of source driver ICs, many products have been designed to change the arrangement of pixels from a vertical arrangement of one gate line with one data line (1G1D) to two gate lines with one data line: in a Half Source Driving (HSD) manner, HSD technology is helpful to increase the production capacity as well as reduce the number of source driving ICs.

In addition, in order to increase the aperture ratio and the viewing angle, the current products tend to use a 4-domain (domain) dual pixel rendering (two pixel rendering) technique, which utilizes the combination of two sub-pixels to control the liquid crystal in different directions by different voltages respectively, so as to render two sub-pixels that are dark and bright. In addition, in order to make the display image more uniform, in the prior art, the 4 area sub-pixels of the dark area are arranged in a checkerboard manner, and the 4 area sub-pixels of the bright area include a design manner of positive and negative polarities under the whole display, so as to reduce the flicker of the display image. However, the biggest problem of this pixel design is that the sub-pixels of the same color cannot cancel each other within one frame time (frame time) due to parasitic capacitive coupling, and therefore vertical crosstalk (crosstalk) of the display screen is caused, resulting in a reduction in the screen quality.

Disclosure of Invention

In view of the deficiencies of the prior art, the inventors have developed the present application. The present application provides a display device, which can improve the problem of the quality reduction of the display image caused by the vertical crosstalk.

The present application provides a display device, which includes a display panel, wherein the display panel includes a plurality of gate lines, a plurality of data lines, a plurality of pixels arranged along a row direction and a column direction, and a driving circuit. The data lines and the gate lines are arranged in a staggered mode, the data lines comprise an nth data line and an n +1 th data line, and n is an odd number. The plurality of sub-pixels arranged along the row direction are respectively and electrically connected with two adjacent gate lines of a corresponding row, each data line is respectively and electrically connected with two adjacent sub-pixels of the same pixel, two adjacent pixels arranged along the column direction respectively form a pixel group, two adjacent pixel groups arranged along the column direction are a first pixel group and a second pixel group, the first pixel group and the second pixel group are respectively and sequentially connected with a first gate line, a second gate line, a third gate line and a fourth gate line, in the first pixel group, the first gate line and the third gate line are respectively and electrically connected with the sub-pixels of the same row, the second gate line and the fourth gate line are respectively and electrically connected with the sub-pixels of the same row, in the second pixel group, the first gate line and the fourth gate line are respectively and electrically connected with the sub-pixels of the same row, and the second gate line and the third gate line are respectively and electrically connected with the sub-pixels of the same row, and the sub-pixels electrically connected with the fourth gate line of the first pixel group and the first gate line of the second pixel group are positioned in the same column. The driving circuit transmits a data signal to drive a plurality of pixels through a plurality of data lines; in one frame time, the polarities of two adjacent sub-pixels of the same pixel driven by the data signal through the nth data line or the (n +1) th data line are opposite, the polarities of the same pixel driven by the data signal through the nth data line and the (n +1) th data line are opposite, and the polarities of two adjacent sub-pixels in the column direction of the same pixel group driven by the data signal through the nth data line and the (n +1) th data line are the same.

In one embodiment, the color arrangement order of the sub-pixels of the plurality of colors of each pixel is the same.

In one embodiment, the nth data line and the (n +1) th data line are connected to the same pixel.

In one embodiment, in different pixel groups, the polarities of two sub-pixels of the first pixel group and the second pixel group adjacent in the column direction driven by the data signal through the nth data line or the (n +1) th data line are opposite.

In one embodiment, in each pixel group, the polarities of two adjacent sub-pixels of the same pixel connected to the nth data line and the (n +1) th data line are the same.

In one embodiment, the polarities of the voltages applied to the sub-pixels of each pixel in the same row are the same.

In one embodiment, each pixel includes four color sub-pixels arranged in a row direction.

In one embodiment, the color of the sub-pixels connected to the nth data line is wrwrwrrwwr, and the sequence is repeated, and the color of the sub-pixels connected to the (n +1) th data line is GBGBBGGB, and the sequence is repeated, where W is white, R is red, G is green, and B is blue.

In one embodiment, in one frame time, the driving circuit makes one of two pixels adjacent to each other in the column direction be a bright area and the other pixel be a dark area, and the positive-negative polarity ratio of bright area sub-pixels of the same color arranged along the column direction is 1: 1.

the present application further provides a display device, which includes a display panel, wherein the display panel includes a plurality of gate lines, a plurality of data lines, a plurality of pixels arranged along a row direction and a column direction, and a driving circuit. The data lines and the gate lines are arranged in a staggered mode, the data lines comprise an nth data line and an n +1 th data line, and n is an odd number. Each pixel comprises four colors of sub-pixels arranged along the row direction, the color arrangement sequence of the sub-pixels of the multiple colors of each pixel is the same, the plurality of sub-pixels arranged along the row direction are respectively and electrically connected with two adjacent gate lines of the corresponding row, each data line is respectively and electrically connected with two adjacent sub-pixels of the same pixel, two adjacent pixels arranged along the column direction respectively form a pixel group, the two adjacent pixel groups arranged along the column direction are a first pixel group and a second pixel group, the first pixel group and the second pixel group are respectively and sequentially connected with a first gate line, a second gate line, a third gate line and a fourth gate line, in the first pixel group, the first gate line and the third gate line are respectively and electrically connected with the sub-pixels of the same row, the second gate line and the fourth gate line are respectively and electrically connected with the sub-pixels of the same row, in the second pixel group, the first gate line and the fourth gate line are respectively and electrically connected with the sub-pixels of the same row, the second gate line and the third gate line are respectively and electrically connected with the sub-pixels in the same row, and the sub-pixels electrically connected with the fourth gate line of the first pixel group and the first gate line of the second pixel group are positioned in the same row. The driving circuit transmits a data signal to drive a plurality of pixels through a plurality of data lines; in one frame time, the polarities of two adjacent sub-pixels of the same pixel driven by a data signal through an nth data line or an n +1 th data line are opposite, the polarities of the same pixel driven by the data signal through the nth data line and the n +1 th data line are opposite, the polarities of two adjacent sub-pixels in the column direction of the same pixel group driven by the data signal through the nth data line and the n +1 th data line are the same, one of the two adjacent pixels in the column direction is a bright area, the other pixel is a dark area, and the positive and negative polarity ratios of the bright area sub-pixels of the same color arranged in the column direction are 1: 1.

in view of the above, the display device of the present application provides a new pixel driving arrangement, and under the connection structure of the multi-color sub-pixels and the half-source driving technology, the positive-negative polarity ratio of the bright-area sub-pixels of the same color arranged along the column direction (vertical direction) within one frame time is 1: 1, the vertical crosstalk problem of the display panel caused by parasitic capacitance coupling is mutually counteracted by the positive polarity and the negative polarity, so that the display picture is more uniform, and the picture quality is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

fig. 1 is a functional block diagram of a display device according to an embodiment of the present application.

Fig. 2A and 2B are schematic diagrams illustrating connection between a pixel and a gate line and a data line of a display panel according to an embodiment of the present disclosure.

Fig. 3 is a schematic waveform diagram of a gate line corresponding to a data signal in a frame time in the connection structure of the sub-pixel and the gate line and the data line in fig. 2B.

Fig. 4A to 4D are schematic diagrams illustrating a manufacturing process of four color filter layers of a display device according to an embodiment.

Detailed Description

Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present application. This application may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, it is to be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and therefore should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Display devices according to some embodiments of the present application will be described with reference to the accompanying drawings, in which like elements are described with like reference numerals.

Fig. 1 is a functional block diagram of a display device 1 according to an embodiment of the present application. As shown in fig. 1, the display device 1 of the present embodiment is a liquid crystal display device, and may include a display panel 11 and a driving circuit 12. The display panel 11 includes a plurality of pixels (pixels) arranged along a row direction and a column direction, a plurality of gate lines (G1, G2, …), and a plurality of data lines (also called source lines, D1, D2, D3, …), the plurality of gate lines and the plurality of data lines are disposed alternately and electrically connected to the plurality of pixels, and each pixel may include Sub-pixels (Sub-pixels) of a plurality of colors arranged along the row direction.

The driving circuit 12 is electrically connected to the display panel 11 and can drive a plurality of pixels of the display panel 11 to display images. The driving circuit 12 of the present embodiment may include a scan driving unit 121, a data driving unit 122, and a timing control unit 123. The scan driving unit 121 may be coupled to the display panel 11 through the gate lines, and the data driving unit 122 may be coupled to the display panel 11 through the data lines. The scan driving unit 121 may output scan signals to turn on the gate lines, and the data driving unit 122 may output data signals corresponding to the data lines to drive the corresponding pixels. In addition, the display device 1 may further include a timing control unit 123, and the timing control unit 123 may transmit a vertical synchronization signal and a horizontal synchronization signal to the scan driving unit 121, convert a video signal received from an external interface into a data signal for the data driving unit 122, and transmit the data signal and the horizontal synchronization signal to the data driving unit 122. In a frame time (frame time), when the gate lines are sequentially turned on by the scan signals, the data driving unit 122 transmits the data signals corresponding to each row of sub-pixels to the sub-pixels through the data lines, so that the display panel 11 displays an image.

Fig. 2A and fig. 2B are schematic diagrams illustrating connection between pixels and gate lines and connection between data lines of a display panel according to an embodiment of the invention. Fig. 2A and 2B show the same connection structure, however, fig. 2B also shows the bright and dark conditions of the sub-pixels of each pixel (the sub-pixels shown by the dotted lines are dark regions). In fig. 2A and 2B, 8 gate lines G1-G8, 4 data lines D1-D4 and 4 rows (horizontal) of 8 pixels (32 sub-pixels P) are shown as an example, but not limited thereto, and in different embodiments, more gate lines, data lines and pixel numbers can be designed according to actual requirements.

In fig. 2A, 8 gate lines G1-G8 can be divided into 4 groups of gate lines (enclosed by dotted lines), each group has two gate lines (G1, G2), (G3, G4), … (G7, G8), and the 4 data lines are respectively represented by D1-D4, and the display panel 11 has a plurality of pixels arranged along a row direction (horizontal direction) and a column direction (vertical direction), wherein each pixel has a plurality of sub-pixels P arranged along the row direction, and the plurality of sub-pixels P arranged along the row direction are respectively electrically connected to two adjacent gate lines (gate line groups) of a corresponding row, and each data line is respectively electrically connected to two adjacent sub-pixels P of the same pixel. Specifically, for example, the gate lines (G1, G2) can simultaneously drive two pixels in the first row (each pixel includes 4 sub-pixels P of white (W), red (R), green (G) and blue (B)), the gate lines (G3, G4) can simultaneously drive two pixels in the second row, and the data lines D1, D2, D3, D4 are respectively electrically connected to two adjacent sub-pixels P of the same pixel, i.e., each pixel is also electrically connected to two data lines, and so on. As shown in fig. 2A, each data line connects two adjacent sub-pixels P in the same pixel, so that the display device 1 of the embodiment adopts the Half Source Driving (HSD) technology, which not only reduces the number of source driver ICs, but also facilitates the improvement of the production capacity.

Each pixel of the present embodiment includes four color (WRGB) sub-pixels P arranged along the row direction, and the color arrangement sequence of the multi-color sub-pixels P of each pixel is the same, and the colors of the sub-pixels P in the same row are the same. In addition, in two adjacent data lines connecting the same pixel: in the nth data line and the (n +1) th data line, D (n) and D (n +1) represent (n is an odd number), the color of the sub-pixel P connected with the data line D (n) is wrrwwr from top to bottom, and the sequence is repeated; the colors of the sub-pixels P connected to the data line D (n +1) are GBGBGBBGGB from top to bottom in sequence, and the sequence is repeated.

In addition, two adjacent pixels arranged in the column direction may form a pixel group T (enclosed by a dotted line), respectively. Taking the pixel group at the upper left corner (labeled as T1) as an example, the sub-pixels P of the upper half of the pixels have a straight Stripe (Stripe) arrangement of WRGB sequentially, and the sub-pixels P of the lower half of the pixels have the same arrangement of WRGB sequentially as the upper half. In the pixel group T1, the upper four sub-pixels P are electrically connected to the gate lines G1 and G2 of the same group in the corresponding row and the two adjacent data lines D1 and D2 in the corresponding column, respectively, and the lower four sub-pixels P are electrically connected to the gate lines G3 and G4 of the same group in the corresponding row and the two adjacent data lines D1 and D2 in the corresponding column, respectively. The color of each pixel is WRGB, but not limited to WRGB, and may be different four colors, such as RGBY, RGBC, or others, in different embodiments.

The two adjacent pixel groups arranged along the row direction may be a first pixel group T1 and a second pixel group T2, and the first pixel group T1 and the second pixel group T2 are respectively connected to a first gate line, a second gate line, a third gate line and a fourth gate line in sequence. In other words, in the present embodiment, as shown in fig. 2A, the first pixel group T1 sequentially connects the first gate line (G1), the second gate line (G2), the third gate line (G3) and the fourth gate line (G4), and the second pixel group T2 also sequentially connects the first gate line (G5), the second gate line (G6), the third gate line (G7) and the fourth gate line (G8). In the first pixel group T1, the first gate line (G1) and the third gate line (G3) are electrically connected to the subpixels P in the same row, respectively, and the second gate line (G2) and the fourth gate line (G4) are electrically connected to the subpixels P in the same row, respectively. In the second pixel group T2, the first gate line (G5) and the fourth gate line (G8) are electrically connected to the sub-pixels P in the same column, the second gate line (G6) and the third gate line (G7) are electrically connected to the sub-pixels P in the same column, and the sub-pixels P electrically connected to the fourth gate line (G4) of the first pixel group T1 and the first gate line (G5) of the second pixel group T2 are located in the same column and electrically connected to the same data line (D1).

In the present embodiment, the first gate line (G1) of the first pixel group T1 is electrically connected to the odd-numbered sub-pixels P of the first row of pixels, the second gate line (G2) is electrically connected to the even-numbered sub-pixels P of the first row of pixels, the third gate line (G3) is electrically connected to the odd-numbered sub-pixels P of the second row of pixels, and the fourth gate line (G4) is electrically connected to the even-numbered sub-pixels P of the second row of pixels; in the second pixel group T2, the first gate lines (G5) are electrically connected to the even sub-pixels P of the third row of pixels, the second gate lines (G6) are electrically connected to the odd sub-pixels P of the third row of pixels, the third gate lines (G7) are electrically connected to the odd sub-pixels P of the fourth row of pixels, and the fourth gate lines (G8) are electrically connected to the even sub-pixels P of the fourth row of pixels, and so on. However, the present application is not limited thereto, and in different embodiments, the first gate line (G1) of the first pixel group T1 may be respectively electrically connected to the even sub-pixels P of the first row of pixels, the second gate line (G2) may be respectively electrically connected to the odd sub-pixels P of the first row of pixels (the odd number and the even number are counted from left to right), the third gate line (G3) may be respectively electrically connected to the even sub-pixels P of the second row of pixels, and the fourth gate line (G4) may be respectively electrically connected to the odd sub-pixels P of the second row of pixels; the first gate lines (G5) of the second pixel group T2 may be respectively electrically connected to the odd sub-pixels P of the third row of pixels, the second gate lines (G6) may be respectively electrically connected to the even sub-pixels P of the third row of pixels, the third gate lines (G7) may be respectively electrically connected to the even sub-pixels P of the fourth row of pixels, and the fourth gate lines (G8) may be respectively electrically connected to the odd sub-pixels P of the fourth row of pixels.

In addition, each pixel may include a first sub-pixel P, a second sub-pixel P, a third sub-pixel P and a fourth sub-pixel P, where the first sub-pixel P and the second sub-pixel P in each pixel are electrically connected to one of the nth data line and the (n +1) th data line, and the third sub-pixel P and the fourth sub-pixel P are electrically connected to the other of the nth data line and the (n +1) th data line (the first to fourth are also counted from left to right). In the present embodiment, taking the data lines D1(D3) and D2(D4) as an example, the data line D1(D3) is electrically connected to the first sub-pixel P and the second sub-pixel P of each pixel in the vertical direction, the data line D2(D4) is electrically connected to the third sub-pixel P and the fourth sub-pixel P of each pixel in the vertical direction, and so on.

Referring to fig. 2A and 2B in conjunction with fig. 3, wherein fig. 3 is a waveform diagram of a gate line corresponding to a data signal transmitted by a data line within a frame time in the connection structure of the sub-pixel and the gate line and the data line of fig. 2B. In the driving of the display device of the present embodiment, under the above-mentioned connection structure, the driving circuit 12 transmits data signals through the plurality of data lines to drive the plurality of pixels of the display panel 11, wherein, in one frame time, the polarities of the data signals driving the two adjacent sub-pixels P of the same pixel through the nth data line or the (n +1) th data line are opposite, the polarities of the data signals driving the same pixel through the nth data line and the (n +1) th data line are opposite (that is, at the same time, if the nth data line is positive, the (n +1) th data line is negative, or opposite), and the polarities of the data signals driving the two adjacent sub-pixels P of the same pixel group in the column direction through the nth data line and the (n +1) th data line are the same.

In the present embodiment, as shown in fig. 2A, the two adjacent sub-pixels P of the same pixel driven by the data signal through the nth data line or the (n +1) th data line respectively include two polarities (positive polarity and negative polarity), and in one frame time, the polarity sequence of the sub-pixel P driven by the data signal through the nth data line is negative, positive, and negative in the column direction, the polarity sequence of the sub-pixel P driven by the data signal through the (n +1) th data line is positive, negative, and positive in the column direction, and in the same frame time, the polarity sequence of the sub-pixel P driven by the nth data line and the (n +1) th data line respectively repeats the sequence of negative, positive, negative, positive, and negative in the column direction, and the (n +1) th data line repeats the sequence of positive, negative, positive, and negative, positive, negative, positive, and negative, positive, negative, negative, positive, negative, positive. In one frame time, the polarities of two adjacent sub-pixels P of the same pixel driven by the data signal through the nth data line or the (n +1) th data line are opposite, the polarities of the same pixel driven by the data signal through the nth data line and the (n +1) th data line are opposite, and the polarities of two adjacent sub-pixels P in the column direction of the same pixel group driven by the data signal through the nth data line and the (n +1) th data line are the same. The sub-pixels P of the plurality of colors for driving each pixel by the data signal comprise two voltage polarities. In addition, the polarities of two adjacent sub-pixels P of the same pixel connected to the nth data line and the (n +1) th data line are the same, and the polarities of two adjacent sub-pixels P in the column direction of the first pixel group T1 and the second pixel group T2 driven by the data signal through the nth data line or the (n +1) th data line are opposite.

In addition, at the next frame time, the driving polarity of the data signal is in a polarity inversion driving mode, so that the characteristics of the liquid crystal molecules are not damaged. In other words, in the present embodiment, at the next frame time, the polarity sequence of the sub-pixels P driven by the data signals through the nth data line and the (n +1) th data line is positive, negative, positive and negative, positive, negative, positive, and negative in the column direction, respectively, and the polarity sequence of the sub-pixels P driven by the nth data line and the (n +1) th data line repeats positive, negative, positive and negative, positive, negative, positive, and negative in the column direction during the next frame time, respectively.

Through the above-mentioned connection structure and driving method of the gate lines, the data lines and the sub-pixels P, as shown in fig. 2B, the driving circuit 12 can make the voltage polarities of the sub-pixels P of the plurality of colors of the two pixels in the first pixel group T1 within one frame time be respectively negative, positive, and negative (++ -), and in the second pixel group T2, the voltage polarities of the sub-pixels P of the plurality of colors of the two pixels are respectively positive, negative, and positive (+ - +); alternatively, the polarities of the voltages of the multi-color sub-pixels P of the two pixels in the first pixel group T1 may be positive, negative, and positive (— +), respectively, and the polarities of the voltages of the multi-color sub-pixels P of the two pixels in the second pixel group T2 may be negative, positive, and negative (++ -) respectively. In addition, the polarities of the voltages presented by the sub-pixels P of each pixel in the same row are the same, and the polarities of the voltages presented by two sub-pixels P adjacent to each other in the column direction are opposite in different pixel groups. At the next frame time, the presented voltage polarity of all the sub-pixels P is then opposite to that at the previous frame time.

In addition, in one frame time, the driving circuit 12 makes one of two pixels adjacent to each other in the column direction a bright area and makes the other pixel a dark area. As shown in fig. 2B, in the present embodiment, one of the two pixels adjacent to each other in the column direction is a bright area, and the other is a dark area, and in each pixel group T, one pixel is also a dark area, and the other is a bright area. That is, the display panel of the present embodiment uses four color sub-pixels with a dual pixel rendering (subwpaixel rendering) technique.

Therefore, as shown in fig. 3, under the above connection structure, the positive-negative polarity ratio of the bright sub-pixels P of the same color arranged along the column direction is 1: 1. for example, for the data line D1, the number of positive polarities and the number of negative polarities of the white (W) sub-pixel P are both 1; the number of positive polarities and the number of negative polarities of the red (R) subpixel P are both 1. For the data line D2, the positive polarity number and the negative polarity number of the green (G) sub-pixel P are both 1; the number of positive polarities and the number of negative polarities of the blue (B) subpixel P are both 1. The other data lines D3 and D4 can be referred to fig. 3 for their corresponding positive and negative polarity numbers, which are not further described.

In summary, in the display device of the present embodiment, a new pixel driving arrangement is proposed, and under the connection structure of the four color sub-pixels and the half-source driving technology, the positive-negative polarity ratio of the bright-area sub-pixels P of the same color arranged along the column direction (vertical direction) within one frame time is 1: 1, the vertical crosstalk problem of the display panel caused by parasitic capacitance coupling is mutually counteracted by the positive polarity and the negative polarity, so that the display picture is more uniform, and the picture quality is improved.

Fig. 4A to 4D are schematic diagrams illustrating steps of manufacturing four color filter layers of a display device according to an embodiment.

As shown in fig. 4A, the first manufacturing process of the four color filter layers of the display device of this embodiment is: forming a black matrix layer 112 on a substrate 111 at an interval, and forming a filter layer (e.g. R) of a first color on the substrate 111 and the black matrix layer 112, for example, by coating; next, as shown in fig. 4B, the second step is: using a mask 2 to perform an exposure process, wherein the opening 21 of the mask 2 corresponds to the position of the first color sub-pixel; next, as shown in fig. 4C, the third step is: performing a developing process to define the position of the first color (R) filter layer on the substrate 111; thereafter, the first, second and third steps are repeated to define the position of the four-color (R, G, B, W) filter layer on the substrate 111, thereby obtaining the arrangement of the sub-pixels P of the four colors, wherein the black matrix layer 112 can be respectively disposed around the four-color filter layers.

In summary, the display device of the present application provides a new pixel driving arrangement, and under the connection structure of the multi-color sub-pixels and the half-source driving technology, the positive-negative polarity ratio of the bright-area sub-pixels of the same color arranged along the column direction (vertical direction) within one frame time is 1: 1, the vertical crosstalk problem of the display panel caused by parasitic capacitance coupling is mutually counteracted by the positive polarity and the negative polarity, so that the display picture is more uniform, and the picture quality is improved.

The foregoing is by way of example only, and not limiting. Any equivalent modifications or variations without departing from the spirit and scope of the present application should be included in the scope of the claims.

Claims

1. A display device, comprising a display panel, the display panel comprising:

a plurality of gate lines;

the data lines are arranged in a staggered manner with the gate lines, each data line comprises an nth data line and an n +1 th data line, and n is an odd number;

a plurality of pixels arranged along a row direction and a column direction, each of the pixels including sub-pixels of a plurality of colors arranged along the row direction, the plurality of sub-pixels arranged along the row direction being electrically connected to two adjacent gate lines of a corresponding row, respectively, each of the data lines being electrically connected to two adjacent sub-pixels of a same pixel, two adjacent pixels arranged along the column direction forming a pixel group, respectively, the two adjacent pixel groups arranged along the column direction being a first pixel group and a second pixel group, the first pixel group and the second pixel group being sequentially connected to a first gate line, a second gate line, a third gate line and a fourth gate line, respectively, in the first pixel group, the first gate line and the third gate line being electrically connected to the sub-pixels of a same column, respectively, the second gate line and the fourth gate line being electrically connected to the sub-pixels of a same column, respectively, in the second pixel group, the first gate line and the fourth gate line are electrically connected to the sub-pixels in the same row respectively, the second gate line and the third gate line are electrically connected to the sub-pixels in the same row respectively, and the fourth gate line of the first pixel group and the sub-pixels electrically connected to the first gate line of the second pixel group are located in the same row respectively; and

a driving circuit for transmitting a data signal through the data lines to drive the pixels;

in one frame time, the polarities of two adjacent sub-pixels of the same pixel driven by the data signal through the nth data line or the (n +1) th data line are opposite, the polarities of the same pixel driven by the data signal through the nth data line and the (n +1) th data line are opposite, and the polarities of two adjacent sub-pixels in the column direction of the same pixel group driven by the data signal through the nth data line and the (n +1) th data line are the same.

2. The display device according to claim 1, wherein the color arrangement order of the sub-pixels of the plurality of colors of each of the pixels is the same.

3. The display device according to claim 1, wherein the nth data line and the (n +1) th data line are connected to the same pixel.

4. The display device according to claim 1, wherein the polarities of the data signals driving the two sub-pixels of the first pixel group adjacent to the second pixel group in the column direction through the nth data line or the n +1 th data line are opposite.

5. The display device according to claim 1, wherein two adjacent sub-pixels of the same pixel connected to the nth data line and the (n +1) th data line have the same polarity.

6. The display device according to claim 1, wherein the polarities of the voltages applied to the sub-pixels of the plurality of colors in each of the pixels in the same row are in the same order.

7. The display device according to claim 1, wherein each of the pixels includes four color sub-pixels arranged in a row direction.

8. The display device according to claim 1, wherein the colors of the sub-pixels connected to the nth data line are sequentially wrwrwrwrrwwr and repeated, and the colors of the sub-pixels connected to the (n +1) th data line are sequentially GBGBBGGB and repeated, where W is white, R is red, G is green, and B is blue.

9. The display device according to claim 1, wherein the driving circuit makes one of two pixels adjacent to each other in a column direction a bright area and the other pixel a dark area within one frame time, and bright area sub-pixels of the same color arranged in the column direction have a positive-negative polarity ratio of 1: 1.

10. a display device, comprising a display panel, the display panel comprising:

a plurality of gate lines;

a plurality of pixels arranged along a row direction and a column direction, each of the pixels including sub-pixels of multiple colors arranged along the row direction, the sub-pixels of four colors of each of the pixels being arranged in the same color sequence, the sub-pixels arranged along the row direction being electrically connected to two adjacent gate lines of a corresponding row, each of the data lines being electrically connected to two adjacent sub-pixels of the same pixel, two adjacent pixels arranged along the column direction forming a pixel group, the two adjacent pixel groups arranged along the column direction being a first pixel group and a second pixel group, the first pixel group and the second pixel group being connected to a first gate line, a second gate line, a third gate line and a fourth gate line, respectively, the first gate line and the third gate line in the first pixel group being electrically connected to the sub-pixels of the same column, the second gate line and the fourth gate line are electrically connected to the sub-pixels in the same row respectively, in the second pixel group, the first gate line and the fourth gate line are electrically connected to the sub-pixels in the same row respectively, the second gate line and the third gate line are electrically connected to the sub-pixels in the same row respectively, and the fourth gate line of the first pixel group and the sub-pixels electrically connected to the first gate line of the second pixel group are in the same row respectively; and

in one frame time, the data signals drive two adjacent sub-pixels of the same pixel through the nth data line or the (n +1) th data line to have opposite polarities, the data signals drive two adjacent sub-pixels of the same pixel group through the nth data line and the (n +1) th data line to have the same polarity, the drive circuit drives two adjacent sub-pixels of the same pixel group in the column direction to have the same polarity through the nth data line and the (n +1) th data line, one of the two adjacent pixels in the column direction is a bright area, the other pixel is a dark area, and the proportion of positive and negative polarities presented by the bright area sub-pixels of the same color arranged in the column direction is 1: 1.