CN107359863B - Integrated amplifier - Google Patents
Integrated amplifier Download PDFInfo
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- CN107359863B CN107359863B CN201710587239.7A CN201710587239A CN107359863B CN 107359863 B CN107359863 B CN 107359863B CN 201710587239 A CN201710587239 A CN 201710587239A CN 107359863 B CN107359863 B CN 107359863B
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- 239000003990 capacitor Substances 0.000 claims abstract description 142
- 230000005669 field effect Effects 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 230000003068 static effect Effects 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000002829 reductive effect Effects 0.000 abstract description 3
- 230000000903 blocking effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000002238 attenuated effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910021124 PdAg Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010344 co-firing Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000009423 ventilation Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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Abstract
The invention relates to the technical field of semiconductor microwave devices and provides an integrated amplifier. The device comprises a circuit substrate, a metal shell fixedly connected with the circuit substrate, and a field effect tube and a circuit matching network which are arranged on the circuit substrate; the field effect transistor comprises a first field effect transistor and a second field effect transistor; the circuit matching network comprises an input matching network, a first feedback bias network, an inter-stage matching network, a second feedback bias network and an output matching network. The integrated amplifier provided by the invention has the advantages that the designed circuit of the integrated amplifier is packaged through the circuit substrate and the metal shell to form the integrally packaged hybrid integrated low-noise amplifier, so that a large-value capacitor, an inductance element, a bare chip and the like in the circuit are arranged in an airtight space inside the package, the external interference is reduced, and the purposes of high concentration, miniaturization and light weight are realized.
Description
Technical Field
The invention belongs to the technical field of semiconductor microwave devices, and particularly relates to an integrated amplifier.
Background
With the development of Microwave technology, Microwave Monolithic Integrated Circuits (MMICs) are widely used. MMIC is a semiconductor process method used to fabricate passive and active devices on a semiconductor substrate and connect them to form various functional circuits for microwave frequency band applications. In order to ensure the long-term reliability of an integrated circuit chip, a suitable housing is usually selected to hermetically encapsulate the integrated circuit chip, thereby isolating the bare chip from the harsh external environment and protecting the chip from or less from the environment.
In the design of the low noise amplifier, some large value of capacitance and inductance are sometimes needed for matching, especially in the lower frequency band of microwave. At present, the devices such as capacitors and inductors with large values cannot be integrated on a chip, and the devices can only be connected outside the chip, so that the size of an integrated circuit is large and the application is inconvenient.
Disclosure of Invention
The invention aims to provide an integrated amplifier, aiming at solving the problems that the large-value capacitor and inductor in the existing microwave monolithic integrated circuit can only be connected off chip, so that the size of the integrated circuit is large and the application is inconvenient.
In order to achieve the purpose, the invention adopts the technical scheme that: providing an integrated amplifier, which comprises a circuit substrate, a metal shell fixedly connected with the circuit substrate, and a field effect transistor and a circuit matching network which are arranged on the circuit substrate;
the field effect transistor comprises a first field effect transistor and a second field effect transistor; the circuit matching network comprises an input matching network, a first feedback bias network, an interstage matching network, a second feedback bias network and an output matching network;
the input end of the first field effect transistor is respectively connected with the output end of the input matching network and the first end of the first feedback bias network; the output end of the first field effect transistor is respectively connected with the second end of the first feedback bias network and the input end of the interstage matching network; the input end of the second field effect transistor is respectively connected with the output end of the interstage matching network and the first end of the second feedback bias network; the output end of the second field effect transistor is respectively connected with the second end of the second feedback bias network and the input end of the output matching network;
the input matching network is used for carrying out impedance matching and noise matching on the input end of the first field effect transistor; the first field effect tube and the second field effect tube are used for amplifying radio frequency signals; the first feedback bias network is used for providing a static bias working point for the first field effect transistor and forming parallel negative feedback between the input end and the output end of the first field effect transistor; the interstage matching network is used for carrying out impedance matching between the first field effect transistor and the second field effect transistor; the second feedback bias network is used for providing a static bias working point for the second field effect transistor and forming parallel negative feedback at the input end and the output end of the second field effect transistor; and the output end of the output matching network is used for outputting the amplified radio frequency signal.
Further, the input matching network comprises a capacitor C1, an inductor L1, a resistor R1, and a capacitor C2; a first end of the inductor L1 is connected to a second end of the capacitor C1, and a second end of the inductor L1 is connected to a first end of the resistor R1 and a first end of the capacitor C2, respectively; a second terminal of the resistor R1 and a second terminal of the capacitor C2 are both grounded; the first end of the capacitor C1 is the input end of the input matching network; the second terminal of the capacitor C1 is the output terminal of the input matching network.
Further, the first feedback bias network comprises a resistor R4, the resistor R1, a resistor R7, a resistor R9, and a resistor R6; the interstage matching network comprises the resistor R7, a resistor R8, the resistor R9, a capacitor C8, a capacitor C9, an inductor L2, a capacitor C4, a capacitor C3 and a resistor R2; a first end of the resistor R4 is connected with an input end of the first field effect transistor, and a second end of the resistor R4 is respectively connected with an output end of the first field effect transistor, a first end of the capacitor C8 and a first end of the resistor R7; a second end of the capacitor C8 is connected to a second end of the resistor R8 and a first end of the capacitor C3, respectively; a second end of the resistor R7 is respectively connected with a first end of the resistor R8 and a first end of the resistor R9; a first end of the resistor R9 is connected to a first end of the capacitor C9 and a first end of the inductor L2, respectively; a second end of the inductor L2 is connected to a first end of the capacitor C4 and a first end of the resistor R6, respectively; a second terminal of the capacitor C9 and a second terminal of the capacitor C4 are both grounded; a second end of the resistor R6 is respectively connected with a power supply voltage Vd and a first end of the capacitor C7; the second end of the capacitor C7 is grounded; the second end of the capacitor C3 is connected with the first end of the resistor R2; the second end of the resistor R2 is grounded; the second terminal of the capacitor C3 is the output terminal of the interstage matching network.
Further, the second feedback bias network comprises a resistor R3, the resistor R2, a resistor R12, a resistor R10, and a resistor R5; the output matching network comprises the resistor R10, a resistor R11, the resistor R12, a capacitor C10, a capacitor C11, an inductor L3, a capacitor C6 and a capacitor C5; a first end of the resistor R3 is connected to an input end of the second fet, and a second end of the resistor R3 is connected to an output end of the second fet, a first end of the capacitor C10, and a first end of the resistor R12, respectively; a second end of the capacitor C10 is connected to a second end of the resistor R11 and a first end of the capacitor C5, respectively; a second end of the resistor R12 is respectively connected with a first end of the resistor R11 and a first end of the resistor R10; a second end of the resistor R10 is connected to a first end of the capacitor C11 and a first end of the inductor L3, respectively; a second end of the inductor L3 is connected to a first end of the capacitor C6 and a first end of the resistor R5, respectively; a second terminal of the capacitor C11 and a second terminal of the capacitor C6 are both grounded; a second end of the resistor R5 is respectively connected with the power supply voltage Vd and a first end of the capacitor C7; the second end of the capacitor C7 is grounded; the second end of the capacitor C5 is the output end of the output matching network, and is used for outputting the amplified radio frequency signal.
Further, the wire bonder comprises wire bonders W1, wire bonders W2, wire bonders W3, wire bonders W4, wire bonders W5, wire bonders W6, wire bonders W7 and wire bonders W8; a first end of the bonding wire W1 is connected with a second end of the capacitor C1, and a second end of the bonding wire W1 is connected with a grid electrode of the first field effect transistor; a first end of the bonding wire W2 and a first end of the bonding wire W3 are both connected with the source electrode of the first field effect transistor, and a second end of the bonding wire W2 and a second end of the bonding wire W3 are both grounded; a first end of the bonding wire W4 is connected with the drain electrode of the first field effect transistor, and a second end of the bonding wire W4 is connected with a first end of the resistor R7; a first end of the bonding wire W5 is connected with a second end of the capacitor C3, and a second end of the bonding wire W5 is connected with a grid electrode of the second field effect transistor; a first end of the bonding wire W6 is connected with the drain electrode of the second field effect transistor, and a second end of the bonding wire W6 is connected with a first end of the resistor R12; a first end of the bonding wire W7 and a first end of the bonding wire W8 are both connected with the source of the second fet, and a second end of the bonding wire W7 and a second end of the bonding wire W8 are both grounded.
Further, the length of the bonding wire ranges from 0.2mm to 1 mm.
Further, the circuit substrate is an LTCC substrate.
Furthermore, the metal shell comprises a metal surrounding frame and a metal cover plate, and the metal surrounding frame is fixedly connected with the circuit substrate and the metal cover plate respectively.
Furthermore, the circuit substrate is multilayer, and projections of any two through holes on the circuit substrate on a parallel plane of the circuit substrate do not contain the same area.
Further, the resistors in the circuit matching network comprise film resistors printed on the circuit substrate in a silk-screen manner.
The integrated amplifier provided by the embodiment of the invention has the beneficial effects that: the design circuit of the integrated amplifier is packaged through the circuit substrate and the metal shell to form the integrally packaged hybrid integrated low-noise amplifier, so that a large-value capacitor, an inductance element, a bare chip and the like in the circuit are arranged in an airtight space inside the package, the interference of the outside is reduced, and the purposes of high concentration, miniaturization and light weight are achieved.
Drawings
Fig. 1 is a block diagram of a circuit in an integrated amplifier according to an embodiment of the present invention;
FIG. 2 is a device connection diagram of a circuit in an integrated amplifier according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a relationship between inductance of a bonding wire and a source and circuit stability in an integrated amplifier according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a circuit substrate and a metal housing in an integrated amplifier according to an embodiment of the invention.
In the figure: 100. a first field effect transistor; 200. a second field effect transistor; 300. inputting a matching network; 400. a first feedback bias network; 500. an interstage matching network; 600. a second feedback bias network; 700. an output matching network; 800. a circuit substrate; 900. a metal housing; 901. a metal cover plate; 902. and (4) a metal enclosure frame.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, an integrated amplifier according to an embodiment of the present invention will now be described. An integrated amplifier comprises a circuit substrate 800, a metal shell 900 fixedly connected with the circuit substrate 800, and a field effect transistor and a circuit matching network which are arranged on the circuit substrate 800.
The fets include a first fet 100 and a second fet 200. The circuit matching network includes an input matching network 300, a first feedback bias network 400, an inter-stage matching network 500, a second feedback bias network 600, and an output matching network 700.
The input terminals of the first fet 100 are respectively connected to the output terminal of the input matching network 300 and the first terminal of the first feedback bias network 400, and the output terminal of the first fet 100 is respectively connected to the second terminal of the first feedback bias network 400 and the input terminal of the inter-stage matching network 500. The input terminal of the second fet 200 is connected to the output terminal of the inter-stage matching network 500 and the first terminal of the second feedback bias network 600, respectively, and the output terminal of the second fet 200 is connected to the second terminal of the second feedback bias network 600 and the input terminal of the output matching network 700, respectively.
The input matching network 300 is used for impedance matching and noise matching of the input terminal of the first fet 100. The first fet 100 and the second fet 200 are used to amplify a radio frequency signal. The first feedback bias network 400 is used to provide a static bias operating point for the first fet 100 and to form a parallel negative feedback between the input and output of the first fet 100. The interstage matching network 500 is used for impedance matching between the first field effect transistor 100 and the second field effect transistor 200. The second feedback bias network 600 is used to provide a static bias operating point for the second fet 200, and form a parallel negative feedback at the input and output of the second fet 200. The output end of the output matching network 700 is used for outputting the amplified radio frequency signal.
The integrated amplifier provided by the embodiment of the invention has the beneficial effects that: the designed circuit of the integrated amplifier is packaged through the circuit substrate 800 and the metal shell 900 to form an integrally packaged hybrid integrated low-noise amplifier, so that a large-value capacitor, an inductance element, a bare chip and the like in the circuit are arranged in an airtight space inside the package, the external interference is reduced, and the purposes of high concentration, miniaturization and light weight are achieved.
In this embodiment, the first fet 100 and the second fet 200 may be enhancement mode fets. The circuit substrate 800 may include back side metallization pads, front side traces and pads, buried layer traces, interlayer transition holes. The rf signal enters through the input matching network 300, is amplified by the two stages of field tubes, and is finally output through the output matching network 700. The first fet 100 is a front stage fet and the second fet 200 is a rear stage fet. The input matching network 300 allows the input of the front stage field tube to achieve 50 ohm impedance and optimum noise matching. Interstage matching network 500 is used to improve impedance matching between the front and rear stage field tubes. The output matching network 700 enables the output end of the back-stage field tube to achieve good matching of 50 ohm impedance, and optimal power output is achieved. The feedback bias network provides a static bias working point for the field tube on one hand, and enables the output end and the input end of the field tube to form a parallel negative feedback effect on the other hand, so that the amplitude-frequency characteristic of a signal is improved.
Optionally, the input matching network 300 is composed of a dc blocking capacitor and an RLC network. The interstage matching network 500 consists of two RLC networks and a dc blocking capacitor. The output matching network 700 is composed of a dc blocking capacitor and an RLC network. The feedback biasing network may include a feedback network and a biasing network. The feedback network consists of parallel resistors, and the bias network consists of series-connected voltage dividing resistors.
Further, referring to fig. 2, as an embodiment of the integrated amplifier provided by the present invention, the input matching network 300 includes a capacitor C1, an inductor L1, a resistor R1, and a capacitor C2. A first terminal of the inductor L1 is connected to a second terminal of the capacitor C1, and a second terminal of the inductor L1 is connected to a first terminal of the resistor R1 and a first terminal of the capacitor C2, respectively. The second end of the resistor R1 and the second end of the capacitor C2 are both grounded. The first terminal of the capacitor C1 is the input terminal of the input matching network 300. The second terminal of the capacitor C1 is the output terminal of the input matching network 300. Wherein the capacitor C1 is a dc blocking capacitor at the input terminal.
Further, referring to fig. 2, as an embodiment of the integrated amplifier provided by the present invention, the first feedback bias network 400 includes a resistor R4, the resistor R1, a resistor R7, a resistor R9, and a resistor R6. The interstage matching network 500 comprises the resistor R7, a resistor R8, the resistor R9, a capacitor C8, a capacitor C9, an inductor L2, a capacitor C4, a capacitor C3, and a resistor R2. A first end of the resistor R4 is connected to the input terminal of the first fet 100, and a second end of the resistor R4 is connected to the output terminal of the first fet 100, the first end of the capacitor C8, and the first end of the resistor R7, respectively. The second end of the capacitor C8 is connected to the second end of the resistor R8 and the first end of the capacitor C3, respectively. The second end of the resistor R7 is connected to the first end of the resistor R8 and the first end of the resistor R9, respectively. A first terminal of the resistor R9 is connected to a first terminal of the capacitor C9 and a first terminal of the inductor L2, respectively. A second terminal of the inductor L2 is connected to a first terminal of the capacitor C4 and a first terminal of the resistor R6, respectively. The second terminal of the capacitor C9 and the second terminal of the capacitor C4 are both grounded. The second end of the resistor R6 is connected to the power supply voltage Vd and the first end of the capacitor C7, respectively. The second terminal of the capacitor C7 is connected to ground. The second end of the capacitor C3 is connected to the first end of the resistor R2. The second end of the resistor R2 is grounded; the second terminal of the capacitor C3 is the output terminal of the interstage matching network 500.
The resistor R4 is a feedback resistor of the foreline field tube, and the resistor R4, the resistor R1, the resistor R7, the resistor R9 and the resistor R6 form a series voltage division bias network of the foreline field tube. The resistor R7, the resistor R8, the resistor R9, the capacitor C8, the capacitor C9, the inductor L2, the capacitor C4, the capacitor C3 and the resistor R2 form an interstage matching network 500, and the interstage matching network is used for impedance matching between the rear stage field tube and the front stage field tube. The capacitor C3 is an inter-stage blocking capacitor; the resistor R7, the resistor R8, the resistor R9, the capacitor C8, the capacitor C9, the inductor L2 and the capacitor C4 form an interstage amplitude equalization network. When the frequency of the radio frequency signal is low, the signal passes through a T-shaped attenuation network formed by a resistor R7, a resistor R8 and a resistor R9, and partial energy can be attenuated; while when the frequency of the rf signal is higher, the signal passes better through the C8 capacitor and less energy is attenuated. Therefore, the gain roll-off of the field tube along with the increase of the frequency can be compensated, and the flatness can be improved.
In this embodiment, the bias network portion may be composed of both the resistance of the input/inter-stage matching network and the resistance of the feedback network, thereby reducing the components and achieving further miniaturization.
Further, referring to fig. 2, as an embodiment of the integrated amplifier provided by the present invention, the second feedback bias network 600 includes a resistor R3, the resistor R2, a resistor R12, a resistor R10, and a resistor R5. The output matching network 700 includes the resistor R10, the resistor R11, the resistor R12, the capacitor C10, the capacitor C11, the inductor L3, the capacitor C6, and the capacitor C5. A first end of the resistor R3 is connected to the input terminal of the second fet 200, and a second end of the resistor R3 is connected to the output terminal of the second fet 200, the first end of the capacitor C10, and the first end of the resistor R12, respectively. The second end of the capacitor C10 is connected to the second end of the resistor R11 and the first end of the capacitor C5, respectively. The second end of the resistor R12 is connected to the first end of the resistor R11 and the first end of the resistor R10, respectively. A second terminal of the resistor R10 is connected to a first terminal of the capacitor C11 and a first terminal of the inductor L3, respectively. A second terminal of the inductor L3 is connected to a first terminal of the capacitor C6 and a first terminal of the resistor R5, respectively. The second terminal of the capacitor C11 and the second terminal of the capacitor C6 are both grounded. A second terminal of the resistor R5 is connected to the power supply voltage Vd and a first terminal of the capacitor C7, respectively. The second terminal of the capacitor C7 is connected to ground. The second end of the capacitor C5 is the output end of the output matching network 700, and is used for outputting the amplified radio frequency signal.
The output matching network 700 is formed by a resistor R10, a resistor R11, a resistor R12, a capacitor C10, a capacitor C11, an inductor L3, a capacitor C6 and a capacitor C5. The capacitor C5 is an output dc blocking capacitor. The resistor R3 is a rear-stage feedback resistor, and forms a series voltage-dividing bias network of the rear-stage field tube together with the resistor R2, the resistor R12, the resistor R10 and the resistor R5. The capacitor C7 is a power filter capacitor.
Further, referring to fig. 2, as an embodiment of the integrated amplifier provided by the present invention, the integrated amplifier further includes a bonding wire. The bonding wire comprises bonding wires W1, bonding wires W2, bonding wires W3, bonding wires W4, bonding wires W5, bonding wires W6, bonding wires W7 and bonding wires W8. A first terminal of the bonding wire W1 is connected to the second terminal of the capacitor C1, and a second terminal of the bonding wire W1 is connected to the gate of the first fet 100. A first end of the bonding wire W2 and a first end of the bonding wire W3 are both connected to the source of the first fet 100, and a second end of the bonding wire W2 and a second end of the bonding wire W3 are both grounded. A first end of the bonding wire W4 is connected to the drain of the first fet 100, and a second end of the bonding wire W4 is connected to the first end of the resistor R7. A first end of the bonding wire W5 is connected with a second end of the capacitor C3, and a second end of the bonding wire W5 is connected with a grid electrode of the second field effect transistor 200; a first end of the bonding wire W6 is connected with the drain electrode of the second field effect transistor 200, and a second end of the bonding wire W6 is connected with a first end of the resistor R12; a first end of the bonding wire W7 and a first end of the bonding wire W8 are both connected to the source of the second fet 200, and a second end of the bonding wire W7 and a second end of the bonding wire W8 are both grounded.
Further, as a specific embodiment of the integrated amplifier provided by the present invention, the length of the bonding wire ranges from 0.2mm to 1 mm. In this embodiment, the parasitic inductance parameter from the source of the field effect transistor chip to the ground can be adjusted by changing the number and length of the bonding wires of the source of the field effect transistor chip, thereby improving the stability of the circuit. The length of the bonding wire is changed from 0.2mm to 1mm, the inductance adjustment range is about 0.1 nH-0.9 nH, the longer the bonding wire is, the larger the inductance is, the larger the series impedance is, the bonding wire is added between the field tube source electrode and the ground, the effect of series negative feedback is realized, and the circuit stability can be improved. As shown in fig. 3, as the source inductance increases, the stability factor gradually increases, and the circuit becomes more stable.
Further, as a specific embodiment of the integrated amplifier provided by the present invention, the circuit substrate 800 is an LTCC substrate. The LTCC (Low Temperature Co-fired Ceramic) has the characteristics of excellent high-frequency and high-speed transmission and wide passband, can meet the requirements of high current and high Temperature resistance, has better thermal conductivity than a common PCB (printed Circuit Board) circuit substrate, greatly optimizes the heat dissipation design of electronic equipment, has high reliability, can be applied to severe environment and prolongs the service life of the electronic equipment.
Further, referring to fig. 4, as a specific embodiment of the integrated amplifier provided by the present invention, the metal housing 900 includes a metal enclosure frame 902 and a metal cover 901, and the metal enclosure frame 902 is fixedly connected to the circuit substrate 800 and the metal cover 901 respectively. The metal enclosure 902 is soldered on the LTCC multi-layer circuit substrate 800, the matching network elements are soldered on the LTCC circuit substrate 800, and the enhancement mode field effect transistor chips are bonded on the LTCC circuit substrate 800 and interconnected by gold bonding wires. The metal cover plate 901 is seam welded on the metal enclosure frame 902, so that the internal air tightness can be ensured.
Further, as a specific embodiment of the integrated amplifier provided by the present invention, the circuit substrate 800 is a multilayer, and projections of any two through holes on the circuit substrate 800 on parallel planes of the circuit substrate 800 do not include the same area. The inner airtightness can be effectively solved through the staggered arrangement of the through holes of all layers, and the ventilation between the through holes of the circuit substrate 800 and the outside is avoided.
Further, as a specific embodiment of the integrated amplifier provided by the present invention, the resistors in the circuit matching network include film resistors printed on the circuit substrate 800. And manufacturing a film resistor on the LTCC substrate in a screen printing mode to form part of resistor elements of the matching network, thereby further achieving the aim of miniaturization.
The specific manufacturing process of the integrated amplifier comprises the following steps: the circuit substrate 800 is manufactured by LTCC process. The raw ceramic tape material is DuPont951, the dielectric constant of the raw ceramic tape material is 7.8, and the layer sintering thickness is 0.095 mm. The substrate conductor material adopts an Au conductor, the part needing to be welded adopts a PdAg conductor, and the film resistance adopts paste with the square resistance of 100 omega or 10 omega according to the resistance value. After the circuit substrate 800 is formed by the low temperature co-firing technology, the metal enclosure 902 is soldered on the circuit substrate 800 to form a circuit package base. And finally, a metal cover plate 901 is sealed and welded on the assembled packaging base by adopting a parallel seam welding process, and finally the LTCC integrated packaging hybrid integrated low noise amplifier with an airtight effect is formed. The final device peripheral dimensions may be 9mm x 2.5 mm.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (9)
1. An integrated amplifier is characterized by comprising a circuit substrate, a metal shell fixedly connected with the circuit substrate, a field effect transistor and a circuit matching network, wherein the field effect transistor and the circuit matching network are arranged on the circuit substrate;
the field effect transistor comprises a first field effect transistor and a second field effect transistor; the circuit matching network comprises an input matching network, a first feedback bias network, an interstage matching network, a second feedback bias network and an output matching network;
the input end of the first field effect transistor is respectively connected with the output end of the input matching network and the first end of the first feedback bias network; the output end of the first field effect transistor is respectively connected with the second end of the first feedback bias network and the input end of the interstage matching network;
the input end of the second field effect transistor is respectively connected with the output end of the interstage matching network and the first end of the second feedback bias network; the output end of the second field effect transistor is respectively connected with the second end of the second feedback bias network and the input end of the output matching network;
the input matching network is used for carrying out impedance matching and noise matching on the input end of the first field effect transistor; the first field effect tube and the second field effect tube are used for amplifying radio frequency signals; the first feedback bias network is used for providing a static bias working point for the first field effect transistor and forming parallel negative feedback between the input end and the output end of the first field effect transistor; the interstage matching network is used for carrying out impedance matching between the first field effect transistor and the second field effect transistor; the second feedback bias network is used for providing a static bias working point for the second field effect transistor and forming parallel negative feedback at the input end and the output end of the second field effect transistor; the output end of the output matching network is used for outputting the amplified radio frequency signal;
wherein the first feedback bias network comprises a resistor R4, a resistor R1, a resistor R7, a resistor R9 and a resistor R6; the interstage matching network comprises the resistor R7, a resistor R8, the resistor R9, a capacitor C8, a capacitor C9, an inductor L2, a capacitor C4, a capacitor C3 and a resistor R2; a first end of the resistor R4 is connected with an input end of the first field effect transistor, and a second end of the resistor R4 is respectively connected with an output end of the first field effect transistor, a first end of the capacitor C8 and a first end of the resistor R7; a second end of the capacitor C8 is connected to a second end of the resistor R8 and a first end of the capacitor C3, respectively; a second end of the resistor R7 is respectively connected with a first end of the resistor R8 and a first end of the resistor R9; a first end of the resistor R9 is connected to a first end of the capacitor C9 and a first end of the inductor L2, respectively; a second end of the inductor L2 is connected to a first end of the capacitor C4 and a first end of the resistor R6, respectively; a second terminal of the capacitor C9 and a second terminal of the capacitor C4 are both grounded; a second end of the resistor R6 is respectively connected with a power supply voltage Vd and a first end of the capacitor C7; the second end of the capacitor C7 is grounded; the second end of the capacitor C3 is connected with the first end of the resistor R2; the second end of the resistor R2 is grounded; the second terminal of the capacitor C3 is the output terminal of the interstage matching network.
2. The integrated amplifier of claim 1, wherein the input matching network comprises a capacitor C1, an inductor L1, a resistor R1, and a capacitor C2; a first end of the inductor L1 is connected to a second end of the capacitor C1, and a second end of the inductor L1 is connected to a first end of the resistor R1 and a first end of the capacitor C2, respectively; a second terminal of the resistor R1 and a second terminal of the capacitor C2 are both grounded; the first end of the capacitor C1 is the input end of the input matching network; the second terminal of the capacitor C1 is the output terminal of the input matching network.
3. The integrated amplifier of claim 2, wherein the second feedback bias network comprises a resistor R3, the resistor R2, a resistor R12, a resistor R10, and a resistor R5; the output matching network comprises the resistor R10, a resistor R11, the resistor R12, a capacitor C10, a capacitor C11, an inductor L3, a capacitor C6 and a capacitor C5; a first end of the resistor R3 is connected to an input end of the second fet, and a second end of the resistor R3 is connected to an output end of the second fet, a first end of the capacitor C10, and a first end of the resistor R12, respectively; a second end of the capacitor C10 is connected to a second end of the resistor R11 and a first end of the capacitor C5, respectively; a second end of the resistor R12 is respectively connected with a first end of the resistor R11 and a first end of the resistor R10; a second end of the resistor R10 is connected to a first end of the capacitor C11 and a first end of the inductor L3, respectively; a second end of the inductor L3 is connected to a first end of the capacitor C6 and a first end of the resistor R5, respectively; a second terminal of the capacitor C11 and a second terminal of the capacitor C6 are both grounded; a second end of the resistor R5 is respectively connected with the power supply voltage Vd and a first end of the capacitor C7; the second end of the capacitor C7 is grounded; the second end of the capacitor C5 is the output end of the output matching network, and is used for outputting the amplified radio frequency signal.
4. The integrated amplifier of claim 3, further comprising a bond wire comprising bond wire W1, bond wire W2, bond wire W3, bond wire W4, bond wire W5, bond wire W6, bond wire W7, and bond wire W8; a first end of the bonding wire W1 is connected with a second end of the capacitor C1, and a second end of the bonding wire W1 is connected with a grid electrode of the first field effect transistor; a first end of the bonding wire W2 and a first end of the bonding wire W3 are both connected with the source electrode of the first field effect transistor, and a second end of the bonding wire W2 and a second end of the bonding wire W3 are both grounded; a first end of the bonding wire W4 is connected with the drain electrode of the first field effect transistor, and a second end of the bonding wire W4 is connected with a first end of the resistor R7; a first end of the bonding wire W5 is connected with a second end of the capacitor C3, and a second end of the bonding wire W5 is connected with a grid electrode of the second field effect transistor; a first end of the bonding wire W6 is connected with the drain electrode of the second field effect transistor, and a second end of the bonding wire W6 is connected with a first end of the resistor R12; a first end of the bonding wire W7 and a first end of the bonding wire W8 are both connected with the source of the second fet, and a second end of the bonding wire W7 and a second end of the bonding wire W8 are both grounded.
5. The integrated amplifier of claim 4, wherein the bond wire has a length in a range of 0.2mm to 1 mm.
6. The integrated amplifier of claim 1, wherein the circuit substrate is an LTCC substrate.
7. The integrated amplifier of claim 1, wherein the metal housing comprises a metal enclosure frame and a metal cover plate, the metal enclosure frame being fixedly connected to the circuit substrate and the metal cover plate, respectively.
8. The integrated amplifier of claim 1, wherein the circuit substrate is multi-layered, and projections of any two vias on the circuit substrate onto parallel planes of the circuit substrate do not contain the same area.
9. The integrated amplifier of any of claims 1-8, wherein the resistors in the circuit matching network comprise film resistors silk-screened onto the circuit substrate.
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| CN209375586U (en) * | 2018-11-30 | 2019-09-10 | 南京米乐为微电子科技有限公司 | A kind of ultra-low noise amplifier |
| CN110798152B (en) * | 2019-10-22 | 2022-04-26 | 北京信芯科技有限公司 | Low-noise amplifier |
| CN116094469B (en) * | 2023-04-11 | 2023-06-30 | 南京米乐为微电子科技有限公司 | Common gate amplifying circuit, low noise amplifier and ultra-wideband receiver |
| CN118413196A (en) * | 2024-04-25 | 2024-07-30 | 睿思微系统(烟台)有限公司 | Power amplifier module and device |
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