CN107230624A - Gallium nitride transistor and its manufacture method - Google Patents
Gallium nitride transistor and its manufacture method Download PDFInfo
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- CN107230624A CN107230624A CN201610178243.3A CN201610178243A CN107230624A CN 107230624 A CN107230624 A CN 107230624A CN 201610178243 A CN201610178243 A CN 201610178243A CN 107230624 A CN107230624 A CN 107230624A
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- gallium nitride
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- aluminum gallium
- nitride layer
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 182
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 72
- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000010410 layer Substances 0.000 claims abstract description 277
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 111
- 230000004888 barrier function Effects 0.000 claims abstract description 47
- 239000011241 protective layer Substances 0.000 claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims description 68
- 239000002184 metal Substances 0.000 claims description 68
- 239000010936 titanium Substances 0.000 claims description 30
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 29
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 29
- 229910052719 titanium Inorganic materials 0.000 claims description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 28
- 238000002161 passivation Methods 0.000 claims description 27
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 14
- 229910052782 aluminium Inorganic materials 0.000 claims description 13
- 239000004411 aluminium Substances 0.000 claims description 13
- 239000012528 membrane Substances 0.000 claims description 12
- 238000003475 lamination Methods 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000005036 potential barrier Methods 0.000 claims description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 238000004381 surface treatment Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 229910003978 SiClx Inorganic materials 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of gallium nitride transistor and its manufacture method, and wherein method includes：The aluminum gallium nitride layer of p-type doping is formed in barrier layer surface, wherein, the width of the aluminum gallium nitride layer of the p-type doping is less than the width of the barrier layer；The both sides of the aluminum gallium nitride layer adulterated in the p-type, the surface of the barrier layer, deposit protective layer；In the protective layer for the aluminum gallium nitride layer both sides that the p-type is adulterated, contact hole is opened up respectively；Source electrode and drain electrode are formed respectively in the contact hole for the aluminum gallium nitride layer both sides that the p-type is adulterated；Grid is formed above the aluminum gallium nitride layer that the p-type is adulterated.Gallium nitride transistor and its manufacture method that the present invention is provided, can realize that device is often closed, and meet practical application request, and can reduce the conducting resistance of device, so that the conduction loss of device is reduced, the overall performance of boost device.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of gallium nitride transistor and its manufacturer
Method.
Background technology
Gallium nitride (GaN) is third generation semiconductor material with wide forbidden band, due to its have big energy gap,
High electron saturation velocities, high breakdown electric field, higher heat-conductivity, corrosion-resistant and radiation-resistant performance, its
Apply has stronger advantage under high pressure, high frequency, high temperature, high-power and Flouride-resistani acid phesphatase environmental condition,
It is considered as the optimal material of shortwave opto-electronic device and high voltagehigh frequency rate high power device.Therefore, nitrogen
Change gallium transistor has become the study hotspot in power device.
But, gallium nitride transistor of the prior art is all open type, in order to meet practical application
Demand, makes gallium nitride transistor compatible with traditional high power transistor, develops normally-off gallium nitride brilliant
Body pipe is very important.
The content of the invention
The present invention provides a kind of gallium nitride transistor and its manufacture method, to manufacture normally-off gallium nitride
Transistor, makes up the deficiencies in the prior art.
The present invention provides a kind of gallium nitride pipe manufacturing method, including：
The aluminum gallium nitride layer of p-type doping is formed in barrier layer surface, wherein, the p-type doping
Aluminum gallium nitride layer width be less than the barrier layer width；
The both sides of the aluminum gallium nitride layer adulterated in the p-type, the surface of the barrier layer, deposition
Protective layer；
In the protective layer for the aluminum gallium nitride layer both sides that the p-type is adulterated, contact hole is opened up respectively；
Source electrode and leakage are formed respectively in the contact hole for the aluminum gallium nitride layer both sides that the p-type is adulterated
Pole；
Grid is formed above the aluminum gallium nitride layer that the p-type is adulterated.
Method as described above, the both sides of the aluminum gallium nitride layer adulterated in the p-type, the barrier layer
Surface, deposit protective layer, including：
The both sides of the aluminum gallium nitride layer adulterated in the p-type, the surface of the barrier layer, deposition
One layer of silicon nitride passivation, the height of the silicon nitride passivation is less than the gallium nitride that the p-type is adulterated
The height of aluminium lamination；
The both sides of the aluminum gallium nitride layer adulterated in the p-type, the surface of the silicon nitride passivation,
Deposit one layer of PETEOS oxide layer；
Wherein, the silicon nitride passivation and the PETEOS oxide layers form the protective layer.
Method as described above, before the aluminum gallium nitride layer of potential barrier layer surface formation p-type doping, also
Including：
Formed on a silicon substrate undoped with gallium nitride layer；
It is described undoped with gallium nitride layer on formed undoped with aluminum gallium nitride layer as the potential barrier
Layer.
Method as described above, in the contact hole for the aluminum gallium nitride layer both sides that the p-type is adulterated
Source electrode and drain electrode are formed respectively, including：
Surface treatment before metal deposit is carried out to the contact hole；
Using magnetron sputtering membrane process, above the aluminum gallium nitride layer that the p-type is adulterated, the guarantor
Deposit ohmic electrode metal layer in sheath and the contact hole；
The Ohmic electrode metal level is performed etching using photoetching process, source electrode and drain electrode is formed.
Method as described above, using magnetron sputtering membrane process, the gallium nitride adulterated in the p-type
Deposit ohmic electrode metal layer in aluminium lamination top, the protective layer and the contact hole, including：
Using magnetron sputtering membrane process, above the aluminum gallium nitride layer that the p-type is adulterated, the guarantor
The first layer of titanium metal is deposited in sheath and the contact hole, the thickness of first layer of titanium metal is
200 angstroms；
The deposited metal aluminium lamination in first layer of titanium metal, the thickness of the metallic aluminum is 1200
Angstrom；
The second layer of titanium metal is deposited on the metallic aluminum, the thickness of second layer of titanium metal is
200 angstroms；
The titanium nitride layer in second layer of titanium metal, the thickness of the titanium nitride layer is 200 angstroms；
Wherein, first layer of titanium metal, the metallic aluminum, second layer of titanium metal and institute
State titanium nitride layer and form the Ohmic electrode metal level.
Method as described above, is using magnetron sputtering membrane process, the nitridation adulterated in the p-type
In gallium aluminium lamination top, the protective layer and the contact hole after deposit ohmic electrode metal layer, also
Including：
Under conditions of nitrogen, 30s annealing process is carried out using 840 DEG C of annealing temperatures.
Method as described above, grid is formed above the aluminum gallium nitride layer that the p-type is adulterated, including：
Using magnetron sputtering membrane process, grid is deposited on the surface of the aluminum gallium nitride layer adulterated in p-type
Metal level；
Photoresist is smeared on the subregion of the gate metal layer；
The gate metal layer is performed etching under the stop of photoresist, and removed after the completion of etching
Photoresist, forms grid；
Wherein, the width of the grid is less than the width for the aluminum gallium nitride layer that the p-type is adulterated.
The present invention also provides a kind of gallium nitride transistor, including：Barrier layer, on the barrier layer
The aluminum gallium nitride layer of the p-type doping of side and be arranged on above the barrier layer, p-type doping
The protective layer that two layers of aluminum gallium nitride layer；
Wherein, contact hole is offered respectively in the protective layer of the aluminum gallium nitride layer both sides of the p-type doping；
Source electrode is formed with the contact hole of the aluminum gallium nitride layer side of the p-type doping, the p-type is mixed
Drain electrode is formed with the contact hole of miscellaneous aluminum gallium nitride layer opposite side；
Grid is formed with above the aluminum gallium nitride layer of the p-type doping.
Gallium nitride transistor as described above, the protective layer includes：Silicon nitride passivation and PETEOS
Oxide layer；
The silicon nitride passivation is located at the both sides for the aluminum gallium nitride layer that the p-type is adulterated, the potential barrier
The top of layer, the height of the silicon nitride passivation is less than the height for the aluminum gallium nitride layer that the p-type is adulterated
Degree；
The PETEOS oxide layers are located at the both sides for the aluminum gallium nitride layer that the p-type is adulterated, the nitrogen
The top of SiClx passivation layer.
Gallium nitride transistor as described above, in addition to：Silicon substrate and undoped with gallium nitride layer；
It is described undoped with gallium nitride layer be located at the silicon substrate top；
The barrier layer be located at it is described undoped with gallium nitride layer top.
Gallium nitride transistor and its manufacture method that the present invention is provided, by barrier layer surface shape
The aluminum gallium nitride layer adulterated into p-type, the both sides of the aluminum gallium nitride layer adulterated in the p-type, the gesture
The surface of barrier layer, deposits protective layer, the protection for the aluminum gallium nitride layer both sides adulterated in the p-type
In layer, contact hole is opened up respectively, the contact hole for the aluminum gallium nitride layer both sides adulterated in the p-type
It is middle to form source electrode and drain electrode respectively, form grid, energy above the aluminum gallium nitride layer that the p-type is adulterated
The gallium nitride transistor of normally-off is enough produced, practical application request is met, and upper electric back cavitation can be with
Two-dimensional electron gas is injected into from grid, causes conductivity modulation effect, the conducting resistance of device is reduced, from
And the conduction loss of device is reduced, the overall performance of boost device.
Brief description of the drawings
Fig. 1 is the flow chart for the gallium nitride pipe manufacturing method that the embodiment of the present invention one is provided；
In potential barrier layer surface in the gallium nitride pipe manufacturing method that Fig. 2 provides for the embodiment of the present invention one
The device architecture schematic diagram formed after the aluminum gallium nitride layer of p-type doping；
Silicon nitride is formed in the gallium nitride pipe manufacturing method that Fig. 3 provides for the embodiment of the present invention one blunt
Change the device architecture schematic diagram after layer and PETEOS oxide layers；
Formed in the gallium nitride pipe manufacturing method that Fig. 4 provides for the embodiment of the present invention one after contact hole
Device architecture schematic diagram；
Fig. 5 is formation source electrode and leakage in the gallium nitride pipe manufacturing method that the embodiment of the present invention one is provided
The method flow diagram of pole；
Ohmic electrode is formed in the gallium nitride pipe manufacturing method that Fig. 6 provides for the embodiment of the present invention one
Device architecture schematic diagram after metal level；
Fig. 7 is formation source electrode and leakage in the gallium nitride pipe manufacturing method that the embodiment of the present invention one is provided
Device architecture schematic diagram after extremely；
Formed in the gallium nitride pipe manufacturing method that Fig. 8 provides for the embodiment of the present invention one after grid
Device architecture schematic diagram.
Reference：
1- silicon substrate 2- gallium nitride layer 3- barrier layers
The aluminum gallium nitride layer 5- silicon nitride passivation 6-PETEOS oxide layers of 4-P types doping
7- contact hole 8- Ohmic electrode metal level 9- source electrodes
10- drain electrode 11- grids
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with this
Accompanying drawing in inventive embodiments, is clearly and completely retouched to the technical scheme in the embodiment of the present invention
State, it is clear that described embodiment is a part of embodiment of the invention, rather than whole embodiments.
Based on the embodiment in the present invention, those of ordinary skill in the art are not making creative work premise
Lower obtained every other embodiment, belongs to the scope of protection of the invention.
Embodiment one
The embodiment of the present invention one provides a kind of gallium nitride pipe manufacturing method.Fig. 1 is implemented for the present invention
The flow chart for the gallium nitride pipe manufacturing method that example one is provided.As shown in figure 1, in the present embodiment
Gallium nitride pipe manufacturing method, can include：
Step 101, the aluminum gallium nitride layer 4 in the surface of barrier layer 3 formation p-type doping, wherein,
The width of the aluminum gallium nitride layer 4 of the p-type doping is less than the width of the barrier layer 3.
The aluminum gallium nitride layer 4 of the p-type doping is the aluminum gallium nitride (AlGaN) for being doped with p-type ion
Layer.P-type ion can include but is not limited to：Triad boron, indium, gallium etc..The p-type adulterated
The concentration of ion can be determined according to actual needs.The barrier layer 3 be one layer undoped with nitridation
Gallium aluminium lamination.
In the table of barrier layer 3 in the gallium nitride pipe manufacturing method that Fig. 2 provides for the embodiment of the present invention one
The device architecture schematic diagram that face is formed after the aluminum gallium nitride layer 4 of p-type doping.As shown in Fig. 2 institute
The lower section for stating barrier layer 3 is additionally provided with gallium nitride (GaN) layer 2 and silicon (Si) substrate 1.
Specifically, before step 101, the He of gallium nitride layer 2 can be formed by the following method
Barrier layer 3：
Formed on silicon substrate 1 undoped with gallium nitride layer 2；
It is described undoped with gallium nitride layer 2 on formed undoped with aluminum gallium nitride layer as the potential barrier
Layer 3.
Step 102, the both sides of aluminum gallium nitride layer 4 adulterated in the p-type, the barrier layer 3
Surface, deposits protective layer.
It is described protective layer used to be played a protective role in the barrier layer 3.The height of the protective layer can
With the height of the aluminum gallium nitride layer 4 adulterated equal to or less than the p-type.The protective layer is located at institute
State the left and right sides of the aluminum gallium nitride layer 4 of p-type doping.
Specifically, the protective layer can include silicon nitride (Si3N4) passivation layer 5 and PETEOS
(PETEOS Plasma Enhanced TEOS, the plasma enhancing of tetraethyl orthosilicate) oxide layer.
Accordingly, the both sides of the aluminum gallium nitride layer 4 adulterated in the p-type in this step, the barrier layer
3 surface, deposits protective layer, can include：
The both sides of the aluminum gallium nitride layer 4 adulterated in the p-type, the surface of the barrier layer 3,
One layer of silicon nitride passivation 5 is deposited, the height of the silicon nitride passivation 5 is adulterated less than the p-type
Aluminum gallium nitride layer 4 height；
The both sides of the aluminum gallium nitride layer 4 adulterated in the p-type, the surface of the silicon nitride passivation 5
Top, deposits one layer of PETEOS oxide layer 6, the height of the PETEOS oxide layers 6 is less than described
The height of the aluminum gallium nitride layer 4 of p-type doping.
Silicon nitride is formed in the gallium nitride pipe manufacturing method that Fig. 3 provides for the embodiment of the present invention one blunt
Change the device architecture schematic diagram after layer 5 and PETEOS oxide layers 6.As shown in figure 3, silicon nitride is blunt
Change layer 5 and PETEOS oxide layers 6 are covered in the top of barrier layer 3, barrier layer 3 can be played
Certain protective effect.
Certainly, the protective layer can be not limited only to silicon nitride passivation 5 and PETEOS oxide layers 6.
In other embodiments, silicon nitride passivation 5 and PETEOS can also be replaced to aoxidize with other materials
Layer 6 is as protective layer, and the present embodiment is not restricted to this.
Step 103, the p-type adulterate the both sides of aluminum gallium nitride layer 4 protective layer in, open respectively
If contact hole 7.
Specifically, it is possible to use protective layer described in dry etching, connect so as to be formed in the protective layer
Contact hole 7.Fig. 4 is formation contact in the gallium nitride pipe manufacturing method that the embodiment of the present invention one is provided
Device architecture schematic diagram behind hole 7.As shown in figure 4, having etched two contact holes in protective layer
7, two contact holes 7 are located at the both sides for the aluminum gallium nitride layer 4 that the p-type is adulterated respectively.
Step 104, the p-type adulterate the both sides of aluminum gallium nitride layer 4 the contact hole 7 in point
Xing Cheng not source electrode 9 and drain electrode 10.
Fig. 5 is the formation He of source electrode 9 in the gallium nitride pipe manufacturing method that the embodiment of the present invention one is provided
The method flow diagram of drain electrode 10.As shown in figure 5, step 104 can be specifically included：
Step 1041, to the contact hole 7 carry out metal deposit before surface treatment.
Surface treatment before the metal deposit, can include：Using DHF+SC1+SC2 method pair
The surface of the contact hole 7 is cleaned, wherein, DHF expressions are cleaned with dilute hydrogen fluoride acid, SC1 tables
Show standardization first step cleaning, SC2 represents standardization second step cleaning, the time of three cleanings
To be arranged on 50s between 80s.
Step 1042, using magnetron sputtering membrane process, the aluminum gallium nitride layer 4 adulterated in the p-type
Deposit ohmic electrode metal layer 8 in top, the protective layer and the contact hole 7.
The Ohmic electrode metal level 8 can include four layers of medium, four layers of medium according to from it is lower to
On order be followed successively by titanium (Ti), aluminium (Al), titanium and titanium nitride (TiN).
Specifically, after being surface-treated to the contact hole 7, magnetron sputtering can be used
Membrane process, the top of aluminum gallium nitride layer 4, the protective layer and the contact adulterated in the p-type
Deposited metal titanium in hole 7, forms the first layer of titanium metal, the thickness of first layer of titanium metal is 200
Angstrom；
Then, the deposited metal aluminium in first layer of titanium metal, forms metallic aluminum, the metal
The thickness of aluminium lamination is 1200 angstroms；
Again, the deposited metal titanium on the metallic aluminum, forms the second layer of titanium metal, described second
The thickness of layer of titanium metal is 200 angstroms；
Finally, the depositing titanium nitride in second layer of titanium metal, forms titanium nitride layer, the nitridation
The thickness of titanium layer is 200 angstroms.
Wherein, first layer of titanium metal, the metallic aluminum, second layer of titanium metal and institute
State titanium nitride layer and constitute the Ohmic electrode metal level 8.
Ohmic electrode is formed in the gallium nitride pipe manufacturing method that Fig. 6 provides for the embodiment of the present invention one
Device architecture schematic diagram after metal level 8.As shown in fig. 6, the Ohmic electrode metal level 8 is covered
The aluminum gallium nitride layer 4 adulterated in the contact hole 7, the PETEOS oxide layers 6 and the p-type
Top.
Further, magnetron sputtering membrane process is being used, the aluminum gallium nitride layer adulterated in the p-type
In 4 tops, the protective layer and the contact hole 7 after deposit ohmic electrode metal layer 8, also
Device can be annealed.
Specifically, moving back for 30s can be carried out using 840 DEG C of annealing temperatures under conditions of nitrogen
Ignition technique.The Ohmic electrode metal level 8 after annealing can form good Ohmic contact.
Step 1043, using photoetching process the Ohmic electrode metal level 8 is performed etching, form source
Pole 9 and drain electrode 10.
Specifically, photoresist can be smeared in the top of the subregion of the Ohmic electrode metal level 8,
And the Ohmic electrode metal level 8 is performed etching under the stop of photoresist, only retain described in being located at
Ohmic electrode metal level 8 in contact hole 7, to form the source electrode 9 and drain electrode 10.
Fig. 7 is the formation He of source electrode 9 in the gallium nitride pipe manufacturing method that the embodiment of the present invention one is provided
Device architecture schematic diagram after drain electrode 10.As shown in fig. 7, source electrode 9 and drain electrode 10 are located at institute respectively
State the left and right sides of the aluminum gallium nitride layer 4 of p-type doping.
In summary, it is formed gallium nitride transistor by above-mentioned steps 1041 to step 1043
Source electrode 9 and drain electrode 10.
Step 105, the top of aluminum gallium nitride layer 4 adulterated in the p-type form grid 11.
Specifically, magnetron sputtering membrane process can be used, the aluminum gallium nitride layer 4 adulterated in p-type
Gate metal layer is deposited on surface, the gate metal layer can be arranged on the p-type including one layer and mix
Metallic nickel (Ni) layer on the surface of miscellaneous aluminum gallium nitride layer 4 and one layer are arranged on the metallic nickel
Metallic gold (Au) layer on layer.
After the gate metal layer is formed, it can be smeared on the subregion of the gate metal layer
Photoresist, is performed etching under the stop of photoresist to the gate metal layer, and after the completion of etching
Photoresist is removed, grid 11 is formed.
Fig. 8 is formation grid 11 in the gallium nitride pipe manufacturing method that the embodiment of the present invention one is provided
Device architecture schematic diagram afterwards.As shown in figure 8, the width of the grid 11 can be less than the P
The width of the aluminum gallium nitride layer 4 of type doping.
The work of the gallium nitride transistor of the method manufacture provided according to the present embodiment is described with reference to Fig. 8
Make principle and beneficial effect.As shown in figure 8, after the power-up, electric current flows to source electrode 9 by drain electrode 10,
Because the gallium nitride transistor uses P-type grid electrode 11, therefore, it is possible to raise channel barrier, device is realized
Part is often closed.In addition, after grid 11 plus positive voltage, a large amount of skies in the aluminum gallium nitride layer 4 of p-type doping
Cave can enter lower section undoped with aluminum gallium nitride layer, i.e., into barrier layer 3, the electronics in raceway groove
Barrier layer 3 can be entered, so that electronics and hole are combined, reduce the resistance of the lower section of grid 11, so that
Reduce the overall conducting resistance of device.
The gallium nitride pipe manufacturing method that the present embodiment is provided, by the surface shape of barrier layer 3
The aluminum gallium nitride layer 4 adulterated into p-type, the both sides of the aluminum gallium nitride layer 4 adulterated in the p-type, institute
The surface of barrier layer 3 is stated, protective layer is deposited, 4 liang of the aluminum gallium nitride layer adulterated in the p-type
In the protective layer of side, contact hole 7 is opened up respectively, the both sides of aluminum gallium nitride layer 4 adulterated in the p-type
The contact hole 7 in formed respectively source electrode 9 and drain electrode 10, the p-type adulterate aluminum gallium nitride
The top of layer 4 forms grid 11, can produce the gallium nitride transistor of normally-off, meet practical application
Demand, and upper electric back cavitation can be injected into two-dimensional electron gas from grid 11, cause conductance modulation to be imitated
Should, the conducting resistance of device is reduced, so that the conduction loss of device is reduced, the globality of boost device
Energy.
Embodiment two
The embodiment of the present invention two provides a kind of gallium nitride transistor.The gallium nitride that the present embodiment is provided
The concrete structure of pipe is referred to Fig. 8.As shown in figure 8, the gallium nitride transistor in the present embodiment,
It can include：
Aluminum gallium nitride layer 4 and set that barrier layer 3, the p-type positioned at the top of barrier layer 3 are adulterated
Put the protective layer of two layers of the aluminum gallium nitride layer 4 in the top of the barrier layer 3, p-type doping；
Wherein, contact is offered respectively in the protective layer of the both sides of aluminum gallium nitride layer 4 of the p-type doping
Hole 7；
Source electrode 9 is formed with the contact hole 7 of the side of aluminum gallium nitride layer 4 of the p-type doping, it is described
Drain electrode 10 is formed with the contact hole 7 of the opposite side of aluminum gallium nitride layer 4 of p-type doping；
The top of the aluminum gallium nitride layer 4 of the p-type doping is formed with grid 11.
Specifically, the gallium nitride transistor in the present embodiment, can be using the method described in embodiment one
It is fabricated by, it is implemented, and principle and manufacturing process are similar with embodiment one, and here is omitted.
The gallium nitride transistor that the present embodiment is provided, p-type doping is formed with the surface of barrier layer 3
Aluminum gallium nitride layer 4, the both sides of aluminum gallium nitride layer 4 adulterated in the p-type, the barrier layer 3
Surface, deposit matcoveredn, the p-type adulterate the both sides of aluminum gallium nitride layer 4 protection
In layer, contact hole 7 is offered respectively, described in the both sides of aluminum gallium nitride layer 4 adulterated in the p-type
Source electrode 9 and drain electrode 10 are respectively formed with contact hole 7, the aluminum gallium nitride layer 4 adulterated in the p-type
Top is formed with grid 11, so as to realize the gallium nitride transistor of normally-off, meets practical application request,
And upper electric back cavitation can be injected into two-dimensional electron gas from grid 11, cause conductivity modulation effect, drop
The conducting resistance of low device, so that the conduction loss of device is reduced, the overall performance of boost device.
On the basis of the technical scheme that above-described embodiment is provided, it is preferred that the protective layer can be with
Including：Silicon nitride passivation 5 and PETEOS oxide layers 6；
The silicon nitride passivation 5 is located at the both sides, described for the aluminum gallium nitride layer 4 that the p-type is adulterated
The top of barrier layer 3, the height of the silicon nitride passivation 5 is less than the gallium nitride that the p-type is adulterated
The height of aluminium lamination 4；
The PETEOS oxide layers 6 are located at the both sides for the aluminum gallium nitride layer 4 that the p-type is adulterated, institute
State the top of silicon nitride passivation 5.
On the basis of the technical scheme that above-described embodiment is provided, it is preferred that the gallium nitride
Pipe, can also include：Silicon substrate 1 and undoped with gallium nitride layer 2；
It is described undoped with gallium nitride layer 2 be located at the silicon substrate 1 top；
The barrier layer 3 be located at it is described undoped with gallium nitride layer 2 top.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than
It is limited；Although the present invention is described in detail with reference to foregoing embodiments, this area
Those of ordinary skill should be understood：It can still enter to the technical scheme described in foregoing embodiments
Row modification, or equivalent substitution is carried out to which part or all technical characteristic；And these modification or
Person replaces, and the essence of appropriate technical solution is departed from the model of various embodiments of the present invention technical scheme
Enclose.
Claims (10)
1. a kind of gallium nitride pipe manufacturing method, it is characterised in that including：
The aluminum gallium nitride layer of p-type doping is formed in barrier layer surface, wherein, the p-type doping
Aluminum gallium nitride layer width be less than the barrier layer width；
The both sides of the aluminum gallium nitride layer adulterated in the p-type, the surface of the barrier layer, deposition
Protective layer；
In the protective layer for the aluminum gallium nitride layer both sides that the p-type is adulterated, contact hole is opened up respectively；
Source electrode and leakage are formed respectively in the contact hole for the aluminum gallium nitride layer both sides that the p-type is adulterated
Pole；
Grid is formed above the aluminum gallium nitride layer that the p-type is adulterated.
2. according to the method described in claim 1, it is characterised in that the nitrogen adulterated in the p-type
Change both sides, the surface of the barrier layer of gallium aluminium lamination, deposit protective layer, including：
The both sides of the aluminum gallium nitride layer adulterated in the p-type, the surface of the barrier layer, deposition
One layer of silicon nitride passivation, the height of the silicon nitride passivation is less than the gallium nitride that the p-type is adulterated
The height of aluminium lamination；
The both sides of the aluminum gallium nitride layer adulterated in the p-type, the surface of the silicon nitride passivation,
Deposit one layer of PETEOS oxide layer；
Wherein, the silicon nitride passivation and the PETEOS oxide layers form the protective layer.
3. according to the method described in claim 1, it is characterised in that in potential barrier layer surface formation P
Before the aluminum gallium nitride layer of type doping, in addition to：
Formed on a silicon substrate undoped with gallium nitride layer；
It is described undoped with gallium nitride layer on formed undoped with aluminum gallium nitride layer as the potential barrier
Layer.
4. the method according to claim any one of 1-3, it is characterised in that in the p-type
Source electrode and drain electrode are formed respectively in the contact hole of the aluminum gallium nitride layer both sides of doping, including：
Surface treatment before metal deposit is carried out to the contact hole；
Using magnetron sputtering membrane process, above the aluminum gallium nitride layer that the p-type is adulterated, the guarantor
Deposit ohmic electrode metal layer in sheath and the contact hole；
The Ohmic electrode metal level is performed etching using photoetching process, source electrode and drain electrode is formed.
5. method according to claim 4, it is characterised in that use magnetron sputtering plating work
Skill, sinks above the aluminum gallium nitride layer that the p-type is adulterated, in the protective layer and the contact hole
Product Ohmic electrode metal level, including：
Using magnetron sputtering membrane process, above the aluminum gallium nitride layer that the p-type is adulterated, the guarantor
The first layer of titanium metal is deposited in sheath and the contact hole, the thickness of first layer of titanium metal is
200 angstroms；
The deposited metal aluminium lamination in first layer of titanium metal, the thickness of the metallic aluminum is 1200
Angstrom；
The second layer of titanium metal is deposited on the metallic aluminum, the thickness of second layer of titanium metal is
200 angstroms；
The titanium nitride layer in second layer of titanium metal, the thickness of the titanium nitride layer is 200 angstroms；
Wherein, first layer of titanium metal, the metallic aluminum, second layer of titanium metal and institute
State titanium nitride layer and form the Ohmic electrode metal level.
6. method according to claim 4, it is characterised in that using magnetron sputtering plating
Technique, above the aluminum gallium nitride layer that the p-type is adulterated, in the protective layer and the contact hole
After deposit ohmic electrode metal layer, in addition to：
Under conditions of nitrogen, 30s annealing process is carried out using 840 DEG C of annealing temperatures.
7. according to the method described in claim 1, it is characterised in that the nitrogen adulterated in the p-type
Change and grid is formed above gallium aluminium lamination, including：
Using magnetron sputtering membrane process, grid is deposited on the surface of the aluminum gallium nitride layer adulterated in p-type
Metal level；
Photoresist is smeared on the subregion of the gate metal layer；
The gate metal layer is performed etching under the stop of photoresist, and removed after the completion of etching
Photoresist, forms grid；
Wherein, the width of the grid is less than the width for the aluminum gallium nitride layer that the p-type is adulterated.
8. a kind of gallium nitride transistor, it is characterised in that including：Barrier layer, positioned at the potential barrier
The aluminum gallium nitride layer of p-type doping above layer and be arranged on above the barrier layer, the p-type is mixed
The protective layer of miscellaneous aluminum gallium nitride layer both sides；
Wherein, contact hole is offered respectively in the protective layer of the aluminum gallium nitride layer both sides of the p-type doping；
Source electrode is formed with the contact hole of the aluminum gallium nitride layer side of the p-type doping, the p-type is mixed
Drain electrode is formed with the contact hole of miscellaneous aluminum gallium nitride layer opposite side；
Grid is formed with above the aluminum gallium nitride layer of the p-type doping.
9. gallium nitride transistor according to claim 8, it is characterised in that the protective layer
Including：Silicon nitride passivation and PETEOS oxide layers；
The silicon nitride passivation is located at the both sides for the aluminum gallium nitride layer that the p-type is adulterated, the potential barrier
The top of layer, the height of the silicon nitride passivation is less than the height for the aluminum gallium nitride layer that the p-type is adulterated
Degree；
The PETEOS oxide layers are located at the both sides for the aluminum gallium nitride layer that the p-type is adulterated, the nitrogen
The top of SiClx passivation layer.
10. gallium nitride transistor according to claim 8 or claim 9, it is characterised in that also include：
Silicon substrate and undoped with gallium nitride layer；
It is described undoped with gallium nitride layer be located at the silicon substrate top；
The barrier layer be located at it is described undoped with gallium nitride layer top.
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| CN108447788A (en) * | 2018-04-19 | 2018-08-24 | 中国电子科技集团公司第十三研究所 | The preparation method of enhancement type high electron mobility transistor |
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