CN106788379A - A kind of radiation hardening latch based on isomery duplication redundancy - Google Patents
A kind of radiation hardening latch based on isomery duplication redundancy Download PDFInfo
- Publication number
- CN106788379A CN106788379A CN201611072873.9A CN201611072873A CN106788379A CN 106788379 A CN106788379 A CN 106788379A CN 201611072873 A CN201611072873 A CN 201611072873A CN 106788379 A CN106788379 A CN 106788379A
- Authority
- CN
- China
- Prior art keywords
- pipes
- drain electrode
- grid
- source electrode
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005510 radiation hardening Methods 0.000 title claims abstract description 17
- 210000004027 cell Anatomy 0.000 claims abstract description 67
- 210000003771 C cell Anatomy 0.000 claims abstract description 40
- 230000005540 biological transmission Effects 0.000 claims abstract description 34
- 239000000203 mixture Substances 0.000 claims description 11
- 239000007787 solid Substances 0.000 claims 1
- 238000001914 filtration Methods 0.000 abstract description 3
- 230000006870 function Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 8
- 239000002245 particle Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000005855 radiation Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/0033—Radiation hardening
- H03K19/00338—In field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
Abstract
The present invention relates to a kind of radiation hardening latch based on isomery duplication redundancy, including the first memory cell, transmission unit, the second memory cell and C cell；First memory cell, transmission unit, the signal input part of the second memory cell meet input signal D, the signal output part of first memory cell is connected with the first signal input part of C cell, the signal output part of second memory cell is connected with the secondary signal input of C cell, the signal output of the transmission unit terminates the signal output part of C cell, the signal output part of C cell as radiation hardening latch output end.The SET filtering functions of Schmidt trigger in the present invention so that latch filters SET pulse in transparent period；The first memory cell and the second memory cell that the present invention is used all have the ability of tolerance single-point and two point upset, and it is combined with C cell, latch is tolerated that single-point upset and multiple spot overturn, with good fault freedom.
Description
Technical field
The present invention relates to radiation hardened integrated circuit design field, especially a kind of anti-spoke based on isomery duplication redundancy
Penetrate reinforcing latch.
Background technology
In aeronautical environment, due to the influence of cosmic ray, various particles, including α particles, proton and neutron can be produced,
When these particles are got on aircraft, it will make the circuit in chip that single-ion transient state SET or single-particle inversion SEU to occur,
Even with the reduction of integrated circuit dimensions, it may occur that multiple spot overturns MNU.The logical value that circuit can thus stored is turned over
Turn so that circuit produces functionality errors.Therefore in order that circuit is exercised correct function and added it is necessary to carry out radioresistance to circuit
Fixed meter.
Latch is conventional sequential logic device, so one important aspect of radiation tolerance design is exactly to latching
Device is reinforced.Conventional reinforcement means mainly includes two aspects of technique and design at present, and technique generally refers to domain level and reinforces,
The main of classics has triplication redundancy and DICE to design aspect at present（Dual-Interlocked storage Cell）But, it
Can only tolerate that single-point overturns, and triplication redundancy has larger area overhead, time delay and power consumption.
The content of the invention
Single-particle inversion and multiple spot upset can be tolerated it is an object of the invention to provide one kind, so that latch is preserved
The radiation hardening latch based on isomery duplication redundancy of correct logical value.
To achieve the above object, present invention employs following technical scheme：A kind of radioresistance based on isomery duplication redundancy
Reinforce latch, including the first memory cell, transmission unit, the second memory cell and C cell；First memory cell is by 4
, to composition, each pair transistor two NMOS tubes and a PMOS to being made up of for group transistor；The transmission unit is by a biography
Defeated door TG3, a phase inverter INV and a Schmidt trigger composition；Second memory cell is by 4 group transistors to group
Into, wherein two groups be two NMOS tubes, a PMOS, in addition two groups be two PMOSs, a NMOS tube；The C cell
It is made up of two PMOS transistors and two nmos pass transistors；First memory cell, transmission unit, the second memory cell
Signal input part connects input signal D, the signal output part of first memory cell and the first signal input part phase of C cell
Even, the signal output part of second memory cell is connected with the secondary signal input of C cell, the signal of the transmission unit
The signal output part of output termination C cell, the signal output part of C cell as radiation hardening latch output end.
4 group transistors that first memory cell is included are to being respectively the first group transistor to, the second group transistor
To, the 3rd group transistor pair and the 4th group transistor pair；First group transistor by M1 to being managed, N1 pipes and N12 pipes are constituted, M1
The source electrode of pipe meets VDD, and the grid of M1 pipes connects the source electrode of N12 pipes, and the drain electrode of M1 pipes is connected with the drain electrode of N1 pipes, and the source electrode of N1 pipes connects
The grid of GND, N1 pipe connects the drain electrode of N4 pipes, and the source electrode of N12 pipes connects the grid of M1 pipes, and the grid of N12 pipes connects CLK clock signals,
The drain electrode of N12 pipes is connected with the drain electrode of M2 pipes；Second group transistor by M2 to being managed, N2 pipes and N23 pipes are constituted, the source of M2 pipes
Pole meets VDD, and the grid of M2 pipes connects the source electrode of N23 pipes, and the drain electrode of M2 pipes is connected with the drain electrode of N2 pipes, and the source electrode of N2 pipes meets GND, N2
The source gate of pipe connects the drain electrode of N1 pipes, and the source electrode of N23 pipes connects the grid of M2 pipes, and the grid of N23 pipes connects CLK clock signals, N23
The drain electrode of pipe is connected with the drain electrode of M3 pipes；3rd group transistor by M3 to being managed, N3 pipes and N34 pipes are constituted, the source electrode of M3 pipes
VDD is met, the grid of M3 pipes connects the source electrode of N34 pipes, and the drain electrode of M3 pipes is connected with the drain electrode of N3 pipes, the source electrode of N3 pipes meets GND, N3 pipes
Grid connect the drain electrode of N2 pipes, the source electrode of N34 pipes connects the grid of M3 pipes, and the grid of N34 pipes connects CLK clock signals, the leakage of N34 pipes
Pole is connected with the drain electrode of M4 pipes；4th group transistor by M4 to being managed, N4 pipes and N41 pipes are constituted, and the source electrode of M4 pipes meets VDD,
The grid of M4 pipes connects the source electrode of N41 pipes, and the drain electrode of M4 pipes is connected with the drain electrode of N4 pipes, and the source electrode of N4 pipes meets GND, the grid of N4 pipes
Connect the drain electrode of N3 pipes, the source electrode of N41 pipes connects the grid of M4 pipes, the grid of N41 pipes connects CLK clock signals, the drain electrode of N41 pipes and
The drain electrode of M1 pipes is connected.
The Schmidt trigger of the transmission unit is managed by M9, M10 pipes, M11 pipes, N9 pipes, N10 pipes and N11 pipes are constituted, institute
The source electrode for stating M9 pipes meets VDD, and the drain electrode of M9 pipes is connected with the source electrode of M10 pipes, and the grid of M9 pipes connects the output of phase inverter INV, M10
The source electrode of pipe is connected with the drain electrode of M9 pipes, and the grid of M10 pipes connects the output of phase inverter INV, the source electrode of N9 pipes and the drain electrode of N10 pipes
It is connected, the grid of N9 pipes connects the output of phase inverter INV, and the drain electrode of N9 pipes is connected with the signal output part of C cell, the source of N10 pipes
Pole meets GND, and the grid of N10 pipes connects the output of phase inverter INV, and the drain electrode of N10 pipes is connected with the source electrode of N9, and the source electrode of M11 pipes connects
The grid of GND, M11 pipe is connected with the grid of N11 pipes, and the drain electrode of M11 pipes is connected with the drain electrode of M9 pipes, and the source electrode of N11 pipes connects
The grid of VDD, N11 pipe is connected with the grid of M11 pipes, and the drain electrode of N11 pipes is connected with the drain electrode of N10.
Second memory cell include 4 included group transistors to be respectively the 5th group transistor to, the 6th group it is brilliant
Body pipe is to, the 7th group transistor pair and the 8th group transistor pair；5th group transistor by M5 to being managed, N5 is managed and N34 pipe groups
Into, the source electrode of M5 pipes meets VDD, the grid of M5 pipes connects the drain electrode of M8 pipes, the drain electrode of M5 pipes is connected with the drain electrode of N5 pipes, N5 pipes
Source electrode meets GND, and the grid of N5 pipes is connected with the source electrode of N34 pipes, and the source electrode of N34 pipes is connected with the grid of N5 pipes, the grid of N34 pipes
CLK clock signals are connect, the drain electrode of N34 pipes connects the drain electrode of M6 pipes；6th group transistor by M6 to being managed, N6 is managed and M45 pipe groups
Into the source electrode of M6 pipes meets VDD, and the grid of M6 pipes is connected with the drain electrode of M5 pipes, and the drain electrode of M6 pipes is connected with the drain electrode of N6 pipes, N6 pipes
Source electrode meet GND, the grid of N6 pipes connects the drain electrode of M7 pipes, and the source electrode of M45 pipes is connected with the drain electrode of M6 pipes, and the grid of M45 pipes connects
CLKB clock signals, the drain electrode of M45 pipes is connected with the grid of M7 pipes；7th group transistor by M7 to being managed, N7 pipes and M56 are managed
Composition, the source electrode of M7 pipes meets VDD, and the grid of M7 pipes is connected with the drain electrode of M45 pipes, and the drain electrode of M7 pipes is connected with the drain electrode of N7 pipes,
The source electrode of N7 pipes meets GND, and the grid of N7 pipes is connected with the source electrode of N56 pipes, and the source electrode of N56 pipes is connected with the grid of N7 pipes, N56 pipes
Grid connect CLK clock signals, the drain electrode of N56 pipes is connected with the drain electrode of M8 pipes；8th group transistor by M8 to being managed, N8 pipes
Constituted with M63 pipes, the source electrode of M8 pipes meets VDD, and the grid of M8 pipes is connected with the drain electrode of M7 pipes, the drain electrode and the drain electrode of N8 pipes of M8 pipes
It is connected, the source electrode of N8 pipes meets GND, and the grid of N8 pipes is connected with the drain electrode of M5 pipes, and the source electrode of M63 pipes is connected with the drain electrode of M8 pipes,
The grid of M63 pipes connects CLKB clock signals, and the drain electrode of M63 pipes is connected with the grid of M5 pipes.
The C cell includes M11 pipes, M12 pipes, N11 pipes and N12 pipes, and the source electrode of M11 pipes meets VDD, the grid of M11 pipes with
The drain electrode that the drain electrode of M4 pipes is connected in node Q1, M11 pipe is connected with the source electrode of M12 pipes, the source electrode of M12 pipes and the drain electrode of M11 pipes
It is connected, the drain electrode that the grid of M12 pipes is connected in node Q2, M12 pipe with the drain electrode of M8 pipes meets the signal output part Q, N11 of C cell
The source electrode of pipe is connected with the drain electrode of N12 pipes, and the source gate of N11 pipes is connected in the source electrode of node Q2, N11 pipe with the drain electrode of M8 pipes
Drain electrode connects the signal output part of C cell, and the source electrode of N12 pipes meets GND, and the grid of N12 pipes is connected in node Q1 with the drain electrode of M4 pipes,
The drain electrode of N12 pipes is connected with the source electrode of N11 pipes.
The M1 pipes, M2 pipes, M3 are managed and M4 pipes are PMOS transistor, the N1 pipes, N2 are managed, N3 pipes, N4 pipes, N12 are managed,
N23 pipes, N34 pipes and N41 pipes are nmos pass transistor.
The M9 pipes, M10 pipes, M11 pipes are PMOS transistor, and the N9 pipes, N10 pipes, N11 pipes are NMOS crystal
Pipe.
The M5 pipes, M6 pipes, M7 pipes, M8 pipes, M45 pipes and M63 pipes are PMOS transistor, the N5 pipes, N6 pipes, N7
Pipe, N8 pipes, N34 pipes and N56 pipes are nmos pass transistor.
The M11 pipes, M12 pipes are PMOS transistor, and the N11 pipes, N12 pipes are nmos pass transistor
As shown from the above technical solution, the advantage of the invention is that：First, the present invention is due to having used by transmission gate, phase inverter
The transmission path constituted with Schmidt trigger, due to the SET filtering functions of Schmidt trigger so that latch is in transparent period
Filtering SET pulse；Second, all there is the first memory cell and the second memory cell that the present invention is used tolerance single-point and two point to turn over
The ability for turning, it is combined with C cell, latch is tolerated that single-point upset and multiple spot overturn, with good fault-tolerance
Energy；3rd, the present invention compares, and other can tolerate the ruggedized construction that multiple spot overturns, and transistor size is less, can reduce face
Product expense, power consumption and delay.
Brief description of the drawings
Fig. 1 is circuit theory diagrams of the invention；
Fig. 2 is the circuit theory diagrams of the first memory cell in Fig. 1；
Fig. 3 is the circuit theory diagrams of transmission unit in Fig. 1；
Fig. 4 is the circuit theory diagrams of the second memory cell in Fig. 1；
Fig. 5 is the circuit theory diagrams of C cell in Fig. 1.
Specific embodiment
As shown in figure 1, a kind of radiation hardening latch based on isomery duplication redundancy, including the first memory cell 1, biography
Defeated unit 2, the second memory cell 3 and C cell 4；First memory cell 1 by 4 group transistors to constituting, each pair transistor pair
It is made up of two NMOS tubes and a PMOS；The transmission unit 2 is by a transmission gate TG3, a phase inverter INV and one
Schmidt trigger is constituted；Second memory cell 3 by 4 group transistors to constituting, wherein two groups be two NMOS tubes, one
PMOS, two groups is two PMOSs, a NMOS tube in addition；The C cell 4 is by two PMOS transistors and two NMOS crystalline substances
Body pipe is constituted；First memory cell 1, transmission unit 2, the signal input part of the second memory cell 3 meet input signal D,
The signal output part of first memory cell 1 is connected with the first signal input part of C cell 4, second memory cell 3
Signal output part is connected with the secondary signal input of C cell 4, and the signal output of the transmission unit 2 terminates the letter of C cell 4
Number output end, the signal output part of C cell 4 as radiation hardening latch output end.
As shown in Fig. 24 group transistors that are included of first memory cell 1 to be respectively the first group transistor to,
Two group transistors are to, the 3rd group transistor pair and the 4th group transistor pair；First group transistor by M1 to being managed, N1 pipe and
N12 pipes are constituted, and the source electrode of M1 pipes meets VDD, and the grid of M1 pipes connects the source electrode of N12 pipes, and the drain electrode of M1 pipes is connected with the drain electrode of N1 pipes,
The source electrode of N1 pipes meets GND, and the grid of N1 pipes connects the drain electrode of N4 pipes, and the source electrode of N12 pipes connects the grid of M1 pipes, and the grid of N12 pipes connects
CLK clock signals, the drain electrode of N12 pipes is connected with the drain electrode of M2 pipes；Second group transistor by M2 to being managed, N2 pipes and N23 are managed
Composition, the source electrode of M2 pipes meets VDD, and the grid of M2 pipes connects the source electrode of N23 pipes, and the drain electrode of M2 pipes is connected with the drain electrode of N2 pipes, N2 pipes
Source electrode meet GND, the source gate of N2 pipes connects the drain electrode of N1 pipes, and the source electrode of N23 pipes connects the grid of M2 pipes, and the grid of N23 pipes connects
CLK clock signals, the drain electrode of N23 pipes is connected with the drain electrode of M3 pipes；3rd group transistor by M3 to being managed, N3 pipes and N34 are managed
Composition, the source electrode of M3 pipes meets VDD, and the grid of M3 pipes connects the source electrode of N34 pipes, and the drain electrode of M3 pipes is connected with the drain electrode of N3 pipes, N3 pipes
Source electrode meet GND, the grid of N3 pipes connects the drain electrode of N2 pipes, and the source electrode of N34 pipes connects the grid of M3 pipes, when the grid of N34 pipes meets CLK
Clock signal, the drain electrode of N34 pipes is connected with the drain electrode of M4 pipes；4th group transistor by M4 to being managed, N4 pipes and N41 pipes are constituted,
The source electrode of M4 pipes meets VDD, and the grid of M4 pipes connects the source electrode of N41 pipes, and the drain electrode of M4 pipes is connected with the drain electrode of N4 pipes, the source electrode of N4 pipes
GND is met, the grid of N4 pipes connects the drain electrode of N3 pipes, and the source electrode of N41 pipes connects the grid of M4 pipes, and the grid of N41 pipes connects CLK clocks letter
Number, the drain electrode of N41 pipes is connected with the drain electrode of M1 pipes.The M1 pipes, M2 pipes, M3 pipes and M4 pipes are PMOS transistor, the N1
Pipe, N2 pipes, N3 pipes, N4 pipes, N12 pipes, N23 pipes, N34 pipes and N41 pipes are nmos pass transistor.
As shown in figure 3, the Schmidt trigger of the transmission unit 2 by M9 manage, M10 pipe, M11 pipe, N9 pipe, N10 pipe and
N11 pipes are constituted, and the source electrode of the M9 pipes meets VDD, and the drain electrode of M9 pipes is connected with the source electrode of M10 pipes, and the grid of M9 pipes connects phase inverter
The output of INV, the source electrode of M10 pipes is connected with the drain electrode of M9 pipes, and the grid of M10 pipes connects the output of phase inverter INV, the source electrode of N9 pipes
Drain electrode with N10 pipes is connected, and the grid of N9 pipes connects the drain electrode of the output N9 pipes of phase inverter INV and the signal output part phase of C cell 4
Even, the source electrode of N10 pipes meets GND, and the grid of N10 pipes connects the output of phase inverter INV, and the drain electrode of N10 pipes is connected with the source electrode of N9,
The source electrode of M11 pipes meets GND, and the grid of M11 pipes is connected with the grid of N11 pipes, and the drain electrode of M11 pipes is connected with the drain electrode of M9 pipes, N11
The source electrode of pipe meets VDD, and the grid of N11 pipes is connected with the grid of M11 pipes, and the drain electrode of N11 pipes is connected with the drain electrode of N10.The M9
Pipe, M10 pipes, M11 pipes are PMOS transistor, and the N9 pipes, N10 pipes, N11 pipes are nmos pass transistor.
As shown in figure 4, second memory cell 3 includes 4 included group transistors to being respectively the 5th group transistor
To, the 6th group transistor to, the 7th group transistor pair and the 8th group transistor pair；5th group transistor by M5 to being managed, N5
Pipe and N34 pipes composition, the source electrode of M5 pipes meet VDD, the grid of M5 pipes connects the drain electrode of M8 pipes, the drain electrode and the drain electrode of N5 pipes of M5 pipes
It is connected, the source electrode of N5 pipes meets GND, and the grid of N5 pipes is connected with the source electrode of N34 pipes, and the source electrode of N34 pipes is connected with the grid of N5 pipes,
The grid of N34 pipes connects CLK clock signals, and the drain electrode of N34 pipes connects the drain electrode of M6 pipes；6th group transistor by M6 to being managed, N6
Pipe and M45 pipes composition, the source electrode of M6 pipes meet VDD, and the grid of M6 pipes is connected with the drain electrode of M5 pipes, the drain electrode and the leakage of N6 pipes of M6 pipes
Extremely it is connected, the source electrode of N6 pipes meets GND, and the grid of N6 pipes connects the drain electrode of M7 pipes, and the source electrode of M45 pipes is connected with the drain electrode of M6 pipes, M45
The grid of pipe connects CLKB clock signals, and the drain electrode of M45 pipes is connected with the grid of M7 pipes；7th group transistor to being managed by M7,
N7 is managed and M56 pipes composition, and the source electrode of M7 pipes meets VDD, and the grid of M7 pipes is connected with the drain electrode of M45 pipes, and the drain electrode of M7 pipes and N7 are managed
Drain electrode be connected, the source electrode of N7 pipes meets GND, and the grid of N7 pipes is connected with the source electrode of N56 pipes, the source electrode of N56 pipes and the grid of N7 pipes
Extremely it is connected, the grid of N56 pipes connects CLK clock signals, and the drain electrode of N56 pipes is connected with the drain electrode of M8 pipes；8th group transistor
To being managed by M8, N8 is managed and M63 pipes are constituted, and the source electrode of M8 pipes meets VDD, and the grid of M8 pipes is connected with the drain electrode of M7 pipes, the leakage of M8 pipes
Pole is connected with the drain electrode of N8 pipes, and the source electrode of N8 pipes meets GND, and the grid of N8 pipes is connected with the drain electrode of M5 pipes, the source electrode and M8 of M63 pipes
The drain electrode of pipe is connected, and the grid of M63 pipes connects CLKB clock signals, and the drain electrode of M63 pipes is connected with the grid of M5 pipes.The M5 pipes,
M6 pipes, M7 pipes, M8 pipes, M45 pipes and M63 pipes are PMOS transistor, the N5 pipes, N6 pipes, N7 pipes, N8 pipes, N34 pipes and N56
Pipe is nmos pass transistor.
As shown in figure 5, the C cell 4 includes M11 pipes, M12 pipes, N11 pipes and N12 pipes, the source electrode of M11 pipes meets VDD, M11
The drain electrode that the grid of pipe and the drain electrode of M4 pipes are connected in node Q1, M11 pipe is connected with the source electrode of M12 pipes, the source electrode of M12 pipes and
The drain electrode of M11 pipes is connected, and the drain electrode that the grid of M12 pipes is connected in node Q2, M12 pipe with the drain electrode of M8 pipes connects the signal of C cell 4
The source electrode of output end Q, N11 pipe is connected with the drain electrode of N12 pipes, and the source gate of N11 pipes is connected in node Q2 with the drain electrode of M8 pipes,
The source drain of N11 pipes connects the signal output part of C cell 4, and the source electrode of N12 pipes connects GND, the grid of N12 pipes and the drain electrode of M4 pipes
The drain electrode for being connected in node Q1, N12 pipe is connected with the source electrode of N11 pipes.The M11 pipes, M12 pipes are PMOS transistor, the N11
Pipe, N12 pipes are nmos pass transistor.
Below in conjunction with Fig. 1 to 5, the present invention is further illustrated.
When CLK is height, and CLKB is low, transmission gate TG1, transmission gate TG2, transmission gate TG3, transmission gate TG4 and transmission gate
TG5 is turned on, and latch is in transparent period, and the first memory cell 1, transmission unit 2, the second memory cell 3 are turned on, input signal D
By transmission gate TG3, phase inverter INV and Schmidt trigger, the output Q of latch is reached.Input signal D passes through transmission gate
TG1, transmission gate TG2 are respectively written into nodes X 0, X2, then using the node Q1 values of the first memory cell 1 as C cell 4 input.
Signal is respectively written into nodes X 3, X5 by input signal D by transmission gate TG4, transmission gate TG5, by the node of the second memory cell 3
The value of Q2 is input into all the way in addition as C cell 4, and the two-way input of C cell 4 is respectively Q1, Q2, is output as the output of latch
Q。
The analysis present invention when CLKB is low level, and CLK is high level, locks to the resistivity of single-ion transient state SET
Storage is in transparent period, only needs to consider the problem of SET this when, when input D has SET to produce, input signal D warps
Cross transmission gate TG3, phase inverter INV, Schmidt trigger, the SET pulse of generation can be filtered, due to the first memory cell and
Second memory cell has two point automatic recovery ability, so the SET pulse for producing can also be eliminated, is transmitted as such to output end
Q will not be influenceed by SET.
The analysis resistivity to single-particle inversion SEU of the invention, when CLKB is high level, and CLK is low level,
Latch is in the latch phase.Only the first memory cell 1 and transmission unit 2 are conductings, and the first memory cell 1 has 8 inside
Node is respectively X0, X1, X2, Q1, BL, CL, QL and AL, transmission unit 2 have 8 internal node respectively X3, X4, X5, Q2,
DL, DR, QL1 and QR.First memory cell 1 and the second memory cell 3 are improved on DICE architecture basics, all with single-point
Self-healing ability, so any one node occurs SEU in this 16 nodes, can realize self- recoverage.
The analysis present invention first considers the situation of two point upset to the resistivity of MNU, and one has 16 internal nodes.Point
Two class discussion：Respectively there is a node to overturn in the first situation, the first memory cell 1 and the second memory cell 3, because the
One memory cell 1 and the second memory cell 3 all can be self-healing single-point, so two point upset can be with self- recoverage；Second
Situation, has two nodes to occur have two nodes to overturn in upset or the second memory cell 3 in TDCIE modules 1.
For TDCIE modules 1,8 internal nodes are had, two groups can be classified as, X0, X1, X2 and Q1 are one group,
BL, CL, QL and AL are another set, choose 3 kinds of typical cases and analyze.When (X0, X1, X2, Q1) logical value for (0,1,0,
1) when, when (BL, CL, QL, AL) logical value is (1,0,1,0)：
（1）When it is 0 that X0 upsets are 1, X1 upsets, because CL remains as the conducting of 0, M2 pipes, it is 1, N1 that X1 can be made to revert to 1, Q1
Pipe is turned on, and X0 point logical values can be made to revert to 0, completes a self- recoverage process；
（2）When it is 0 that X0 upsets are 1, BL upsets, can turn on N2 pipes, the upset of X1 points logical value is 0, due to Q1 point logical values
It is the conducting of 1, N1 pipes so that X0 point logical values revert to 0, CL logical values for 0, M2 pipes are turned on so that X1 point logical values are reverted to
1, complete a self- recoverage process；
（3）When it is 0 that CL upsets are 1, QL upsets, the conducting of M3 pipes, it is 1 that can overturn X2 points logical value so that N4 pipes are turned on, Q1
Point logical value upset is 0, and due to AL for 0, M4 pipes are turned on, Q1 point logical values revert to 1, and due to X1 points logical value for 1, N3 is managed
Conducting so that X2 point logical values revert to 0, complete a self- recoverage process.
For the second memory cell 3,8 internal nodes are had, two groups can be classified as, X3, X4, X5 and Q2 are one
Group, DL, DR, QL1 and QR are another set, choose 3 kinds of typical cases and analyze.When (X3, X4, X5, Q2) logical value for (0,
1,0,1) when, when (DL, DR, QL1, QR) is (1,1,1,1)：
（1）When X3 upset for 1, X4 upset for 0 when, N8 pipes conducting, Q2 points logical value upset for 0, X5 points logical value be 0, M8
Pipe is turned on, and Q2 point logical values return to 1, DL logics for 1, N5 pipes are turned on by 0, and X3 point logical values revert to 0, and such M6 pipes are just led
Logical, X4 point logical values revert to 1, complete a self- recoverage process；
（2）When X4 by 1 upset for 0, DL by 1 upset for 0 when, X3 points are the conducting of 0, M6 pipes, and X4 point logical values return to 0 by 1, complete
Into a self- recoverage process；
（3）Work as QL1, when 1 is turned to 0, M5 pipes conducting, X3 point logical values are turned to 1, N8 pipes and turn on QR logical values by 0, and Q2 is patrolled
Collect value and be turned to 0 by 1, because DL is 1, N5 pipes turning on, X3 point logical values revert to 0, X5 points logical value for 0, M8 pipes are led by 1
Logical, Q2 point logical values return to 1 by 0, complete a self- recoverage process.
First memory cell 1 and the second memory cell 3 there is also can not self-healing situation, such as the first memory cell 1
Middle CL, AL overturn simultaneously when, the logical value of whole latch overturns.When the situation that can't stand two point upset, mistake
Logical value is delivered to C cell 4, and latch can be made to enter high-impedance state, and the logical value Q of circuit output is still unaffected.It is comprehensive with
Upper analysis, the present invention can be tolerance two point upset, and a few cases can not realize self- recoverage.
Because the first memory cell 1 and the second memory cell 3 all can be self-healing two point upset, when by particle bombardment
A node overturns in causing to have a unit in the first memory cell 1 and the second memory cell 3, in another unit
There are two nodes to overturn, or the first memory cell 1 and the second memory cell 3 have two nodes to overturn, at this moment
The correct logical value of circuit output, the so present invention can tolerate 3 points of upsets or 4 points of upsets to a certain extent.
Analysis can be seen that the present invention and can filter SET with reference to more than, tolerate single-particle inversion SEU, be turned over for two point
Turn, majority can realize self- recoverage, 3 points of upsets or 4 points of upsets, it is possible to achieve part self- recoverage.The present invention can be used for aviation
The highly reliable integrated circuit latches design of space industry, has great importance for lifting circuit stability.
Claims (9)
1. a kind of radiation hardening latch based on isomery duplication redundancy, it is characterised in that：Including the first memory cell（1）、
Transmission unit（2）, the second memory cell（3）And C cell（4）；First memory cell（1）By 4 group transistors to constituting, often
To transistor to being made up of two NMOS tubes and a PMOS；The transmission unit（2）By a transmission gate TG3, one it is anti-
Phase device INV and a Schmidt trigger composition；Second memory cell（3）By 4 group transistors to constituting, wherein two groups are
Two NMOS tubes, a PMOS, two groups is two PMOSs, a NMOS tube in addition；The C cell（4）By two PMOS
Transistor and two nmos pass transistor compositions；First memory cell（1）, transmission unit（2）, the second memory cell（3）'s
Signal input part meets input signal D, first memory cell（1）Signal output part and C cell（4）The first signal it is defeated
Enter end to be connected, second memory cell（3）Signal output part and C cell（4）Secondary signal input be connected, the biography
Defeated unit（2）Signal output termination C cell（4）Signal output part, C cell（4）Signal output part add as radioresistance
The output end of solid lock storage.
2. the radiation hardening latch based on isomery duplication redundancy according to claim 1, it is characterised in that：Described
One memory cell（1）Comprising 4 group transistors to be respectively the first group transistor to, the second group transistor to, the 3rd group it is brilliant
Body pipe pair and the 4th group transistor pair；First group transistor by M1 to being managed, N1 pipes and N12 pipes are constituted, and the source electrode of M1 pipes connects
The grid of VDD, M1 pipe connects the source electrode of N12 pipes, and the drain electrode of M1 pipes is connected with the drain electrode of N1 pipes, and the source electrode of N1 pipes meets GND, N1 pipes
Grid connects the drain electrode of N4 pipes, and the source electrode of N12 pipes connects the grid of M1 pipes, and the grid of N12 pipes connects CLK clock signals, the drain electrode of N12 pipes
Drain electrode with M2 pipes is connected；Second group transistor by M2 to being managed, N2 pipes and N23 pipes are constituted, and the source electrode of M2 pipes meets VDD, M2
The grid of pipe connects the source electrode of N23 pipes, and the drain electrode of M2 pipes is connected with the drain electrode of N2 pipes, and the source electrode of N2 pipes meets GND, the source electrode grid of N2 pipes
Pole connects the drain electrode of N1 pipes, and the source electrode of N23 pipes connects the grid of M2 pipes, and the grid of N23 pipes connects CLK clock signals, the drain electrode of N23 pipes and
The drain electrode of M3 pipes is connected；3rd group transistor by M3 to being managed, N3 pipes and N34 pipes are constituted, and the source electrode of M3 pipes meets VDD, M3 pipes
Grid connect the source electrode of N34 pipes, the drain electrode of M3 pipes is connected with the drain electrode of N3 pipes, and the source electrode of N3 pipes meets GND, and the grid of N3 pipes meets N2
The drain electrode of pipe, the source electrode of N34 pipes connects the grid of M3 pipes, and the grid of N34 pipes connects CLK clock signals, drain electrode and the M4 pipes of N34 pipes
Drain electrode is connected；4th group transistor by M4 to being managed, N4 pipes and N41 pipes are constituted, and the source electrode of M4 pipes meets VDD, the grid of M4 pipes
The source electrode of N41 pipes is connect, the drain electrode of M4 pipes is connected with the drain electrode of N4 pipes, and the source electrode of N4 pipes meets GND, and the grid of N4 pipes connects the leakage of N3 pipes
Pole, the source electrode of N41 pipes connects the grid of M4 pipes, and the grid of N41 pipes connects CLK clock signals, the drain electrode and the drain electrode of M1 pipes of N41 pipes
It is connected.
3. the radiation hardening latch based on isomery duplication redundancy according to claim 1, it is characterised in that：The biography
Defeated unit（2）Schmidt trigger by M9 pipe, M10 pipe, M11 pipe, N9 pipe, N10 pipe and N11 pipes constitute, the source of the M9 pipes
Pole meets VDD, and the drain electrode of M9 pipes is connected with the source electrode of M10 pipes, and the grid of M9 pipes connects the output of phase inverter INV, the source electrode of M10 pipes with
The drain electrode of M9 pipes is connected, and the grid of M10 pipes connects the output of phase inverter INV, and the source electrode of N9 pipes is connected with the drain electrode of N10 pipes, N9 pipes
Grid connect the output of phase inverter INV, the drain electrode of N9 pipes and C cell（4）Signal output part be connected, the source electrode of N10 pipes connects
The grid of GND, N10 pipe connects the output of phase inverter INV, and the drain electrode of N10 pipes is connected with the source electrode of N9, and the source electrode of M11 pipes meets GND,
The grid of M11 pipes is connected with the grid of N11 pipes, and the drain electrode of M11 pipes is connected with the drain electrode of M9 pipes, and the source electrode of N11 pipes meets VDD, N11
The grid of pipe is connected with the grid of M11 pipes, and the drain electrode of N11 pipes is connected with the drain electrode of N10.
4. the radiation hardening latch based on isomery duplication redundancy according to claim 1, it is characterised in that：Described
Two memory cell（3）Including 4 group transistors that are included to be respectively the 5th group transistor to, the 6th group transistor to, the 7th
Group transistor pair and the 8th group transistor pair；5th group transistor by M5 to being managed, N5 pipes and N34 pipes are constituted, the source of M5 pipes
Pole meets VDD, the grid of M5 pipes connects the drain electrode of M8 pipes, the drain electrode of M5 pipes is connected with the drain electrode of N5 pipes, and the source electrode of N5 pipes meets GND,
The grid of N5 pipes is connected with the source electrode of N34 pipes, and the source electrode of N34 pipes is connected with the grid of N5 pipes, and the grid of N34 pipes connects CLK clocks
Signal, the drain electrode of N34 pipes connects the drain electrode of M6 pipes；6th group transistor by M6 to being managed, N6 pipes and M45 pipes are constituted, M6 pipes
Source electrode meets VDD, and the grid of M6 pipes is connected with the drain electrode of M5 pipes, and the drain electrode of M6 pipes is connected with the drain electrode of N6 pipes, and the source electrode of N6 pipes connects
The grid of GND, N6 pipe connects the drain electrode of M7 pipes, and the source electrode of M45 pipes is connected with the drain electrode of M6 pipes, and the grid of M45 pipes connects CLKB clocks
Signal, the drain electrode of M45 pipes is connected with the grid of M7 pipes；7th group transistor by M7 to being managed, N7 pipes and M56 pipes are constituted, M7
The source electrode of pipe meets VDD, and the grid of M7 pipes is connected with the drain electrode of M45 pipes, and the drain electrode of M7 pipes is connected with the drain electrode of N7 pipes, the source of N7 pipes
Pole meets GND, and the grid of N7 pipes is connected with the source electrode of N56 pipes, and the source electrode of N56 pipes is connected with the grid of N7 pipes, and the grid of N56 pipes connects
CLK clock signals, the drain electrode of N56 pipes is connected with the drain electrode of M8 pipes；8th group transistor by M8 to being managed, N8 pipes and M63 are managed
Composition, the source electrode of M8 pipes meets VDD, and the grid of M8 pipes is connected with the drain electrode of M7 pipes, and the drain electrode of M8 pipes is connected with the drain electrode of N8 pipes, N8
The source electrode of pipe meets GND, and the grid of N8 pipes is connected with the drain electrode of M5 pipes, and the source electrode of M63 pipes is connected with the drain electrode of M8 pipes, M63 pipes
Grid connects CLKB clock signals, and the drain electrode of M63 pipes is connected with the grid of M5 pipes.
5. the radiation hardening latch based on isomery duplication redundancy according to claim 1, it is characterised in that：The C
Unit（4）Including M11 pipes, M12 pipes, N11 pipes and N12 pipes, the source electrode of M11 pipes connects VDD, the grid of M11 pipes and the drain electrode of M4 pipes
The drain electrode for being connected in node Q1, M11 pipe is connected with the source electrode of M12 pipes, and the source electrode of M12 pipes is connected with the drain electrode of M11 pipes, M12 pipes
The drain electrode of grid and M8 pipes be connected in the drain electrode of node Q2, M12 pipe and connect C cell（4）Signal output part Q, N11 pipe source electrode
Drain electrode with N12 pipes is connected, and the source drain that the source gate of N11 pipes is connected in node Q2, N11 pipe with the drain electrode of M8 pipes meets C
Unit（4）Signal output part, the source electrode of N12 pipes meets GND, and the grid of N12 pipes is connected in node Q1, N12 with the drain electrode of M4 pipes
The drain electrode of pipe is connected with the source electrode of N11 pipes.
6. the radiation hardening latch based on isomery duplication redundancy according to claim 2, it is characterised in that：The M1
Pipe, M2 pipes, M3 pipes and M4 pipes are PMOS transistor, the N1 pipes, N2 pipes, N3 pipes, N4 pipes, N12 pipes, N23 pipes, N34 pipes and
N41 pipes are nmos pass transistor.
7. the radiation hardening latch based on isomery duplication redundancy according to claim 3, it is characterised in that：The M9
Pipe, M10 pipes, M11 pipes are PMOS transistor, and the N9 pipes, N10 pipes, N11 pipes are nmos pass transistor.
8. the radiation hardening latch based on isomery duplication redundancy according to claim 4, it is characterised in that：The M5
Pipe, M6 pipes, M7 pipes, M8 pipes, M45 pipes and M63 pipes are PMOS transistor, the N5 pipes, N6 pipes, N7 pipes, N8 pipes, N34 pipes and
N56 pipes are nmos pass transistor.
9. the radiation hardening latch based on isomery duplication redundancy according to claim 5, it is characterised in that：It is described
M11 pipes, M12 pipes are PMOS transistor, and the N11 pipes, N12 pipes are nmos pass transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611072873.9A CN106788379B (en) | 2016-11-29 | 2016-11-29 | A kind of radiation hardening latch based on isomery duplication redundancy |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611072873.9A CN106788379B (en) | 2016-11-29 | 2016-11-29 | A kind of radiation hardening latch based on isomery duplication redundancy |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106788379A true CN106788379A (en) | 2017-05-31 |
| CN106788379B CN106788379B (en) | 2019-10-01 |
Family
ID=58904452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611072873.9A Expired - Fee Related CN106788379B (en) | 2016-11-29 | 2016-11-29 | A kind of radiation hardening latch based on isomery duplication redundancy |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106788379B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108134598A (en) * | 2018-01-16 | 2018-06-08 | 安徽理工大学 | Symmetrical radioresistance latch in high-frequency circuit |
| CN108134597A (en) * | 2018-01-08 | 2018-06-08 | 安徽大学 | A kind of completely immune latch of three internal nodes overturning |
| CN108233894A (en) * | 2018-01-24 | 2018-06-29 | 合肥工业大学 | A kind of low-power consumption dual-edge trigger based on duplication redundancy |
| CN108449071A (en) * | 2018-03-28 | 2018-08-24 | 上海华虹宏力半导体制造有限公司 | Resist the latch of two nodes overturning |
| CN109150138A (en) * | 2018-08-20 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | latch |
| CN109586704A (en) * | 2018-11-26 | 2019-04-05 | 中北大学 | Flouride-resistani acid phesphatase D-latch based on double interlocking structure |
| CN109687850A (en) * | 2018-12-19 | 2019-04-26 | 安徽大学 | A kind of latch that any three nodes overturning is tolerated completely |
| CN110572146A (en) * | 2019-08-29 | 2019-12-13 | 安徽大学 | latch capable of tolerating any three-node turnover and filtering transient pulse |
| CN111988030A (en) * | 2020-08-24 | 2020-11-24 | 合肥工业大学 | Single-particle three-point overturning reinforced latch |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070216464A1 (en) * | 2006-03-01 | 2007-09-20 | Stmicroelectronics Sa | Circuit for distributing an initial signal with a tree structure, protected against logic random events |
| CN103326711A (en) * | 2013-06-17 | 2013-09-25 | 天津大学 | Anti-radiation hardening latch based on TMR and DICE |
| CN105577161A (en) * | 2015-12-21 | 2016-05-11 | 合肥工业大学 | Single particle resistance multi-node overturning reinforcement latch register based on dual modular redundancy |
| CN105871366A (en) * | 2016-04-05 | 2016-08-17 | 河海大学常州校区 | Subthreshold-to-super-threshold CMOS (Complementary Metal Oxide Semiconductor) level conversion circuit capable of resisting single event effect |
-
2016
- 2016-11-29 CN CN201611072873.9A patent/CN106788379B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070216464A1 (en) * | 2006-03-01 | 2007-09-20 | Stmicroelectronics Sa | Circuit for distributing an initial signal with a tree structure, protected against logic random events |
| CN103326711A (en) * | 2013-06-17 | 2013-09-25 | 天津大学 | Anti-radiation hardening latch based on TMR and DICE |
| CN105577161A (en) * | 2015-12-21 | 2016-05-11 | 合肥工业大学 | Single particle resistance multi-node overturning reinforcement latch register based on dual modular redundancy |
| CN105871366A (en) * | 2016-04-05 | 2016-08-17 | 河海大学常州校区 | Subthreshold-to-super-threshold CMOS (Complementary Metal Oxide Semiconductor) level conversion circuit capable of resisting single event effect |
Non-Patent Citations (2)
| Title |
|---|
| H.-B. WANG: "An SEU-Tolerant DICE Latch Design with Feedback Transistors", 《 IEEE TRANSACTIONS ON NUCLEAR SCIENCE 》 * |
| KATERINA KATSAROU: "Double node charge sharing SEU tolerant latch design", 《2014 IEEE 20TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM》 * |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108134597A (en) * | 2018-01-08 | 2018-06-08 | 安徽大学 | A kind of completely immune latch of three internal nodes overturning |
| CN108134597B (en) * | 2018-01-08 | 2021-05-25 | 安徽大学 | Latch with three internal nodes completely immune in overturning |
| CN108134598B (en) * | 2018-01-16 | 2021-02-09 | 安徽理工大学 | Symmetrical radiation-resistant latch in high-frequency circuit |
| CN108134598A (en) * | 2018-01-16 | 2018-06-08 | 安徽理工大学 | Symmetrical radioresistance latch in high-frequency circuit |
| CN108233894A (en) * | 2018-01-24 | 2018-06-29 | 合肥工业大学 | A kind of low-power consumption dual-edge trigger based on duplication redundancy |
| CN108449071A (en) * | 2018-03-28 | 2018-08-24 | 上海华虹宏力半导体制造有限公司 | Resist the latch of two nodes overturning |
| CN109150138A (en) * | 2018-08-20 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | latch |
| CN109586704A (en) * | 2018-11-26 | 2019-04-05 | 中北大学 | Flouride-resistani acid phesphatase D-latch based on double interlocking structure |
| CN109687850A (en) * | 2018-12-19 | 2019-04-26 | 安徽大学 | A kind of latch that any three nodes overturning is tolerated completely |
| CN109687850B (en) * | 2018-12-19 | 2022-09-23 | 安徽大学 | Latch completely tolerating any three-node overturning |
| CN110572146A (en) * | 2019-08-29 | 2019-12-13 | 安徽大学 | latch capable of tolerating any three-node turnover and filtering transient pulse |
| CN110572146B (en) * | 2019-08-29 | 2022-10-14 | 安徽大学 | Latch capable of tolerating any three-node turnover and filtering transient pulse |
| CN111988030A (en) * | 2020-08-24 | 2020-11-24 | 合肥工业大学 | Single-particle three-point overturning reinforced latch |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106788379B (en) | 2019-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106788379B (en) | A kind of radiation hardening latch based on isomery duplication redundancy | |
| US7236001B2 (en) | Redundancy circuits hardened against single event upsets | |
| CN108011628A (en) | A kind of latch of three node of tolerable upset | |
| CN104202037A (en) | Single event radiation effect resistant reinforced latch circuit | |
| CN109687850B (en) | Latch completely tolerating any three-node overturning | |
| CN103326711B (en) | Based on the radiation hardening latch of triplication redundancy and DICE | |
| CN103633990B (en) | A kind of anti-single particle upset and the adjustable latch of transient effect time delay | |
| EP3439179A1 (en) | Clock driving circuit resistant to single-event transient | |
| CN108134597A (en) | A kind of completely immune latch of three internal nodes overturning | |
| CN104852722A (en) | Self-recovery latch register for preventing single event upset | |
| CN105897223A (en) | D trigger resistant to single event upset | |
| CN105577160A (en) | Self-recovery single particle resistance latch register structure based on time-delay unit | |
| CN104426532A (en) | Filtered Radiation Hardened Flip Flop With Reduced Power Consumption | |
| CN103957001A (en) | Latch capable of resisting dual-node upset | |
| Devarapalli et al. | SEU-hardened dual data rate flip-flop using C-elements | |
| CN109547006B (en) | Anti-radiation D latch | |
| CN106656149A (en) | Single event upset on-line self-recovery latch with high performance and low overhead | |
| CN102082568A (en) | Anti-single event transient circuit | |
| CN109361387A (en) | A kind of low cost triplication redundancy latch | |
| CN103546145B (en) | Single-event transient pulse resistant CMOS circuit | |
| CN108199698A (en) | A kind of doubleclocking anti-single particle latch | |
| CN204993301U (en) | Time domain of binode upset can be resisted and latch is consolidated | |
| CN111988030A (en) | Single-particle three-point overturning reinforced latch | |
| CN103475359B (en) | Single-event transient pulse resistant CMOS circuit | |
| CN103888099B (en) | A kind of anti-single particle transient state redundancy filter circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20191001 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |