CN106449653B - A kind of display base plate and preparation method thereof, display panel, display device - Google Patents
A kind of display base plate and preparation method thereof, display panel, display device Download PDFInfo
- Publication number
- CN106449653B CN106449653B CN201610873678.XA CN201610873678A CN106449653B CN 106449653 B CN106449653 B CN 106449653B CN 201610873678 A CN201610873678 A CN 201610873678A CN 106449653 B CN106449653 B CN 106449653B
- Authority
- CN
- China
- Prior art keywords
- oxide
- low
- display
- drain electrode
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229920005591 polysilicon Polymers 0.000 claims description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 28
- 239000010703 silicon Substances 0.000 claims description 28
- 238000001259 photo etching Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 239000003292 glue Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 150000002927 oxygen compounds Chemical class 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention provides a kind of display base plate and preparation method thereof, display panel, display device, belong to field of display technology, can solve the problems, such as that existing display device has limitation because low-temperature polycrystalline silicon transistor or oxide transistor is used alone in practical applications.Display base plate of the invention, the display base plate includes substrate and low-temperature polycrystalline silicon transistor and oxide transistor above substrate, display area and the neighboring area around the display area are provided on the substrate, the low-temperature polycrystalline silicon transistor is located in the neighboring area, and the oxide transistor is located in the display area.
Description
Technical field
The invention belongs to field of display technology, and in particular to a kind of display base plate and preparation method thereof, display panel, display
Device.
Background technique
Currently, basic industry of the display panel as electronics industry, technology are developed and are reformed continuous, wherein oxygen
Compound technology and low-temperature polysilicon silicon technology the advantages of its own because being widely used.Specifically, low-temperature polycrystalline silicon transistor is excellent
Point is to can be used for making metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor, MOS) device, oxide crystalline substance
The advantages of body pipe, is it with lesser leakage current.
Although having the above advantages, oxide technique and low-temperature polysilicon silicon technology also because of its own the shortcomings that, in reality
Application in be restricted, specifically, the leakage current of low-temperature polycrystalline silicon transistor is excessive, and oxide transistor is more difficult is used for
Prepare MOS device.
Therefore, the display device of low-temperature polysilicon silicon technology is either used, or uses the display device of oxide technique,
All there is very big problem in practical applications in it.
Summary of the invention
The present invention is directed at least solve one of the technical problems existing in the prior art, proposes a kind of while there is oxidation
Object transistor and the display base plate of low-temperature polycrystalline silicon transistor and preparation method thereof, display panel, display device.
Solving technical solution used by present invention problem is a kind of display base plate, and the display base plate includes substrate
Low-temperature polycrystalline silicon transistor and oxide transistor with being located above substrate, are provided with display area on the substrate and are located at
Neighboring area around the display area,
The low-temperature polycrystalline silicon transistor is located in the neighboring area, and the oxide transistor is located at the viewing area
In domain.
Wherein, the display base plate further include: the first insulating layer and second insulating layer, first insulating layer and described
The first via hole and the second via hole are provided in two insulating layers；
The low-temperature polycrystalline silicon transistor includes: low-temperature polysilicon silicon active layer, first grid, the first source electrode and the first leakage
Pole, part first source electrode are located in first via hole, and part first drain electrode is located in second via hole, described
First insulating layer is provided between first grid and the low-temperature polysilicon silicon active layer；
The oxide transistor includes: second grid, the second source electrode, the second drain electrode and oxide active layer, and described the
The second insulating layer, second source electrode and the second drain electrode are provided between two grids and second source electrode, the second drain electrode
It is connect with the oxide active layer.
Wherein, the display base plate further include: pixel electrode；
The pixel electrode and second drain electrode connect.
As another technical solution, the present invention also provides a kind of preparation methods of display base plate, comprising:
It is rectangular at low-temperature polycrystalline silicon transistor and oxide transistor on substrate；
Display area and the neighboring area around the display area, the low-temperature polysilicon are provided on the substrate
Silicon transistor is located in the neighboring area, and the oxide transistor is located in the display area.
Wherein, the low-temperature polycrystalline silicon transistor includes: low-temperature polysilicon silicon active layer, first grid, the first source electrode and
One drain electrode；The oxide transistor includes: second grid, the second source electrode, the second drain electrode and oxide active layer；
Formation low-temperature polycrystalline silicon transistor and the oxide transistor over the substrate include:
Low-temperature polysilicon silicon active layer is formed on the substrate；
The first insulating layer is deposited on the low-temperature polysilicon silicon active layer；
First grid and second grid are formed on the first insulating layer；
Deposit second insulating layer on the first grid and the second grid, and to first insulating layer and described
Second insulating layer is patterned technique, to form the first via hole and second in first insulating layer and the second insulating layer
Via hole；
The first source electrode, the first drain electrode, the second source electrode and the second drain electrode, part described the are formed on the second insulating layer
One source electrode is located in first via hole, and part first drain electrode is located in second via hole；
Oxide active layer is formed on second source electrode and the second drain electrode.
Wherein, pixel electrode is also formed while forming oxide active layer on second source-drain electrode；
It is described on second source-drain electrode formed oxide active layer while also formed pixel electrode include:
In second source electrode and the upper deposited oxide layer of the second drain electrode and photoresist layer, the photoresist layer is exposed
Light forms the photoetching offset plate figure after exposure, and the photoetching offset plate figure after the exposure includes complete exposure photo-etching glue pattern, part exposure
Light photoetching offset plate figure and unexposed photoresist figure；
Develop to the photoetching offset plate figure after exposure, removes the complete exposure photo-etching glue pattern to expose part oxygen
Compound layer；
The portions of oxide layer exposed is performed etching；
Using cineration technics, the Partial exposure photoetching offset plate figure is removed；
The oxide skin(coating) corresponding to the Partial exposure photoetching offset plate figure carries out conductor chemical industry skill, to form pixel electricity
Pole；
The remaining unexposed photoresist figure after removal cineration technics.
As another technical solution, the present invention also provides a kind of display panels, including display described in above-mentioned any one
Substrate.
As another technical solution, the present invention also provides a kind of display devices, including above-mentioned display panel.
Display base plate of the invention and preparation method thereof, display panel, in display device, the display base plate include substrate and
Low-temperature polycrystalline silicon transistor and oxide transistor above substrate are provided with display area on substrate and are located at viewing area
Neighboring area around domain, low-temperature polycrystalline silicon transistor are located in neighboring area, and oxide transistor is located in display area, lead to
It crosses low-temperature polycrystalline silicon transistor and oxide transistor while being arranged in display base plate, oxide crystal can either be passed through
Pipe effectively reduces the electric energy consume that pixel electrode in display area shows the deviation and display device of gray scale during display；
Simultaneously, additionally it is possible to the driving by the good electric performance stablity of low-temperature polycrystalline silicon transistor, for neighboring area；With this, energy
It is enough effectively to promote properties of product, improve product competitiveness.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the display base plate of the embodiment of the present invention 1；
Fig. 2 is the structural schematic diagram of step S1 in the preparation method of the display base plate of the embodiment of the present invention 2；
Fig. 3 is the structural schematic diagram of step S2 in the preparation method of the display base plate of the embodiment of the present invention 2；
Fig. 4 is the structural schematic diagram of step S3 in the preparation method of the display base plate of the embodiment of the present invention 2；
Fig. 5 is the structural schematic diagram of step S4 in the preparation method of the display base plate of the embodiment of the present invention 2；
Fig. 6 is the structural schematic diagram of step S5 in the preparation method of the display base plate of the embodiment of the present invention 2；
Fig. 7 is the structural schematic diagram of step S6 in the preparation method of the display base plate of the embodiment of the present invention 2；
Fig. 8 is the structural schematic diagram of step S71 in the preparation method of the display base plate of the embodiment of the present invention 2；
Fig. 9 is the structural schematic diagram of step S72 in the preparation method of the display base plate of the embodiment of the present invention 2；
Figure 10 is the structural schematic diagram of step S73 in the preparation method of the display base plate of the embodiment of the present invention 2；
Figure 11 is the structural schematic diagram of step S74 in the preparation method of the display base plate of the embodiment of the present invention 2；
Figure 12 is the structural schematic diagram of step S75 in the preparation method of the display base plate of the embodiment of the present invention 2；
Wherein, appended drawing reference are as follows: A, display area；B, neighboring area；1, substrate；2, low-temperature polycrystalline silicon transistor；21, low
Warm polysilicon active layer；22, first grid；23, the first source electrode；24, the first drain electrode；3, oxide transistor；31, second gate
Pole；32, the second source electrode；33, the second drain electrode；34, oxide active layer；4, the first insulating layer；41, the first via hole；42, the second mistake
Hole；5, second insulating layer；6, pixel electrode；7, oxide skin(coating)；10, complete exposure photo-etching glue pattern；11, Partial exposure photoresist
Figure；12, unexposed photoresist figure；.
Specific embodiment
Technical solution in order to enable those skilled in the art to better understand the present invention, with reference to the accompanying drawing and specific embodiment party
Present invention is further described in detail for formula.
Embodiment 1:
Fig. 1 is please referred to, the present embodiment provides a kind of display base plate, display base plate includes substrate 1 and above substrate 1
Low-temperature polycrystalline silicon transistor 2 and oxide transistor 3 are provided with display area A on substrate 1 and around the A of display area
Neighboring area B, low-temperature polycrystalline silicon transistor 2 are located in the B of neighboring area, and oxide transistor 3 is located in the A of display area.
From figure 1 it appears that oxide transistor 3 is located in the A of display area, why so set, being due to oxygen
Compound transistor 3 has lesser leakage current, during display, can effectively promote display picture quality and reduce display dress
The electric energy consume set, therefore, is disposed in the A of display area；And low-temperature polycrystalline silicon transistor 2 is arranged in neighboring area B
It is interior, it is since during display, the leakage current that low-temperature polycrystalline silicon transistor 2 generates is larger, but because it is with good electrical property
Stabilizability can be used for the driving of neighboring area B.
Low-temperature polycrystalline silicon transistor 2 includes: low-temperature polysilicon silicon active layer 21, first grid 22, the first source electrode 23 and first
Drain electrode 24, the first source electrode of part 23 is located in the first via hole 41, and the drain electrode of part first 24 is located in the second via hole 42, first grid
The first insulating layer 4 is provided between 22 and low-temperature polysilicon silicon active layer 21.
Wherein, display base plate further include: the first insulating layer 4 and second insulating layer 5, the first insulating layer 4 and second insulating layer 5
In be provided with the first via hole 41 and the second via hole 42.
From figure 1 it appears that being provided with the first via hole 41 and the second via hole in the first insulating layer 4 and second insulating layer 5
42, the first via hole 41 and the second via hole 42 respectively expose part low-temperature polysilicon silicon active layer 21.
From figure 1 it appears that low-temperature polysilicon silicon active layer 21 is located on substrate 1；First grid 22 and low temperature polycrystalline silicon
It is provided with the first insulating layer 4 between active layer 21, first grid 22 and low-temperature polysilicon silicon active layer 21 are separated, avoids short
Road；A part of first source electrode 23 is located in the first via hole 41, and another part of the first source electrode 23 is located in second insulating layer 5,
Therefore, the first source electrode 23 is connect by the first via hole 41 with low-temperature polysilicon silicon active layer 21；A part of first drain electrode 24 is located at
In second via hole 42, another part of the first drain electrode 24 is located in second insulating layer 5, and therefore, the first drain electrode 24 passes through the second mistake
Hole 42 is connect with low-temperature polysilicon silicon active layer 21.
Oxide transistor 3 includes: second grid 31, the second source electrode 32, second drain electrode 33 and oxide active layer 34, the
Second insulating layer 5 is provided between two grids 31 and the second source electrode 32, second drain electrode 33, the second source electrode 32 and the second drain electrode 33 are
It is connect with oxide active layer 34.
From figure 1 it appears that second grid 31 is located on the first insulating layer 4；Second source electrode 32 and the second drain electrode 33
In in second insulating layer 5, it is not connected between the second source electrode 32 and the second drain electrode 33, second insulating layer 5 is used for the second source electrode 32
It is separated with the second drain electrode 33 with second grid 31, to avoid that short circuit occurs；Oxide active layer 34 also is located at second insulating layer 5
On, the second source electrode of part 32 is located in oxide active layer 34, and the drain electrode of part second 33 is located in oxide active layer 34.
Wherein, display base plate further include: pixel electrode 6；Pixel electrode 6 is connect with the second drain electrode 33.
Shown in Fig. 1, display base plate further includes having pixel electrode 6, and a part of pixel electrode 6 is located at the second drain electrode 33
On, another part of pixel electrode 6 is located in second insulating layer 5.
The display base plate of the present embodiment, low-temperature polycrystalline silicon transistor 2 are located in the B of neighboring area, and oxide transistor 3 is located at
In the A of display area, by being arranged low-temperature polycrystalline silicon transistor and oxide transistor in display base plate simultaneously, it can either lead to
Peroxide crystal pipe effectively reduces deviation and display dress that pixel electrode in display area shows gray scale during display
The electric energy consume set；Simultaneously, additionally it is possible to by the good electric performance stablity of low-temperature polycrystalline silicon transistor, for neighboring area
Driving；With this, properties of product can be effectively promoted, improve product competitiveness.
Embodiment 2:
Referring to figure 2. to Figure 12, the present embodiment provides a kind of preparation methods of display base plate, comprising:
Step S0 forms low-temperature polycrystalline silicon transistor 2 and oxide transistor 3 above substrate 1；1 is provided on substrate
Display area A and the neighboring area around the A of display area, low-temperature polycrystalline silicon transistor 2 are located in the B of neighboring area, oxidation
Object transistor 3 is located in the A of display area.
Wherein, low-temperature polycrystalline silicon transistor 2 includes: low-temperature polysilicon silicon active layer 21, first grid 22,23 and of the first source electrode
First drain electrode 24；Oxide transistor 3 includes: second grid 31, the second source electrode 32, second drain electrode 33 and oxide active layer
34。
In the present embodiment, substrate 1 can be by the other materials system such as glass or polyethylene terephthalate (PET)
At details are not described herein.
Step S0 includes:
As shown in Fig. 2, step S1, forms low-temperature polysilicon silicon active layer 21 on substrate 1.
Specifically, one layer a-Si layers of monocrystalline silicon are deposited on substrate 1, using quasi-molecule laser annealing method (Excimer
Laser Annealing, ELA) laser crystallization mode, using certain energy excimer laser to a-Si layers of monocrystalline silicon carry out
Laser emission, making the chemical conversion of a-Si layer crystal is p-Si layers；Then, to be patterned technique to p-Si layers active to form low temperature polycrystalline silicon
Layer 21.Wherein, patterning processes may include the techniques such as photoresist coating, exposure, development, etching and photoresist lift off.
As shown in figure 3, step S2, deposits the first insulating layer 4 on low-temperature polysilicon silicon active layer 21.
As shown in figure 4, step S3, forms first grid 22 and second grid 31 on the first insulating layer 4.
Specifically, the deposition of gate material layer on the first insulating layer 4 is patterned technique to gate material layers to form
One grid 22 and second grid 31.Wherein, patterning processes may include photoresist coating, exposure, development, etching and photoresist lift off
Etc. techniques.
As shown in figure 5, step S4, deposits second insulating layer 5, and absolutely to first on first grid 22 and second grid 31
Edge layer 4 and second insulating layer 5 are patterned technique, to form 41 He of the first via hole in the first insulating layer 4 and second insulating layer 5
Second via hole 42.
Specifically, second insulating layer 5 is deposited on first grid 22 and second grid 31, and structure is carried out to second insulating layer 5
Figure technique is to form the first via hole 41 and the second via hole 42.Wherein, patterning processes may include photoresist coating, exposure, development, carve
The techniques such as erosion and photoresist lift off.
In the present embodiment, SiN can be used in the first insulating layer 4 and second insulating layer 5x、SiO2Or the insulating materials system such as resin
At details are not described herein.
As shown in fig. 6, step S5, forms the first source electrode 23, first the 24, second source electrode 32 of drain electrode in second insulating layer 5
With the second drain electrode 33, the first source electrode of part 23 is located in the first via hole 41, and the drain electrode of part first 24 is located in the second via hole 42.
Specifically, source and drain material layer is deposited in second insulating layer 5, and technique is patterned to source and drain material layer to form the
One source electrode 23, first drain electrode the 24, second source electrode 32 and the second drain electrode 33.Wherein, patterning processes may include photoresist coating, expose
The techniques such as light, development, etching and photoresist lift off.
Step S6 forms oxide active layer 34 and pixel electrode 6 on the second source electrode 32 and the second drain electrode 33.
In the present embodiment, oxide used by oxide skin(coating) is indium gallium zinc oxide (IGZO) or indium tin zinc oxide
(ITZO) etc. oxide semiconductor materials, details are not described herein.
Step S6 includes:
As shown in fig. 7, step S61, deposited oxide layer 7 and photoresist layer on the second source electrode 32 and the second drain electrode 33,
The photoetching offset plate figure being exposed after forming exposure to photoresist layer, the photoetching offset plate figure after exposure includes complete exposure photo-etching glue
Figure 10, Partial exposure photoetching offset plate figure 11 and unexposed photoresist figure 12.
As shown in figure 8, step S62, develops to the photoetching offset plate figure after exposure, complete exposure photo-etching glue pattern is removed
10, to expose portions of oxide layer 7.Meanwhile retaining unexposed photoresist figure 12 and Partial exposure photoetching offset plate figure 11.
As shown in figure 9, step S63, performs etching the portions of oxide layer 7 exposed.
As shown in Figure 10, step S64 removes Partial exposure photoetching offset plate figure 11 using cineration technics.
Since step S61 is exposed using intermediate tone mask plate or grayscale mask plate, so that Partial exposure photoresist figure
The thickness of shape 11 is less than the thickness of unexposed photoresist figure 12, therefore, removes Partial exposure photoresist figure by cineration technics
When shape 11, the thickness of unexposed photoresist figure 12 can also reduce therewith, but not be removed completely.
As shown in figure 11, step S65 carries out conductor chemical industry to the corresponding oxide skin(coating) 7 of Partial exposure photoetching offset plate figure 11
Skill, to form pixel electrode 6.
As shown in figure 12, step S66 removes remaining unexposed photoresist figure 12 after cineration technics, to form oxidation
Object active layer 34.
The preparation method of the display base plate of the present embodiment is used to prepare the display base plate of embodiment 1, by by low-temperature polysilicon
Silicon transistor and oxide transistor are arranged in display base plate simultaneously, can either be by oxide transistor, in display process
In, effectively reduce the electric energy consume that pixel electrode in display area shows the deviation and display device of gray scale；Simultaneously, additionally it is possible to logical
Cross the good electric performance stablity of low-temperature polycrystalline silicon transistor, the driving for neighboring area；With this, product can be effectively promoted
Performance improves product competitiveness.
Embodiment 3:
The present embodiment provides a kind of display panel, the display base plate including embodiment 1.
The display panel of the present embodiment, the display base plate including embodiment 1, by by low-temperature polycrystalline silicon transistor and oxidation
Object transistor is arranged in display base plate simultaneously, can either effectively reduce display by oxide transistor, during display
Pixel electrode shows the electric energy consume of the deviation and display device of gray scale in region；Simultaneously, additionally it is possible to pass through low-temperature polysilicon silicon wafer
The good electric performance stablity of body pipe, the driving for neighboring area；With this, properties of product can be effectively promoted, improve product
Competitiveness.
Embodiment 4:
Present embodiments provide a kind of display device comprising the display panel of embodiment 3.Display device can be with are as follows: liquid
LCD panel, Electronic Paper, mobile phone, tablet computer, television set, display, laptop, Digital Frame, navigator etc. are appointed
What products or components having a display function.
The display device of the present embodiment, the display panel including embodiment 3, by by low-temperature polycrystalline silicon transistor and oxidation
Object transistor is arranged in display base plate simultaneously, can either effectively reduce display by oxide transistor, during display
Pixel electrode shows the electric energy consume of the deviation and display device of gray scale in region；Simultaneously, additionally it is possible to pass through low-temperature polysilicon silicon wafer
The good electric performance stablity of body pipe, the driving for neighboring area；With this, properties of product can be effectively promoted, improve product
Competitiveness.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, essence of the invention is not being departed from
In the case where mind and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (6)
1. a kind of display base plate, which is characterized in that the display base plate includes substrate and the low temperature polycrystalline silicon above substrate
Transistor and oxide transistor are provided with display area and the peripheral region around the display area on the substrate
Domain,
The low-temperature polycrystalline silicon transistor is located in the neighboring area, and the oxide transistor is located at the display area
It is interior；
The display base plate further include: second insulating layer and pixel electrode, the oxide transistor include: second grid,
Two source electrodes, the second drain electrode and oxide active layer, are arranged between the second grid and second source electrode, the second drain electrode
Second insulating layer is stated, second source electrode and the second drain electrode are connect with the oxide active layer, the pixel electrode and institute
State the second drain electrode connection, the oxide active layer and pixel electrode same layer setting.
2. display base plate according to claim 1, which is characterized in that the display base plate further include: the first insulating layer, institute
It states in the first insulating layer and the second insulating layer and is provided with the first via hole and the second via hole；
The low-temperature polycrystalline silicon transistor includes: low-temperature polysilicon silicon active layer, first grid, the first source electrode and the first drain electrode, portion
First source electrode is divided to be located in first via hole, part first drain electrode is located in second via hole, and described first
First insulating layer is provided between grid and the low-temperature polysilicon silicon active layer.
3. a kind of preparation method of display base plate characterized by comprising
It is rectangular at low-temperature polycrystalline silicon transistor and oxide transistor on substrate；
Display area and the neighboring area around the display area, the low-temperature polysilicon silicon wafer are provided on the substrate
Body pipe is located in the neighboring area, and the oxide transistor is located in the display area；
The low-temperature polycrystalline silicon transistor includes: low-temperature polysilicon silicon active layer, first grid, the first source electrode and the first drain electrode；Institute
Stating oxide transistor includes: second grid, the second source electrode, the second drain electrode and oxide active layer；
Formation low-temperature polycrystalline silicon transistor and the oxide transistor over the substrate include:
Low-temperature polysilicon silicon active layer is formed on the substrate；
The first insulating layer is deposited on the low-temperature polysilicon silicon active layer；
First grid and second grid are formed on the first insulating layer；
Second insulating layer is deposited on the first grid and the second grid, and to first insulating layer and described second
Insulating layer is patterned technique, to form the first via hole and the second mistake in first insulating layer and the second insulating layer
Hole；
The first source electrode, the first drain electrode, the second source electrode and the second drain electrode, part first source are formed on the second insulating layer
Pole is located in first via hole, and part first drain electrode is located in second via hole；
Oxide active layer is formed on second source electrode and the second drain electrode；
Also form pixel electrode while forming oxide active layer on second source-drain electrode, the pixel electrode with it is described
Second drain electrode connection, the oxide active layer and the pixel electrode are formed by the same patterning processes.
4. the preparation method of display base plate according to claim 3, which is characterized in that
It is described on second source-drain electrode formed oxide active layer while also formed pixel electrode include:
In second source electrode and the upper deposited oxide layer of the second drain electrode and photoresist layer, shape is exposed to the photoresist layer
At the photoetching offset plate figure after exposure, the photoetching offset plate figure after the exposure includes complete exposure photo-etching glue pattern, Partial exposure light
Photoresist figure and unexposed photoresist figure；
Develop to the photoetching offset plate figure after exposure, removes the complete exposure photo-etching glue pattern to expose partial oxide
Layer；
The portions of oxide layer exposed is performed etching；
Using cineration technics, the Partial exposure photoetching offset plate figure is removed；
The oxide skin(coating) corresponding to the Partial exposure photoetching offset plate figure carries out conductor chemical industry skill, to form pixel electrode；
The remaining unexposed photoresist figure after removal cineration technics.
5. a kind of display panel, which is characterized in that including display base plate described in claim 1 or claim 2.
6. a kind of display device, which is characterized in that including the display panel described in claim 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610873678.XA CN106449653B (en) | 2016-09-30 | 2016-09-30 | A kind of display base plate and preparation method thereof, display panel, display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610873678.XA CN106449653B (en) | 2016-09-30 | 2016-09-30 | A kind of display base plate and preparation method thereof, display panel, display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106449653A CN106449653A (en) | 2017-02-22 |
| CN106449653B true CN106449653B (en) | 2018-12-21 |
Family
ID=58172749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610873678.XA Active CN106449653B (en) | 2016-09-30 | 2016-09-30 | A kind of display base plate and preparation method thereof, display panel, display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106449653B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273404B (en) | 2017-07-12 | 2021-01-26 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof, display panel and display device |
| CN108321159B (en) * | 2018-02-01 | 2021-01-26 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
| CN112534578A (en) * | 2018-05-09 | 2021-03-19 | 深圳市柔宇科技股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN109244082B (en) * | 2018-08-30 | 2020-10-27 | 天马微电子股份有限公司 | Display panel, preparation method thereof and display device |
| CN110634890B (en) * | 2019-10-11 | 2022-04-15 | 京东方科技集团股份有限公司 | Array substrate, electronic device and manufacturing method of array substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103000632A (en) * | 2012-12-12 | 2013-03-27 | 京东方科技集团股份有限公司 | Complementary metal oxide semiconductor (CMOS) circuit structure and manufacture method and display device thereof |
| CN104537992A (en) * | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | GOA circuit for liquid crystal display device |
-
2016
- 2016-09-30 CN CN201610873678.XA patent/CN106449653B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103000632A (en) * | 2012-12-12 | 2013-03-27 | 京东方科技集团股份有限公司 | Complementary metal oxide semiconductor (CMOS) circuit structure and manufacture method and display device thereof |
| CN104537992A (en) * | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | GOA circuit for liquid crystal display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106449653A (en) | 2017-02-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106449653B (en) | A kind of display base plate and preparation method thereof, display panel, display device | |
| CN102842587B (en) | Array base palte and preparation method thereof, display device | |
| CN110620119A (en) | Array substrate and preparation method thereof | |
| CN104538352A (en) | Array substrate, manufacturing method thereof and display device | |
| CN103474471A (en) | Thin film transistor and preparation method thereof, array substrate and preparation method thereof, and display device | |
| CN103715096A (en) | Thin film thyristor and manufacturing method thereof and array substrate and manufacturing method thereof | |
| CN106024813B (en) | A kind of production method and related device of low temperature polycrystalline silicon tft array substrate | |
| CN105093763A (en) | Array substrate, manufacturing method thereof, liquid crystal display panel and display device | |
| US10121901B2 (en) | Pixel structure with isolator and method for fabricating the same | |
| CN106298957A (en) | A kind of thin film transistor (TFT) and preparation method thereof, array base palte, display device | |
| WO2017140058A1 (en) | Array substrate, manufacturing method therefor, display panel and display apparatus | |
| CN106449521B (en) | Display base plate and preparation method thereof, display device | |
| CN103474439B (en) | A kind of display device, array base palte and preparation method thereof | |
| CN106328592A (en) | Thin film transistor and manufacturing method, the array substrate and display device | |
| CN111129033B (en) | Array substrate and preparation method thereof | |
| US10134765B2 (en) | Oxide semiconductor TFT array substrate and method for manufacturing the same | |
| CN106373967B (en) | Array base palte and preparation method thereof, display device | |
| CN105140234A (en) | Array substrate and manufacturing method thereof and display device | |
| CN104701254B (en) | A kind of preparation method of low-temperature polysilicon film transistor array base palte | |
| US20190326332A1 (en) | Ltps tft substrate and manufacturing method thereof | |
| TW462135B (en) | Method for manufacturing the electronic device of thin film transistor display | |
| CN104681626A (en) | Oxide thin film transistor as well as manufacture and array substrate thereof | |
| WO2017041447A1 (en) | Array substrate and manufacturing method therefor, and display apparatus | |
| WO2016000363A1 (en) | Low temperature poly-silicon thin film transistor array substrate and manufacturing method therefor and display device | |
| CN109192668A (en) | Thin film transistor (TFT) and its manufacturing method, display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |