CN106253899B - Apparatus and associated method for offset trimming - Google Patents

Abstract

The present invention relates to apparatus, and an associated method, for gain and offset fine tuning. In one exemplary embodiment, an apparatus includes a first circuit including a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit including a second circuit to provide an output voltage selectable from a plurality of voltage values and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. By adding the second current to the first current, the output offset of the first circuit is trimmed.

Description

Apparatus and associated method for offset trimming

Cross Reference to Related Applications

This application relates to and is incorporated by reference for various purposes in the following patent applications:

U.S. patent application serial No. 14/732,700 (attorney docket number SILA361) entitled "Apparatus for Digital-to-Analog Conversion with Improved Performance and Associated Methods" filed 6/2015; and

U.S. patent application serial No. 14/732,701 (attorney docket number SILA362) entitled "Apparatus for Gain Selection with Compensation for Parasitic Elements and Associated Methods," filed on 6/2015.

Technical Field

The present disclosure relates generally to electronic devices for processing signals, and more particularly to devices and related methods for gain and offset fine tuning.

Background

Electronic signal processing often requires simultaneous processing of both analog and digital signals, sometimes referred to as mixed signal processing. Some sensors or transducers and natural properties or characteristics, such as temperature, pressure, etc., either constitute analog quantities or, in the case of sensors, often generate analog signals. Additionally, some transducers receive an analog signal as an input.

Instead, as is understood by those of ordinary skill in the art, signal processing circuits and building blocks are increasingly using digital signals and digital technology for reasons such as repeatability, stability, flexibility, and the like. In order to interface the signal processing circuit with the analog circuit, a signal conversion circuit is used.

One type of signal conversion circuit constitutes a digital-to-analog converter (DAC). A DAC is typically used to accept a digital signal as an input and provide an analog signal as an output. Thus, a DAC can provide an interface between a digital processing circuit and an analog circuit, such as a transducer or other circuit.

Several figures of merit are used to characterize or specify the DAC. These figures of merit include resolution (the number of bits of information in the input digital signal), noise level, monotonicity, differential non-linearity (DNL), cost, die area, power consumption, gain and offset levels, and stability, among others.

The description in this section and any corresponding figures are included as background information material. The materials in this section should not be taken as an admission that these constitute prior art to the present patent application.

Disclosure of Invention

An apparatus and associated methods are disclosed herein for an apparatus for gain and offset fine tuning. In one exemplary embodiment, an apparatus includes a first circuit including a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit including a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. By adding the second current to the first current, the output offset of the first circuit is trimmed.

In another exemplary embodiment, an apparatus includes a DAC to convert a digital input signal to an analog output signal. The DAC includes a buffer that buffers a voltage and provides a reference voltage. The DAC further comprises: an RDAC that provides a first voltage and a second voltage in response to a first set of control signals and the reference voltage; and an interpolator coupled to receive the first voltage and the second voltage and to provide a first analog signal in response to the second set of control signals. The interpolator has a trimmable offset voltage. The DAC further includes an offset trimming circuit including a first transconductance stage to provide a first current to the interpolator to trim an offset voltage of the interpolator.

In another exemplary embodiment, a method of fine tuning an offset includes: generating a first current by using a first transconductance stage in a first circuit, the first circuit having an output offset; and providing a voltage selectable from a plurality of voltage values. The method further comprises: generating a second current in response to the voltage by using a second transconductance stage; and trimming the output offset of the first circuit by adding the second current to the first current.

Drawings

The drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of the scope of the application or claims. It should be appreciated by those of ordinary skill in the art that the concepts disclosed lend themselves to other equally effective embodiments. In the drawings, the same numerical designators used in more than one drawing denote the same, similar, or equivalent functionality, components, or modules.

Fig. 1 illustrates a block diagram of a DAC architecture according to an example embodiment.

Fig. 2 depicts a circuit arrangement for a DAC according to an example embodiment.

Fig. 3 illustrates a conceptual block diagram of a DAC architecture according to an example embodiment.

Fig. 4 depicts a circuit arrangement for a DAC according to an example embodiment.

Fig. 5 illustrates values corresponding to the operation of a DAC according to an exemplary embodiment.

Fig. 6 depicts a process flow diagram for operation of a DAC according to an example embodiment.

Fig. 7 illustrates a conceptual block diagram of a DAC architecture according to an example embodiment.

Fig. 8 illustrates a circuit arrangement for fine tuning the gain of a buffer according to an exemplary embodiment.

FIG. 9 illustrates a circuit arrangement for trimming an interpolator offset voltage according to an exemplary embodiment.

Fig. 10 depicts a circuit arrangement for a DAC according to an exemplary embodiment of a compensation parasitic element.

Fig. 11 shows a circuit arrangement for providing offset trimming in a DAC according to an example embodiment.

Fig. 12 illustrates an Integrated Circuit (IC) combining a DAC with other circuit blocks according to an example embodiment.

Fig. 13 depicts a circuit arrangement for information processing using a DAC according to an exemplary embodiment.

FIG. 14 illustrates a control system using a DAC according to an exemplary embodiment.

Fig. 15 shows a circuit arrangement with a feedback loop of a DAC according to an exemplary embodiment.

Fig. 16 depicts a communication system using a DAC according to an example embodiment.

Detailed Description

One aspect of the disclosed concept relates to DAC architectures and techniques that provide certain advantages and benefits. Examples of these benefits and advantages include improved performance and figure of merit as described in detail below.

Various conventional DAC architectures exist. DACs that should meet relatively stringent specifications (e.g., monotonicity and relatively high resolution, e.g., 12 bits) typically include a large number of devices, such as resistors, capacitors, and transistors (typically metal oxide semiconductor field effect transistors or MOSFETs). A relatively simple conventional DAC uses 2N elements of an N-bit resolution architecture, which typically occupies a relatively large die area.

In addition, some specifications of a DAC generally compete with other specifications thereof. For example, monotonicity specifications often compete with high resolution. As another example, low noise operation often competes with the overall power consumption of the DAC.

One technique for obtaining monotonicity includes matching elements. In other words, the various DAC or components or elements such as resistors, capacitors, and MOSFETs are matched to achieve monotonicity. Thus, using component matching, a current mode DAC can be implemented to achieve monotonicity.

In such a DAC, to achieve good matching, the elements are physically relatively large, which is generally proportional to the square root of the element area. As DAC resolution increases, the physical size of the elements also increases. In addition, as the DAC resolution increases, the number of elements doubles for each additional resolution bit. In a simple binary implementation, the total element area is increased by a factor of 8 for each additional resolution bit. More specifically, twice as many elements are used, and each element is four times as large.

In fact, although techniques to reduce the area of the DAC circuit may be used, the element area still increases significantly as the resolution increases. One technique for reducing the amount of components required to match in improving DAC performance is to use thermometer decoding to select the higher order bits (where the matching considerations tend to dominate) and simple binary decoding of the lower order bits. However, the die area used to implement thermometer decoding is much larger than the area used to implement binary encoding, which partially offsets the advantage of having a smaller overall component area.

Another type of conventional DAC does not rely on element matching, where one element will be added per input code increment, so the output voltage or current will rise regardless of the weight of the element. DNL is determined by the absolute element variation such that if the value of each element is within ± 100% of the mean, then a ± 1 least significant bit (or Less Significant Bit) (LSB) DNL is obtained. Brute force algorithm (brute force approach) for realizing monotonic DAC) Using the same number of elements (2) as a simple non-monotonic DAC^N) But the decoding logic and switches used in the DAC tend to be more complex. The reason is that all 2^NEach element is controlled by a unique digital signal rather than the N signals used for a simple binary DAC.

The DAC in various embodiments according to the present disclosure reduces the number of DAC elements and the complexity of the decoding circuit. Accordingly, the DAC according to various embodiments provides monotonic operation with relatively high resolution.

More specifically, a DAC according to an example embodiment may provide 12-bit resolution, relatively low noise operation and monotonicity (± 1LSB DNL), and a relatively small die size. Details of DAC architecture and operating techniques are described in detail below (for static operation, the DAC output is occasionally held at a programmed voltage (i.e., the analog output voltage of the DAC corresponding to the digital input of the DAC) without the application of one or more clock signals).

In some embodiments, a DAC according to the present disclosure uses an architecture that includes a plurality of resistors, switches, and current sources. Fig. 1 shows a block diagram of the architecture of such a DAC. More specifically, fig. 1 shows the architecture of DAC 100, DAC 100 comprising a current source network 103, a switching network 106, a switching network 109, and a resistor network 112, resistor network 112 comprising a plurality of resistors.

The current source network 103 includes a plurality of current sources (n +1 sources in the illustrated example) respectively labeled CS 0-CSn. The output current of the current sources in the current source network 103 is provided to the switching network 106. The switching network 106 causes the output current of the current sources in the current source network 103 to be provided to a node (or circuit branch (leg) or circuit branch (branch) or circuit channel) 106A or a node (or circuit branch or circuit channel) 106B.

As shown in fig. 1, the Lower Significant Bits (LSBs) of the digital input signal to the DAC drive the input of the decoder 118. Decoder 118 decodes the LSBs to generate control signals for switching network 106. In response to these control signals, switching network 106 may provide the output current of current source network 103 to either node 106A or node 106B. Viewed from another perspective, switching network 106 selectively directs the output current of current source network 103 to nodes 106A and 106B. The switching network 106 directs the output current to maintain the monotonicity of the DAC 100.

Nodes 106A-106B are coupled to a switching network 109. The More Significant Bit (MSB) of the digital input signal to the DAC drives the input of the decoder 121. Decoder 121 decodes the MSB to generate the control signals for switching network 109. In response to these control signals, switching network 109 couples nodes 106A and 106B to resistor network 112. Thus, current flowing through nodes 106A-106B flows through selected portions of resistor network 112 according to these control signals. A switching network 109 couples nodes 106A-106B to a resistor network 112 in order to maintain monotonicity of DAC 100. In response, the resistor network 112 provides an analog output.

In an exemplary embodiment, the decoder 118 and decoder 121 may be implemented or realized in various ways and may use various configurations or topologies. In some embodiments, decoder 118 may constitute a thermometer decoder, while decoder 121 constitutes a binary decoder.

It should be noted that for ease of illustration, certain blocks of DAC 100 are omitted from fig. 1. For example, the analog output of the resistor network 112 may be coupled to a buffer or amplifier (not shown) to provide an analog output signal of the DAC 100, which may be used to drive an external load. As another example, the bias circuit is not shown in fig. 1.

Fig. 2 depicts a circuit arrangement for DAC 100 according to an example embodiment. The DAC 100 in fig. 2 operates similar to the DAC shown in fig. 1. Referring to fig. 2, DAC 100 includes a current source network 103, a switching network 106, a switching network 109, and a resistor network 112.

Similar to fig. 1, the current source network 103 in fig. 2 includes a plurality of current sources (n +1 sources in the illustrated example) respectively labeled CS 0-CSn. The output current of the current sources in the current source network 103 is provided to the switching network 106.

The switch network 106 includes a plurality of switches 106A1-106N 2. In the example shown, the switches 106A1-106N2 constitute p-channel MOSFETs. However, as one of ordinary skill in the art will appreciate, other types of switches may be used. As one of ordinary skill in the art will appreciate, the selection of the switch depends on factors such as the available technology, the specifications for a given implementation, and the like.

Referring to the switch network 106, the switches 106A1-106N2 are arranged in pairs and coupled to respective current sources in the current source network 103. Thus, the switch 106a1 and the switch 106a2 are coupled to the current source CS 0. As another example, switch 106B1 and switch 106B2 are coupled to current source CS1, and so on.

The switches 106A1-106N2 are controlled by signals labeled B0 through Bnb. The switches in the switch pairs described above are controlled by complementary signals. For example, the control signal for switch 106a1, signal B0, is the logical complement of the control signal for switch 106a2, signal B0B. As another example, the control signal for switch 106B1, signal B1, is the logical complement of the control signal for switch 106B2, signal B1B, and so on.

Switching network 106 causes the output current of the current sources in current source network 103 to be provided to node 106A or node 106B. The LSB of the digital input signal to the DAC drives the input of the decoder 118. The decoder 118 decodes the LSBs to generate control signals for the switches 106A1-106N2 in the switching network 106, in response to which the respective output currents of the current sources are directed to one of the two nodes.

More specifically, as shown in fig. 2, the LSB of the digital input signal to the DAC drives the input of the decoder 118. The decoder 118 decodes the LSBs to generate control signals for the switch network 106, i.e., for the switches 106A1-106N 2. In response to the control signal, the switching network 106 may provide the output current of the current source network 103 to either node 106A or node 106B.

More specifically, the switching network 106 selectively directs the output current of the current source network 103 to the nodes 106A and 106B, thereby maintaining the monotonicity of the DAC 100. For example, consider the case where signal B0 and signal B0B have low and high logic values, respectively. Thus, the switch 106a1 is turned on, and the switch 106a2 is turned off. Thus, switch 106A1 conducts the output current of current source CS0 to node 106A.

In contrast, assume that signal B0 and signal B0B have high and low logic values, respectively. Thus, the switch 106a1 is turned off, and the switch 106a2 is turned on. Thus, switch 106a2 conducts the output current of current source CS0 to node 106B.

Nodes 106A-106B are coupled to a switching network 109. The switching network 109 includes a plurality of switches labeled 109-0 through 109-m in fig. 2. The More Significant Bit (MSB) of the digital input signal to the DAC causes switches 109-0 to 109-m to be selectively turned on (in accordance with the MSB bit, as described in detail below) and thus couples nodes 106A-106B to resistor network 112.

The MSB bit drives the input of decoder 121. Decoder 121 decodes the MSB bits and generates (m +1) output signals labeled A0-Am. The driver 124 generates switch control signals for the switches 109-0 to 109-m +1, i.e., it generates (m +2) switch control signals.

More specifically, driver 124 derives the switch control signal from the output signal of decoder 121, i.e., signal A0-Am. Signals A0 and Am control switches 109-0 and 109-m +1, respectively, without any further change. However, the switches 109-1 to 109-m use switch control signals derived from logical operations performed on the output of the decoder 121.

For example, the switch control signal for switch 109-1 is

Wherein the symbols

Representing a logical OR (OR) operation. As another example, the switch control signal for switch 109-2 is

And so on. In general, the switch control signal for switch 109-i has

Wherein i represents an integer. For a configuration including (m +2) switches as shown in FIG. 2, switch 109-m has

A switch control signal in the form of (1).

The switching network 109 provides the current received from the switching network 106 to the resistor network 112 through the nodes 106A-106B. More specifically, as described above, decoder 121 decodes the MSBs to generate control signals for the switches in switching network 109. In response to these control signals, switches in switch network 109 couple nodes 106A and 106B to resistor network 112.

Thus, as described in detail below, current flowing through nodes 106A-106B flows through selected portions of resistor network 112 according to the control signal. A switching network 109 couples nodes 106A-106B to a resistor network 112 in order to maintain monotonicity of DAC 100. The resistor network 112 provides an analog output in response to the current provided by the switching network 109.

The resistor network 112 includes a plurality of resistors. In the embodiment shown in fig. 2, the resistor network 112 includes (m +1) resistors labeled R0 through Rm. Depending on the state of the switches in the switch network 109, i.e., whether the respective switches are conductive, current is provided to one or more resistors in the resistor network 112. The flow of current creates a voltage across the resistor network 112, which is provided through the analog output 115.

Thus, in response to a digital input to the DAC 100, the DAC 100 forms an output voltage at the analog output 115. For example, consider the case where the digital input to DAC 100 is incremented to its maximum value starting with all bits set to zero. In response, DAC 100 generates a signal at analog output 115, as described below.

When the MSB is set to zero, the decoder 121 asserts the signal a0 at its output. In response, driver 124 causes switch 109-0 and switch 109-1, which are coupled to resistor R0, to conduct. When the LSB is set to zero, the decoder 118 asserts the signals B0, B1,. gtang, Bn (which results in the signals B0B, B1B,. gtang, Bnb being inactive).

Thus, the switches 106A1, 106B1, 106Bn are on and provide the output current of the current sources CS0-CSn to the node 106A. The current flowing into node 106A flows through switch 109-0 to circuit ground. Therefore, the DAC 100 provides zero volts at the analog output 115.

As the LSB code increments, the output currents of the current sources CS0-CSn will be sequentially supplied to node 106B through the switching network 106. The current provided to node 106B will then flow through resistor R0 to circuit ground, thus causing the output voltage at analog output 115 to increase.

When the output currents of all current sources CS0-CSn have been supplied to node 106B, the MSB code will start to increment, e.g., it will change from 0.. 00 to 0.. 01. Thus, the decoder 121 causes signal a1 to be active and signal a0 to be inactive. However, the output voltage at analog output 115 will not change because all of the current at that point flows through the switch control signal provided by driver 124

A controlled switch 109-1.

As the LSB code is further incremented, the switches in the switching network 106 change state in the reverse order. In other words, the outputs of current sources CS0-CSn will flow sequentially to node 106A, rather than node 106B. Thus, each code increment switches one LSB of current from the upper node of resistor R0 to the upper node of resistor R1. Thus, the output voltage at the analog output 115 rises.

The above process repeats as the digital input to the DAC 100 is incremented to a maximum code value (e.g., all binary 1's). At this point, all of the output currents of current sources CS0-CSn will flow into the upper node of resistor Rm. Thus, the output voltage at the analog output 115 will have a value corresponding to the maximum digital input applied to the DAC 100.

The current steering architecture described above maintains a constant current independent of the digital input provided to DAC 100. The DAC architecture remains monotonic because each step in the digital input removes one bin current from current sources CS0-CSn from a given resistor of resistor network 112 and provides that bin current to the resistor (e.g., from resistor R (m-1) to resistor Rm). The voltage at the analog output 115 will rise in response to a code increment at the input of the DAC 100 as long as the current value is not reduced and as long as the resistor in question has a positive resistance.

In an exemplary embodiment, the driver 124 may be implemented in various ways. For example, in some embodiments, driver 124 may include logic circuitry, such as an OR gate (OR gate), to generate switch control signals for the switches in switch network 109. However, the driver 124 may be implemented in other ways. As one of ordinary skill in the art will appreciate, the choice of implementation depends on factors such as available technology, available die area, performance specifications, and the like.

It should be noted that similar to fig. 1, fig. 2 omits certain blocks of DAC 100 for ease of illustration. For example, the analog output of the resistor network 112 may be coupled to a buffer or amplifier (not shown) to provide an analog output signal of the DAC 100, which may be used to drive an external load. As another example, the bias circuit is not shown in fig. 2.

As described above, the decoder 118 and decoder 121 may be implemented or realized in various ways and may use various configurations or topologies. In the embodiment shown in fig. 2, decoder 118 may constitute a thermometer decoder, while decoder 121 constitutes a binary decoder. Other types and/or configurations of decoders may be used, as will be appreciated by one of ordinary skill in the art.

To control the switching network 106 as compared to the switching network 109, one aspect of the present disclosure relates to the allocation of digital input bits. In other words, the assignment of the digital input bits includes selecting or determining the relative values of m and n, which determine the number of current sources in the current source network 103 and the number of resistors in the resistor network 112.

Considering an embodiment using a thermometer decoder as decoder 118 and a binary decoder as decoder 121, the assignment of bits (bits), i.e., the selection of m and n values, may be based on the properties of the decoders. In particular, the size of a thermometer decoder is typically about twice the size of a binary decoder (i.e., it consumes twice the die area in an IC). Fewer bits may be allocated to the current source if the resistor and current source element sizes are similar. For example, resistor network 112 uses 6 bits and current source network 103 uses 5 bits to produce a decoder having about the same size (i.e., the die area used by decoder 118 and decoder 121 is about the same). (note that the DAC element size is generally selected based on the Integral Nonlinearity (INL) and noise specifications of a given implementation of DAC 100).

Another aspect of the disclosure relates to increasing the resolution of DAC 100 by modifying the switching network. More specifically, the resolution of the DAC 100 can be increased by controlling the gate voltages of the current steering switches rather than biasing them to simple current steering switches. If two switches corresponding to a given current source (e.g., switches 106N1 and 106N2 corresponding to current source CSn) are turned on by setting their two gate voltages equal or approximately equal, the output current of the corresponding current source (e.g., CSn in the previous example) will be divided evenly or approximately evenly between nodes 106A-106B. In other words, the switches are biased to uniformly conduct the output current of the corresponding current source (e.g., CSn in the previous example) between them.

This configuration adds extra resolution bits to the DAC 100 while preserving monotonicity. In an exemplary embodiment, digital control of the switches in the switching network 106 may be implemented using exclusive or gates (XOR gates) to determine which switches correspond to a given current source to which the above control scheme applies.

It should be noted that other mechanisms and circuit arrangements may be used in addition to the use of XOR gates for control. For example, in some embodiments, the control mechanism may be built into a thermometer decoder. It should be noted that the additional bias level may add more resolution bits at the expense of (or degradation of) monotonicity. Thus, as one of ordinary skill in the art will appreciate, there is a tradeoff that may be based on factors such as the specifications for a given application.

In some applications, a relatively low noise level is desirable. One aspect of the present disclosure relates to providing a DAC with a relatively low noise level (e.g., compared to conventional DACs) while preserving monotonicity. Fig. 3 illustrates a block diagram of a low noise DAC 200 according to an exemplary embodiment.

DAC 200 includes a resistor network 203, a switch network 206, a switch network 209, an interpolator network 212, and an output stage 215, where resistor network 203 includes a plurality of resistors. In addition, the DAC 200 includes a decoder 218, the decoder 218 decoding the digital input applied to the DAC 200 and generating control signals for the switching network 206 and the switching network 209.

Resistor network 203 is coupled to reference voltage V_ref. Thus, current flows through resistor network 203. The flow of current through resistor network 203 results in the generation of multiple voltages that are provided to switching network 206.

As described above, the decoder 218 decodes the digital input to the DAC 200 and generates the control signal 218A for the switching network 206. More specifically, the control signal 218A is derived from the More Significant Bit (MSB) of the digital input of the DAC 200. In response to control signal 218A, switching network 206 selectively couples the voltage from resistor network 203 to a reference voltage labeled V _evenAnd V_oddThe node of (2). More specifically, based on control signal 218A, a voltage from resistor network 203 is coupled to node V_evenAnd a voltage is coupled to the node V_odd。

Switching network 209 selectively couples node V_evenAnd V_oddCoupled to interposer network 212. In response, the interpolator network 212 provides a signal, such as a current, to the output stage 215. Based on the signals from the interpolator network 212, the output stage 215 generates an output signal at an analog output 221. In the illustrated embodiment, the analog output 221 constitutes the output of the DAC 200.

The switching network 209 operates in response to the control signal 218B. More specifically, based on controllingThe switching network 209 selectively connects the node V to the signal 218B_evenAnd V_oddCoupled to interposer network 212. The decoder 218 decodes the digital input to the DAC 200 and generates a control signal 218B for the switching network 209. The control signal 218B is derived from the Less Significant Bit (LSB) of the digital input to the DAC 200.

In general, in response to a digital input, DAC 200 uses switching networks 206 and 206 to route two output signals derived from the output of resistor network 203 to interpolator network 212. Thus, DAC 200 may be considered as generating two outputs (at node V) coupled to drive an interpolator (interpolator network 212 driven by switch network 209) _evenAnd V_oddAt) a resistor network 203 that drives a switching network 206.

In an exemplary embodiment, the interposer network 212 may be implemented in various ways. For example, in some embodiments, the interposer network 212 may use multiple transconductances (g)_m) A stage or an amplifier. Thus, interposer network 212 may be g_mAn interposer network.

Fig. 4 depicts a circuit arrangement for the DAC 200 according to an example embodiment. Similar to the embodiment shown in fig. 3, DAC 200 in fig. 4 includes resistor network 203, switch network 206, switch network 209, interpolator network 212, and output stage 215. In addition, the DAC 200 includes a decoder 218, the decoder 218 decoding the digital input applied to the DAC 200 and generating control signals for the switching network 206 and the switching network 209.

Resistor network 203 includes a series coupling at a reference voltage (V)_ref) And ground potential (labeled R0-RN). In some embodiments, resistors R0-RN may have the same (or approximately the same) resistance value. Applying a reference voltage to the resistor will cause a current to flow through the resistor string. Thus, multiple voltages are formed across each identical resistor of the plurality of resistors in resistor network 203. The resulting plurality of voltages is fed to a switching network 206.

The switching network 206 includes a Multiplexer (MUX)206A and a MUX 206B. The MUXs 206A-206B operate in response to the control signals 218A1-218A2, respectively. Resistors R0-RN are coupled to MUXs 206A-206B in an alternating manner. More specifically, the upper node of each resistor is alternately coupled to MUX 206 and MUX 206B. For example, the upper node of resistor R0 is coupled to an input of MUX 206A, while the upper node of resistor R1 is coupled to an input of MUX 206B, and so on.

The decoder 218 generates the control signals 218A1-21A2 in response to digital inputs applied as input signals to the DAC 200. The control signals 218A1-21A2 together form the control signal 218A. The decoder 218 generates the control signals 218A1-21A2 based on the value of the More Significant Bits (MSBs) of the digital input to the DAC 200. In other words, the control signals 218A1-21A2 are derived from the MSB to control the MUXs 206A-206B, respectively.

The control signals 218A1-21A2 cause the MUXs 206A-206B to selectively couple the resistors R0-RN to the resistors labeled V_evenAnd V_oddOne of the two nodes. Thus, based on the MSB, the MUXs 206A-206B selectively provide the output voltage of the resistor network 203 to the node V_evenAnd V_odd. In the illustrated embodiment, node V_evenAnd V_oddAre coupled to half of the resistors in the resistor network 203 through the switch network 206, and the couplings are staggered. Thus, node V _evenAnd V_oddAcross the extent of the resistor string or ladder, but coupled to V by upper nodes of different or alternating resistors, e.g. even-numbered resistors_evenNode, and the upper node of the odd resistor is coupled to V_oddA node (or vice versa).

Node V_evenAnd V_oddCoupled to an input of the switching network 209. Switching network 209 includes MUXs 209-0 to 209-k. Node V_evenCoupled to one input of MUXs 209-0 to 209-k. Node V_oddTo another input of MUXs 209-0 to 209-k. The outputs of MUXs 209-0 to 209-k drive respective inputs of interpolator network 212.

Switching network 209 selectively couples node V_evenAnd V_oddCoupled to interposer network 212. Specifically, the switching network 209 operates in response to the control signal 218B. Therefore, the temperature of the molten metal is controlled,based on the control signal 218B, the switching network 209 switches the node V_evenAnd V_oddOptionally to an interposer network 212.

Decoder 218 provides control signal 218B. In particular, the decoder 218 decodes the digital input to the DAC 200 and generates the control signal 218B for the switching network 209. The control signal 218B is derived from the Less Significant Bit (LSB) of the digital input to the DAC 200.

Switching network 209 couples node V_evenAnd V_oddOptionally to an interposer network 212. In the illustrated embodiment, the interpolators in the interpolator network 212 constitute a plurality of transconductors (g) _m) Stage or amplifier, thus g_mAn interposer network. G in interposer network 212_mThe interpolator is marked g_m0To g_mk。

As described above, each g in interposer network 212_mOne input, e.g., a non-inverting input, in the interpolator is coupled to a respective output of a MUX among MUXs 209-0 through 209-k. G in interposer network 212_mThe other input, e.g., the inverting input, in the interpolator is coupled to a feedback network comprising a resistor 224 and a resistor 226. Specifically, g in the interpolator network 212 is provided through resistor 224 and resistor 226_mThe interpolator receives a signal that is related (in the embodiment shown in fig. 4, scaled down) to the signal at the analog output 221. By selecting appropriate values for resistors 224 and 226, the overall gain of the interpolator network 212 and output stage 215 can be programmed to a desired value.

In response to the outputs of MUXs 209-0 through 209-k, g_mInterposer g_m0To g_mkOutput signals are provided that are summed at node 212A to generate an output signal (e.g., a current signal) for the interpolator network 212. The signal at node 212A drives the input of the output stage 215. In response, the output stage 215 generates an output signal at the analog output 221. In the illustrated embodiment, the analog output 221 constitutes the output of the DAC 200.

The output stage 215 may be implemented in various ways. For example, in some embodiments, the output stage may include transconductance stage(s) and an amplifier, such as a class AB amplifier. The output stage 215 provides an analog signal at an analog output 221, which may drive an external load.

As with the DAC in fig. 2, several bits of the digital input of DAC 200 may be assigned to control switch network 206, while the remaining bits may be assigned to drive switch network 209. For example, consider a 12-bit DAC according to one embodiment, where 5 bits of the digital input to the DAC implement the LSB of DAC 200. In such a DAC, a resistor string in the resistor network 203 implements the 7 MSBs (128 elements) of the DAC. In such an embodiment, MUX 206A and MUX 206B are controlled by 6-bit control or select signals 218a1 and 218a2, respectively.

The remaining 5 bits of the digital input to DAC 200 implement the LSB. Thus, the DAC includes 2 in the switching network 209⁵Or 32 MUXs. The outputs of the 32 MUXs drive one input of the interpolators in interpolator network 212. In such an embodiment, interposer network 212 includes 32 interposers, i.e., k-31.

To illustrate the operation of such a DAC, it should be noted that the MUXs 206A and 206B couple the taps in the resistor string in the resistor network 203 to V _evenAnd V_oddA node or a bus. Since the 7 MSBs in the digital input to the DAC ramp up from 0000000 to 1111111, the voltage from the resistor taps changes in a "leapfrog" manner or in an alternating manner. FIG. 5 illustrates the presence at node V_evenAnd V_oddAt some voltage.

As shown in the table in fig. 5, at node V_evenAnd V_oddThe voltage of which depends on the reference voltage V_refAnd MSB input code (indicated under the column heading "code"). It should be noted that in response to successive code changes, at node V_evenAnd V_oddThe voltage at (1/128) V_refOr 0.0078125. V_refThe voltage of (c). If V_refHas a value of 1.2 volts, then V_evenAnd V_oddThe difference between will be about 10 mV. It should be noted that if the MSB code is even, V_oddWill ratio V_evenThe height is 10 mV. Conversely, if the MSB code has an odd value, V_evenWill ratio V_oddThe height is 10 mV. By generating a function ofOutput (V) of input code and reference voltage value_evenAnd V_odd) The combination of the resistor string and the switching network (and corresponding decoder circuit) may be considered an RDAC.

In the example discussed above, interposer network 212 implements the lower 5 LSBs. As the name implies, the interposer network 212 uses 32 grams_mInterposer at V_evenAnd V_oddInterpolating between the voltages at the nodes. As described above, the control signal 218B derived from the LSB in the digital input of the DAC is controlled at V _evenSum of voltage at V_oddWhich of the voltages at is provided to each respective interpolator in interpolator network 212.

To illustrate the operation of interposer network 212, assume that the 7 MSBs have a value of 0000000, i.e., are all 0. In this case, V_evenIs 0V, and V_oddWith a value of about 10mV (see fig. 5). When the 5 LSBs are all 0 (i.e., 00000), 32 g_mThe interpolators connect their non-inverting inputs to V_evenI.e. 0V or ground potential. Assuming that the output stage 215 has a gain of 3V/V, the signal at the analog output 221 will have a value of 0V (ground potential).

As the LSB ramps up (ramp up) or increments from 00000 to 11111, each increment of the code (LSB value) results in a signal being provided to g by the switching network 209_mInterposer g_m0-g_mkOne of the inputs is from V_even(0V) to V_odd(≈ 10 mV). When the LSBs are all binary 1 (code 11111), the switching network 209 will have V_odd(≈ 10mV) is provided to 32 g_m31 of the interpolators are used as inputs. In this case, the voltage at analog output 221 will have a value of 3 × (31/32) × 10mV, or approximately 29 mV.

For LSB code values between 00000 and 11111, switching network 209 couples node V_evenThe voltage at (a) is supplied to some g_mAn interpolator, and apply a voltage V_oddIs provided to the rest of g _mAn interpolator. Thus based on the receiving node V_oddAs a part g of the input signal_mThe signal at analog output 221 will have an interpolated value between 0V and about 29 mV. V_evenAnd V_oddThe small voltage difference between provides linear or near linear interpolation performed by the interpolator network 212.

The "frog-jump" or alternating property described above occurs when the 12-bit input (i.e., the digital input to the DAC) increments to the next value after 000000011111. The 7 MSBs in the digital input increment from 0000000 to 0000001 and the 5 LSBs change from 11111 to 00000. Decoder 218 provides control signals 218B to MUXs 209-0 through 209-k, respectively, such that incoming bits are converted when the MSB code is odd, thereby all 32 g' s_mInterposer receiving node V_oddThe voltage at (c) is taken as input (it still has a value of ≈ 10 mV).

When the incoming LSB code in the DAC digital input is incremented to 00001, 31 g_mThe interposer is still coupled (via switching network 209) to receive at node V_oddThe voltage at is taken as input, and one g_mInterposer receiving node V_evenThe voltage at (c) is taken as input, which now has a value of ≈ 20mV instead of 0V. In this way, as the incoming LSB is further incremented, more g' s _mThe interpolator stage receiving at node V_evenAt a voltage other than at node V_oddThe voltage of (d). Thus, the interpolated signal (at output 212A) and thus the output signal at analog output 221 continue to rise. Finally, all g_mThe interposer is received at node V_evenThe voltage at (c) is used as an input. At this point the MSB code is incremented again and the process repeats.

It should be noted that although the DAC operation is described above with reference to a 12-bit DAC according to an exemplary embodiment, similar descriptions and operations apply to DACs according to other exemplary embodiments. Thus, as one of ordinary skill in the art will appreciate, the concepts described may be applied to DACs having different resolutions, different numbers of elements, and the like.

Fig. 6 depicts a process flow diagram for operation of a DAC according to an example embodiment. At 253, a digital input signal provided to the DAC is received. At 256, the digital input signal is decoded to derive a set of control signals from the More Significant Bits (MSBs) of the digital input signal. Another set of control signals is derived from the Less Significant Bits (LSBs) of the digital input signal.

At 259, a set of control signals derived from the MSB are used to drive the RDAC to generate V_oddAnd V _even. At 262, a set of control signals derived from the LSB are used to drive an interpolator to derive a reference voltage from V_oddAnd V_evenAn analog output signal is obtained. For example, as described above, the analog output signal may be further buffered or processed using an output stage.

The DAC disclosed in connection with fig. 3-5 provides a number of benefits and advantages. For example, one advantage relates to relatively low noise operation, while maintaining monotonicity and other characteristics described above, as compared to conventional DACs. Another advantage relates to the relative ease of setting a relatively accurate gain for the DAC.

One aspect of the present disclosure relates to gain selection or adjustment in an electronic device, such as a DAC. The following description uses a DAC as an example to illustrate the concepts, but as one of ordinary skill in the art will appreciate, the disclosed concepts may be applied to a variety of electronic devices having selectable or adjustable gains.

As described above, the gain of the DAC according to the exemplary embodiment depends on the reference voltage (V)_ref) The value of (c). To illustrate various values such as V_refAnd the effect of the gain of the output stage on the overall DAC characteristics, fig. 7 provides a conceptual block diagram of a DAC 200 according to an example embodiment.

In the illustrated embodiment, the reference voltage (i.e., V) used in the DAC _ref) May be the original reference voltage (V)_r) Scaled or divided versions of (a). Alternatively or additionally, the original reference voltage may be applied externally to the DAC 200, e.g., by way of a pin in the IC comprising the DAC 200_EXTIs applied to DAC 200. As one of ordinary skill in the art will appreciate, various sources, such as an external reference source, may provide the voltage V_EXT. As described in detail below, in such a configuration, DAC 200 includes circuitry for processing and using signals provided by a reference source to generate V_refThe mechanism of (2).

In either case, by using for zooming orWith appropriate values of the division factor, an overall desired DAC gain value can be obtained. Scaling circuit 303 applies a desired scaling factor to V_rTo generate a scaled version at output 303A of scaling circuit 303 that is applied to buffer 306. The scaling factor of scaling circuit 303 may have a desired value or set of values and may be programmable or adjustable as desired. The buffer 306 is V_rProvides buffering or amplification and provides a DAC reference voltage V at its output 306A_ref. The buffer 306 has a gain fine adjustment input 306B that allows its gain to be fine-tuned.

As described above, the reference voltage V _refIs applied to the RDAC 309. As described in detail above, in response to control signals 218A and V_refRDAC 309 provides a voltage V at its output_evenAnd V_odd. As described above, the decoder 218 provides the control signal 218A by decoding the digital input signal applied to the DAC 200.

The interpolator 312 accepts the label V_evenAnd V_oddAs an input. As described in detail above, the interpolator 312 can include a switching network and several interpolator stages. As described in detail above, in response to the control signal 218B, the interpolator 312 forms the voltage V at the output 312A_evenAnd V_oddThe output voltage of the function of. As described above, the decoder 218 provides the control signal 218B by decoding the digital input signal applied to the DAC 200.

Interpolator 312 has an offset trim input 312B. The signal applied at input 312B may be used to fine tune the offset voltage of interpolator 312B. As one of ordinary skill in the art will appreciate, doing so will improve the overall performance of the DAC 200. As described in detail above, the output stage 215 receives the output signal of the interpolator 215 and generates the analog output of the DAC 200 at the output 221. In an exemplary embodiment, the output stage 215 may have a programmable or adjustable gain. This feature allows the overall gain or full scale voltage of DAC 200 to be set.

Scaling circuit 315 scales the analog output voltage of DAC 200 to generate V at output 315A_rA scaled version of (a). The scaled voltage at output 315A is provided to interpolator 312 as a feedback signal derived from the output voltage of interpolator 312. The scaling factor of scaling circuit 315 may have a desired value or set of values and may be programmable or adjustable as desired. Thus, the effective gain of the output stage (more specifically, the total gain of the interpolator 312 and output stage 215) can be programmed to a desired value.

Reducing the voltage V_rMany benefits may be provided, such as ease of implementation. In some embodiments, n-type mos (nmos) devices may be used in a switching network (not shown in fig. 7) in the DAC 200. Reduction V_rAllowing the swing of the input voltage applied to the interpolator stages in the interpolator 312 to be reduced or limited. Further, the voltage V is scaled_rAllowing the overall gain or full scale output voltage of DAC 200 to be programmed or set.

In an exemplary embodiment, buffer 306 has a gain in unity, but a combination of buffer 306 and scaling circuit 303 may be used to provide a programmable gain setting. The programmable gain setting may have various desired values, for example, 1/2, 1/2.4, and 1/3. The programmable gain setting allows the overall gain of the DAC 200 to be set or programmed. As an example, consider a DAC with an output stage 215 having a gain of 3. If a DAC is desired with an overall gain of unity, a scaling factor of 1/3 may be used for scaling circuit 303, i.e., V _ref＝(1/3)×V_r. The total gain will have a value of 1/3 x 3 or unity.

The buffer 306 also has gain trimming capability, which allows the output offset voltage of the buffer 306 to be cancelled (or nearly cancelled). If the output offset voltage is not eliminated, it will appear in the DAC as a gain error and will degrade its performance. In an exemplary embodiment, the fine tuning of the gain of buffer 306 may correct (or approximately correct) for temperature change effects, supply voltage variations, and the like.

The fine tuning of the gain of the buffer 306 may be carried out in many ways. In some embodiments, the trimming is performed at the time of product testing, i.e., during testing after processing. In some embodiments, trimming is performed during use, such as periodically or upon power up, and/or according to other schemes, as desired. Fig. 8 illustrates a circuit arrangement 350 for fine tuning the gain of buffer 306 according to an exemplary embodiment. (other aspects of offset trimming are discussed below in connection with FIG. 11.)

Referring to fig. 8, the output signal of the scaling circuit 303 is applied to the switch 353. The use of the switch 353 is optional. If the switch is used under the control of the controller 359, the switch 353 allows selective use of V_rOr another gain adjustment voltage to fine tune the gain of the buffer 306 (the controller 359 or another part of the DAC may generate a voltage for gain fine tuning). The voltage selected by switch 353 is applied to the input of buffer 306. The output of buffer 306 is applied to switch 356. The switch 356 may selectively provide the output 306A of the buffer 306 to the RDAC 309 or the controller 359 under the control of the controller 359.

During normal operation (i.e., when there is no gain trim to buffer 306), switch 356 couples output 306A to RDAC 309. During a gain trim operation, switch 356 couples output 306A to controller 359. Based on the actual output voltage of buffer 306 and the expected output voltage (based on the input voltage applied to buffer 306), controller 359 applies one or more control signals to gain trim input 360B of buffer 306. Accordingly, the gain of buffer 306 is fine-tuned to a desired value (e.g., in the exemplary embodiment, the unit of one).

It should be noted that, as described above, in some embodiments, a user of the DAC (or other device, circuit, module, etc.) may cause the controller 359 to perform gain trimming at one or more desired points in time. It is further noted that in some embodiments, the DAC may be configured to automatically perform gain trimming at one or more desired points in time, such as during power-up or reset of the DAC, as desired. Moreover, various other circuit arrangements are possible and are contemplated. For example, in some embodiments, controller 359 can be implemented partially or entirely external to the IC on which the DAC resides, such as in a production tester that performs operations such as testing and trimming after IC processing. As one of ordinary skill in the art will appreciate, in some embodiments, for example, switch 353 and/or switch 356 may be omitted, and instead an additional input or parallel input to buffer 306 (instead of switch 353) may be used, such as by sensing the output of RDAC 309 (instead of using switch 356), or the like.

Similarly, the output offset voltage of the interpolator 312 can be fine-tuned. In an exemplary embodiment, the fine tuning of the output offset voltage of the interpolator 312 may correct (or approximately correct) for temperature change effects, supply voltage variations, and the like.

Trimming of the output offset voltage of the interpolator 312 can be performed in many ways. In some embodiments, the fine tuning is performed at the time of product testing, i.e., during testing after processing. In some embodiments, trimming is performed during use, such as periodically or upon power up, and/or according to other schemes, as desired. Fig. 9 illustrates a circuit arrangement 400 for trimming an interpolator offset voltage according to an exemplary embodiment. (other aspects of offset trimming are discussed below in connection with FIG. 11.)

Referring to FIG. 9, voltage V_evenAnd V_oddAre applied to switches 403A and 403B, respectively. It should be noted that the use of switches 403A-403B is optional. If the switch is used under the control of controller 359, switches 403A-403B allow selective use of V_evenAnd V_oddOr another set of offset trim voltages to trim the offset of the interpolator 312 (the controller 359 or another portion of the DAC may generate voltages for offset trim).

The voltages selected by the switches 403A-403B are applied to the inputs of the interpolator 312. The output of interpolator 312 is applied to scaling circuit 315, as described above. The output 315A of the scaling circuit 315 is provided to a controller 359. The output signal of the scaling circuit 315 is used to fine tune the output voltage offset of the interpolator 312.

Under the control of the controller 359, the switch 406 may selectively provide either the control signal 218B (generated by the decoder 218 as described in detail above) or a control signal 359A (available at the output 306A) generated by the controller 359 to the interpolator 312. The controller 359 generates control signals 359A based on the input signals to the interpolator 312 to cause the interpolator 312 to have a desired output voltage (e.g., 0V) to determine and fine tune the output offset voltage of the interpolator 312.

During normal operation (i.e., when the offset voltage of the interpolator 312 is not being fine-tuned), the switches 403A-403B will apply a voltage V_evenAnd V_oddIs coupled to the interpolator 312. In addition, switch 406 provides control signal 218B (generated by decoder 218) to interpolator 312. Thus, as described above, the DAC generates an analog output signal in response to a digital input.

However, as described above, during the offset trim operation, switches 403A-403B couple V _evenAnd V_oddOr another set of offset trim voltages to trim the offset of the interpolator 312. In addition, switch 406 provides control signal 359A to interpolator 312. The output 315A of the scaling circuit 315 provides a scaled version of the output voltage of the interpolator 312 to the controller 359.

Depending on the actual output voltage of the interpolator 312 and the desired output voltage (based on the input voltage applied to the interpolator 312) (or a scaled down version at the output 315A of the scaling circuit 315), the controller 359 applies one or more control signals to the offset trim input 312B of the interpolator 312. Accordingly, the offset of interpolator 312 is fine-tuned to a desired value (e.g., zero or approximately zero).

It should be noted that, as described above, in some embodiments, a user of the DAC (or other device, circuit, module, etc.) may cause the controller 359 to perform offset trimming at one or more desired points in time. It is further noted that in some embodiments, the DAC may be configured to automatically perform offset trimming at one or more desired points in time, such as during power-up or reset of the DAC, as desired. Moreover, various other circuit arrangements are possible and are contemplated. For example, in some embodiments, controller 359 can be implemented partially or entirely external to the IC on which the DAC resides, such as in a production tester that performs operations such as testing and trimming after IC processing. As one of ordinary skill in the art will appreciate, in some embodiments, for example, switches 403A-403B and/or switch 406 may be omitted, instead of using additional or parallel inputs to interpolator 312 (instead of switches 403A-403B) to adjust the offset voltage of interpolator 312 (instead of using switch 406), by sensing the voltage at output 221 and applying a correction voltage through 312B, and so forth.

Various alternative configurations of the circuit arrangements in fig. 8-9 are possible and conceivable. For example, in some embodiments, some or all of the functionality of decoder 218 may be combined with the functionality of controller 359, or vice versa. As will be appreciated by those of ordinary skill in the art, the choice of circuit arrangement used in a particular application depends on factors such as the specifications for that application.

As described above, in exemplary embodiments, more than one source may be used to generate reference voltage V_ref. This involves the use of a switch that allows selection of the source. The switch has a finite parasitic element, such as a parasitic resistance (e.g., on-state resistance). In addition, as described above, V is changed_refResults in a change in the overall gain or output full scale value of the DAC.

To maintain or provide a desired gain or full scale value, the effective gain of the output stage may be programmed or set to correspond to a selected V_refThe value of the value. The effective gain of the output stage (the total gain of the interpolator and output stage 215) can be programmed by the scaling circuit 315. Programming the effective gain of the output stage involves the use of switches in the scaling circuit 315. These switches also have limited parasitic elements, such as parasitic resistances (e.g., on-state resistances). One aspect of the present disclosure relates to gain and offset trimming or adjustment in electronic devices such as DACs.

One aspect of the present disclosure relates to compensating for parasitic elements or effects, such as parasitic resistances of the above-described switches in an electronic device, such as a DAC. Fig. 10 depicts a circuit arrangement of a DAC 200 according to an exemplary embodiment for compensating parasitic elements.

The DAC 200 in fig. 10 includes some of the same or similar modules or circuits as those shown in fig. 7. Scaling circuit 303 in fig. 10 provides for selecting for generating V_refOf one or both sources. In the illustrated embodiment, the external voltage (V) from a source external to DAC 200_EXT) Or another voltage V_r(e.g., internally generated sources) can be used to generate V_ref。

Voltage V_EXTAre applied to have R respectively₁And R₂Tapped resistors 450A-450B of resistance value. Switch 456D couples resistor 450B to ground. Switch 456D allows V to be driven from V through resistors 450A-450B when the corresponding portion of scaling circuit 303 is not in use, when DAC 200 is not in use, or the like_EXTThe current flowing to the ground line is interrupted, which results in reduced power consumption. Controller 359 controls the operation of switch 456D.

Taps in resistors 450A-450B are coupled to switches 456A and 456C, respectively. Switch 456B is coupled to one end or terminal of resistor 450A and one end of resistor 450B. A controller 359 controls the operation of each of the switches 456A-456C. For example, the controller 359 may cause the switches 456A-456B to open and the switch 456C to close. By controlling the switch, the controller 359 may cause the voltage V to be provided at the output 303a1 of the scaling circuit 303 _EXTA programmable portion or a desired portion of (a).

Similarly, the voltage V_rAre applied to have R respectively₁And R₂Resistors 453A-453B. Switch 459D couples resistor 453B to ground. When the corresponding portion of the scaling circuit 303 is not used, or when the DAC 200 is not used, etc., the switch 459D allows V to be driven from V through the resistors 453A-453B_rThe current flowing to the ground line is interrupted, which results in reduced power consumption. The controller 359 controls the operation of the switch 459D.

Taps of resistors 453A-453B are coupled to switches 459A and 459C, respectively. Switch 459B is coupled to one end or terminal of resistor 453A and one end of resistor 453B. Controller 359 controls the operation of each switch 459A-459C. For example, the controller 359 may cause the switches 459A-459B to open and the switch 459C to close. By controlling these switches, the controller 359 may cause the voltage V to be provided at the output 303a2 of the scaling circuit 303_rA programmable portion or a desired portion of (a). As shown in the figure, the inputThe outputs 303a1 and 303a2 flow into the inputs of the buffer 306.

As described above, the scaling circuit 315 will be used to provide a scaled version (denoted V) of the output signal (available at the output 221) of the output stage 215₀) Is provided to the interpolator 312. Voltage V ₀Are applied to the substrate having M.R₁And M.R₂Resistors 462A-462B of resistance value (M), where M represents a positive integer. Switch 465D couples resistor 462B to ground. Switch 465D allows V to be driven through resistors 462A-462B when the corresponding portion of scaling circuit 303 is not in use, or when DAC 200 is not in use, etc₀The current flowing to the ground line is interrupted, which results in reduced power consumption. The controller 359 controls the operation of the switch 465D.

Taps in resistors 462A-462B are coupled to switches 465A and 465C, respectively. Switch 465B is coupled to one end or terminal of resistor 462A and one end of resistor 462B. A controller 359 controls the operation of each switch 465A-465C. For example, the controller 359 can cause the switches 465A-465B to open and the switch 465C to close. By controlling these switches, the controller 359 may cause the voltage V to be applied₀Is provided to the interpolator 312 to enable gain programming of the output stage of the DAC 200.

In a practical implementation, the circuit arrangement shown in FIG. 10 includes various parasitic elements, such as parasitic resistances of switches 456A-456D, 459A-459D, and 465A-465D. Parasitic resistances of switches 456D, 459D, and 465D may cause errors when setting the gain or full-scale output value of DAC 200. By appropriately sizing the components in scaling circuits 303 and 315, the errors may be cancelled or nearly cancelled.

Specifically, as described above, the respective resistances of resistors 462A-462B are M times greater than the resistances of resistors 450A-450B. In addition, assume that switches 456D and 459D have values of R_SWThe switch 465D is scaled or sized to have M.R_SWThe parasitic resistance of (1). Selection of component sizes and values offsets or approximately offsets the gain error discussed above, provided that the effective gain G of the output stage_out(i.e., of interpolator 312 and output stage 215)Total gain) is the effective gain G of the reference voltage gain setting circuit_ref(i.e., the total gain of the scaling circuit 303 and the buffer 306).

The following equation represents the overall gain of the DAC 200 in such a case:

G_ref·G_out＝{(R₂+R_sw)/(R₁+R₂+R_sw)·{1+(M·R₁)/((M·R₂)+(M·R_sw) ) } [ equation 1]

It should be noted that G if the reciprocal condition described above is met_ref·G_out＝1。

Further, it should be noted that if G is_refAnd G_outNot set to the reciprocal value, the gain error will be partially cancelled. Thus, G_refAnd G_outThe closer the values of (a) are set to the reciprocal of each other, the better the gain error is cancelled out.

The techniques for canceling gain errors due to parasitic elements have been described with reference to a DAC. However, one of ordinary skill in the art will appreciate that these concepts may be applied to other electronic devices with modifications.

Another aspect of the disclosure relates to trimming (trim) or correcting various offset errors in an electronic device, such as a DAC. Fig. 11 shows a circuit arrangement for providing offset trimming in a DAC according to an example embodiment. Constant current source 503 provides a current I to resistor 506 and resistor 512 coupled as a resistor string. The flow of current through resistor 506 and resistor 512 results in a voltage level for trimming the offset.

More specifically, resistor 506 and resistor 512 have several taps. As will be appreciated by one of ordinary skill in the art, for example, in some embodiments resistor 506 may have 31 taps and resistor 512 may have 31 taps, although other numbers of taps may be used. A tap in resistor 506 is coupled to switch 509. The lower end or terminal of the resistor 506 may be used as an additional tap and coupled to one of the switches 509. Thus, the current flow through the resistor 506 provides several voltage levels available through taps in the resistor 506.

A switch 509 selectively couples a tap of the resistor 506 to the node 509A. A controller 359 controls the operation of the switch 509. In particular, the controller 359 can cause one or more switches 509 to turn on. In this manner, the controller 359 can provide several voltage levels to the node 509A. For example, by turning on a single one of the switches 509, the controller 359 may cause the voltage level at the tap coupled to that switch to be available at node 509A.

Similarly, a tap in resistor 512 is coupled to switch 515. The lower end or terminal of resistor 512 may be used as an additional tap and coupled to one of switches 515. Thus, the flow of current through resistor 512 through the taps in resistor 512 provides several available voltage levels.

Switch 515 selectively couples a tap of resistor 512 to node 515A. A controller 359 controls the operation of the switch 515. In particular, the controller 359 can cause one or more switches 515 to turn on. In this manner, controller 359 can provide several voltage levels to node 515A. For example, by turning on a single one of switches 515, controller 359 may cause the voltage level at the tap coupled to that switch to be available at node 515A.

Switch 518 couples resistor 509 to ground. Thus, when the offset trimming function is not used or when the DAC is not used, etc., the switch 518 allows the current flowing from the current source 503 to the ground through the resistors 506 and 509 to be interrupted, which results in reduced power consumption. The controller 359 controls the operation of the switch 518.

The voltage at node 509A is used to fine tune the output offset of interpolator 312. More specifically, the voltage at node 509A drives transconductance (g) _m) The input of stage or amplifier 312-2. g_mThe output current of stage 312-2 is provided to output 312A of interpolator 312. As described above, the interposer 312 includes receiving the voltage V through a switching network_evenAnd V_oddA number of g_mStage (labeled 312-1). In response, g_mStage 312-1 generates output currents that are provided togetherTo the output 312A of the interpolator 312.

In other words, the current available at the output 312A of the interpolator 312 constitutes g_mCurrent provided by stage 312-1 and sum of g_mThe sum of the currents provided by stage 312-2. By changing the sum of g_mThe magnitude and/or polarity of the current provided by stage 312-2, the output offset of interpolator 312 and thus the output offset voltage of the DAC may be trimmed or cancelled or approximately cancelled.

In an exemplary embodiment, g_mStage 312-2 to g_mStage 312-1 has a lower current drive or drive capability (or strength) or transconductance value. Thus, g_mStages 312-2 and g_mStage 312-1 injects less current into node 312A than it does. In other words, the output offset of the interpolator 312 can be fine-tuned with finer granularity.

As described above, the trimming of the output offset voltage of the interpolator 312 can be performed in many ways. In some embodiments, the fine tuning is performed at the time of product testing, i.e., during testing after processing. Based on these results, the control level for switch 509 may be stored (e.g., in memory) for further retrieval and use in fine tuning the offset of interpolator 312. Further, as described above, in some embodiments, trimming is performed during use, such as periodically or upon power up, and/or according to other schemes, as desired.

Referring to FIG. 11, the voltage at node 515A is used to trim the output offset of buffer 306. The output offset of the trim buffer 306 provides gain trimming for the overall DAC.

The voltage at node 515A is used to fine tune the output offset of interpolator 312. More specifically, the voltage at node 515A drives transconductance (g)_m) The input of stage or amplifier 306-2. g_mThe output current of stage 306-2 is provided to output 306A of buffer 306. Buffer 306 also includes g that receives the voltage from output 303A of scaling circuit 303_mStage 306-1. In response, g_mStage 306-1 generates an output current that is converted to V by output stage 306-3_ref。

In other words, the current available at the output 306A of the buffer 306 constitutes g_mCurrent sum provided by stage 306-1 and g_mThe sum of the currents provided by stage 306-2. By changing the sum of g_mThe magnitude and/or polarity of the current provided by stage 306-2, the output offset of buffer 306, and thus the overall gain of the DAC, can be fine tuned.

In an exemplary embodiment, g_mStage 306-2 to g_mStage 306-1 has a lower current drive or drive capability (or strength) or transconductance value. Thus, g_mStage 306-2 and g_mStage 306-1 injects less current into node 306A than it does. In other words, the output offset of the buffer 306 can be fine-tuned with finer granularity.

As described above, the trimming of the output offset voltage of the buffer 306 may be performed in many ways. In some embodiments, the fine tuning is performed at the time of product testing, i.e., during testing after processing. Based on these results, the control level for switch 515 may be stored (e.g., in memory) for further retrieval and use in fine tuning the offset of buffer 306. Further, as described above, in some embodiments, trimming is performed during use, such as periodically or upon power up, and/or according to other schemes, as desired.

For example, according to an exemplary embodiment, a DAC may be combined with other circuitry by integrating the DAC and signal processing or computing circuitry within an IC. Fig. 12 illustrates an Integrated Circuit (IC)550, e.g., a microcontroller unit (MCU), that combines a DAC with other circuit modules, according to an example embodiment.

IC 550 includes several modules (e.g., processor 565, data converter 605, I/O circuitry 585, etc.) that communicate with one another using link 560. In an exemplary embodiment, link 560 may constitute a coupling mechanism, such as a bus, a set of conductors, or a semiconductor for communicating information, such as data, commands, status information, and the like.

IC 550 may include a link 560 coupled to one or more processors 565, clock circuits 575, and power management circuits 580. In some embodiments, processor 565 may include circuitry or modules to provide computational functions, such as a Central Processing Unit (CPU), Arithmetic Logic Unit (ALU), and so forth. In some embodiments, processor 565 may additionally or alternatively include one or more Digital Signal Processors (DSPs). The DSP may provide various signal processing functions such as arithmetic functions, filtering, delay blocks, etc., as desired.

Clock circuit 575 may generate one or more clock signals that facilitate or control the timing of operation of one or more modules in IC 550. Clock circuit 575 may also control the timing of operations using link 560. In some embodiments, clock circuit 575 may provide one or more clock signals to other modules in IC 550 via link 560.

In some embodiments, power management circuit 580 may reduce a clock speed of a device (e.g., IC 550), turn off a clock, reduce power, turn off power, or any combination thereof with respect to a portion of a circuit or all components of a circuit. Further, power management circuit 580 may turn on a clock, increase a clock rate, turn on power, increase power, or any combination thereof in response to a transition from an inactive state to an active state (such as when processor 565 makes a transition from a low power or idle or sleep state to a normal operating state).

Link 560 may be coupled to one or more circuits 600 through a serial interface 595. One or more circuits coupled to link 560 may communicate with circuit 600 through serial interface 595. As one of ordinary skill in the art will appreciate, the circuit 600 may use one or more serial protocols such as SMBUS, I₂C. SPI, etc.

Link 560 may be coupled to one or more peripheral devices 590 through I/O circuitry 585. Through the I/O circuitry 585, one or more peripheral devices 590 may be coupled to the link 560 and, thus, may communicate with other modules coupled to the link 560, such as the processor(s) 365, the memory circuitry 625, and so on.

In an exemplary embodiment, peripheral devices 590 may include various circuits, modules, and the like. Examples include I/O devices (keypads, keyboards, speakers, display devices, storage devices, timers, etc.). It should be noted that in some embodiments, some of peripherals 590 may be external to IC 550. Examples include a keypad, a speaker, etc.

In some embodiments, I/O circuitry 585 may be bypassed with respect to some peripherals. In such embodiments, some peripheral devices 590 may be coupled to link 560 and communicate with link 560 without the use of I/O circuitry 585. It should be noted that, as described above, in some embodiments, such peripheral devices may be external to IC 550.

Link 560 may be coupled to analog circuit 620 through data converter 605. The data converter 405 may include one or more ADCs 615 and/or one or more DACs 200. ADC 615 receives analog signals from analog circuitry 620 and converts the analog signals to a digital format so that they communicate with one or more modules coupled to link 560.

Instead, DAC(s) 200 receive one or more digital signals from one or more modules coupled to link 560 and convert the digital signal(s) to an analog format. Analog signal(s) may be provided to circuitry within IC 550 (e.g., analog circuitry 620) or circuitry external to IC 550, as desired.

Analog circuitry 620 may include various circuitry to provide and/or receive analog signals. Examples include sensors, transducers, and the like, as will be understood by those of ordinary skill in the art. In some embodiments, analog circuitry 620 may communicate with circuitry external to IC 550 to form more complex systems, subsystems, control modules, and information processing modules, as desired.

Control circuitry 570 is coupled to link 560. Accordingly, control circuitry 570 may communicate with various modules coupled to link 560 and/or control the operation of various modules coupled to link 560. Additionally or alternatively, control circuitry 570 may facilitate communication or cooperation between various modules coupled to link 560. In some embodiments, the functions or lines of the control circuitry (e.g., controller 359 described above) in DAC 200 may be combined with the functions or lines of control circuit 570, or the functions or lines of the control circuitry (e.g., controller 359 described above) in DAC 200 may be included in the functions or lines of control circuit 570, as desired.

Referring again to fig. 12, in some embodiments, the control circuit 570 may initiate or respond to a reset operation. As one of ordinary skill in the art will appreciate, the reset operation may result in a reset of one or more modules or the like of link 560 coupled to IC 550. For example, control circuitry 570 may cause DAC(s) 200 to reset to an initial state.

In an exemplary embodiment, the control circuit 570 may include various types of circuits and modules of various circuits. In some embodiments, the control circuitry 570 may include logic circuitry, a Finite State Machine (FSM), or other circuitry to perform various operations, such as the operations described above.

Communication circuit 640 is coupled to link 560 and is also coupled to a circuit or module (not shown) that is external to IC 550. Through communication circuitry 640, various modules coupled to link 560 (or, in general, IC 550) may communicate with external circuits or modules (not shown) through one or more communication protocols. Examples include Universal Serial Bus (USB), ethernet, etc. As one of ordinary skill in the art will appreciate, in the exemplary embodiment, other communication protocols may be used depending on factors such as the specifications for a given application.

As described above, the memory circuit 625 is coupled to the link 560. Thus, the memory circuit 625 may communicate with one or more modules coupled to the link 560, such as the processor(s) 365, control circuitry 570, I/O circuitry 585, and so on. In the illustrated embodiment, the memory circuit 625 includes a control circuit 610, a memory array 635, and a direct access memory (DMA) 630.

The control circuit 610 controls or oversees various operations of the memory circuit 625. For example, control circuitry 619 may provide a mechanism to perform memory read or write operations over link 360. In an exemplary embodiment, the control circuit 610 may support various protocols such as Double Data Rate (DDR), DDR2, DDR3, and the like, as desired.

In some embodiments, memory read and/or write operations involve the use of one or more modules in IC 550, such as memory(s) 565. DMA 630 allows for improved performance of memory operations in some cases. More specifically, DMA 630 provides a mechanism for performing memory read and write operations directly between a data source or destination and memory circuit 625, rather than through a module such as processor(s) 565.

The memory array 635 may include various memory circuits or modules. In the illustrated embodiment, the memory array 635 includes volatile memory 635A and non-volatile (NV) memory 635B. In some embodiments, the memory array 635 may include volatile memory 635A. In some embodiments, the memory array 635 may include NV memory 635B.

NV memory 635B may be used to store information related to the performance or configuration of one or more modules in IC 550. For example, as described above, NV memory 635B may store configuration information related to offset or gain trimming of DAC(s) 200.

According to an exemplary embodiment, a DAC having advantages such as those described above may prove beneficial in various applications. Examples include applications that specify some or all of the attributes listed above, such as monotonicity and relatively high resolution, e.g., 12 bits.

One example application includes a data processing application that processes an analog input signal, as depicted by circuit arrangement 700 in fig. 13. More specifically, the processing circuit 705 (or in general a digital signal source, e.g., MCU, CPU, microprocessor, etc.) provides a digital signal at an output 705A. The digital signal is provided to DAC 200. The DAC 200 converts the digital signal to an analog signal and provides the analog signal at an output 221. The analog signal flows into an analog destination 710 (e.g., transducer, driver, amplifier, etc.). Thus, a digital information source such as processing circuit 708 may control or communicate with analog destination 710 using DAC 200.

In another application, a DAC according to an exemplary embodiment may be used to implement a control system 750 as shown in FIG. 14. Control system 750 includes a process 765, which process 765 includes a simulation source 755 and a simulation destination 710. An analog source 755, such as a sensor or transducer, provides an analog signal to ADC 760. The ADC 760 converts the analog signal into a digital signal and provides the digital signal to the control circuit 760.

For example, the control circuit 760 processes the digital signal by filtering, amplifying or scaling, delaying, etc. Control circuit 760 provides a digital output signal and provides the digital output signal to DAC 200. The DAC 200 converts the digital output signal of the control circuit 760 into an analog signal, which is available at the output 221. The analog signal at the output of the DAC 200 is provided to an analog destination, such as a transducer, driver, motor or other electromechanical device. Thus, the combination of modules shown in system 750 implements a feedback control loop.

In general, applications that use one or more DACs in a feedback loop (e.g., a servo system) may benefit from using a DAC, according to various embodiments. Fig. 15 illustrates a circuit arrangement 780 showing such a configuration. More specifically, the feedback loop includes a source 785 that provides an output signal to the control circuit 760. In response, control circuit 760 generates and provides a digital signal to DAC 200.

DAC 200 converts a digital signal received from control circuit 760 to generate an analog signal at output 221. The analog output signal of DAC 200 flows into driver 790. The driver 790 drives the source 785 (e.g., by providing one or more drive signals), thus completing the loop.

A more specific example of a feedback loop that employs a DAC according to an exemplary embodiment may be a communication system. More specifically, a DAC may be used in a feedback loop to control the intensity of a light source used in an optical communication system. Fig. 16 shows such a communication system 800 using this scheme.

More specifically, communication system 800 includes a source 805, a medium 830, and a destination 835. A source 805, typically a transmitter (or transceiver), provides an information signal to a medium 830, e.g., an optical fiber or a collection of optical fibers. The medium 830 provides the information to a destination 835, which destination 835 is typically a receiver (or transceiver) and is typically located remotely from the source 805.

In the illustrated embodiment, source 805 includes a laser 810, and laser 810 generates and provides a beam of light to a beam splitter 815. It should be noted that the beam from laser 810 is typically modulated with information (turned on and off according to a digital bit pattern) using additional circuit blocks (not shown). As described above, beam splitter 815 provides a portion of the input light from laser 810 to medium 830, and medium 830 provides light to destination 835.

In addition, beam splitter 815 provides a portion of the input light from laser 810 to controller 820. In other words, controller 820 receives an optical signal indicative of the intensity of the optical beam output from laser 810. In response to input light from beam splitter 815, controller 820 generates a digital signal that is ultimately used to drive laser 810.

More specifically, the DAC 200 converts a digital signal from the controller 820 into an analog signal, which is provided at the output 221. The analog output signal of DAC 200 flows into driver 825. In response, driver 825 provides a bias voltage to laser 810 to cause laser 810 to provide an output beam having a desired intensity.

As described above, controller 820 receives a measure of the intensity of the light beam provided by laser 810 by receiving a signal from beam splitter 815. By comparing the signal from the beam splitter 815 with a reference signal, the controller 820 provides a digital signal to the DAC 200, which ultimately causes the driver 825 to increase or decrease the bias voltage provided to the laser 810 in order to adjust the intensity of the output light from the laser 810.

With reference to the figures, those of ordinary skill in the art will note that the various modules shown may primarily depict conceptual functions and signal flow. An actual circuit implementation may or may not contain separately identifiable hardware for the various functional blocks and may or may not use the specific circuitry shown. For example, the functions of the various modules may be combined into one circuit module, as desired. Furthermore, the functionality of a single module may be implemented in several circuit modules, as desired. The choice of circuit implementation depends on various factors, such as the particular design and performance specifications for a given implementation. Other modifications and alternative embodiments in addition to those described herein will be apparent to those of ordinary skill in the art. Accordingly, this description teaches those skilled in the art the manner of carrying out the disclosed concepts and should be construed as illustrative only. As will be appreciated by those of ordinary skill in the art, the drawings may or may not be to scale, where applicable.

The forms and embodiments illustrated and described should be taken as illustrative embodiments. Various changes in the shape, size and arrangement of parts may be made by those skilled in the art without departing from the scope of the concepts disclosed herein. For example, persons skilled in the art may substitute equivalent elements for the elements illustrated and described here. Moreover, persons skilled in the art may use certain features of the disclosed concepts independently of the use of other features, without departing from the scope of the disclosed concepts.

Claims (20)

1. A device to fine tune an offset, comprising:

a first circuit comprising a first transconductance stage to generate a first current, the first circuit having an output offset;

an offset trimming circuit, comprising:

a second circuit that provides an output voltage selectable from a plurality of voltage values; and

a second transconductance stage that generates a second current in response to the output voltage of the second circuit;

wherein the output offset of the first circuit is trimmed by adding the second current to the first current.

2. The apparatus of claim 1, wherein the first circuit comprises a buffer.

3. The apparatus of claim 1, wherein the first circuit comprises an interpolator.

4. The apparatus of claim 1, wherein the first transconductance stage and the second transconductance stage have corresponding transconductance values, and wherein a transconductance of the second transconductance stage is less than a transconductance of the first transconductance stage.

5. The apparatus of claim 1, wherein the second circuit in the offset trimming circuit comprises at least one resistor coupled to a current source.

6. The apparatus of claim 5, wherein the at least one resistor comprises a plurality of taps to provide the plurality of voltage values, and wherein the second circuit in the offset trimming circuit further comprises a plurality of switches coupled to respective taps in the at least one resistor.

7. The apparatus of claim 6, further comprising a controller that selectively controls the set of switches to provide the output voltage.

8. The apparatus of claim 1, wherein the first circuit is a buffer in a digital-to-analog converter (DAC) that converts a digital signal to an analog signal having monotonicity.

9. The device of claim 1, wherein the first circuit is an interpolator in a DAC that converts a digital signal to an analog signal having monotonicity.

10. A device to fine tune an offset, comprising:

a digital-to-analog converter (DAC) that converts a digital input signal to an analog output signal, the DAC comprising:

a buffer that buffers a voltage and provides a reference voltage;

a Resistor DAC (RDAC) that provides a first voltage and a second voltage in response to a first set of control signals and the reference voltage;

an interpolator coupled to receive the first voltage and the second voltage and to provide a first analog signal in response to a second set of control signals, the interpolator having a trimmable offset voltage; and

an offset trimming circuit comprising a first transconductance stage to provide a first current to the interpolator to trim the offset voltage of the interpolator.

11. The apparatus of claim 10, wherein the buffer has a programmable offset voltage, and wherein the offset trimming circuit further comprises a second transconductance stage to provide a second current to the buffer to trim the offset voltage of the buffer.

12. The apparatus of claim 11, wherein the offset trimming circuit further comprises a first resistor having a first plurality of taps coupled to a first plurality of respective switches to provide a first selectable voltage to the first transconductance stage.

13. The apparatus of claim 12, wherein the offset trimming circuit further comprises a second resistor having a second plurality of taps coupled to a second plurality of corresponding switches to provide a second selectable voltage to the second transconductance stage.

14. The apparatus of claim 11, wherein the interpolator comprises a transconductance stage having a higher transconductance than a transconductance of the first transconductance stage, and wherein the buffer comprises a transconductance stage having a higher transconductance than a transconductance of the second transconductance stage.

15. A method of fine tuning an offset, the method comprising:

generating a first current by using a first transconductance stage in a first circuit, the first circuit having an output offset;

providing a voltage selectable from a plurality of voltage values;

generating a second current in response to the voltage by using a second transconductance stage; and

fine-tuning the output offset of the first circuit by adding the second current to the first current.

16. The method of claim 15, wherein the first circuit comprises a buffer.

17. The method of claim 15, wherein the first circuit comprises an interpolator.

18. The method of claim 15, wherein the first transconductance stage and the second transconductance stage have respective transconductance values, and wherein a transconductance of the second transconductance stage is less than a transconductance of the first transconductance stage.

19. The method of claim 15, wherein generating the second current further comprises providing a selectable voltage generated by a resistor coupled to a current source to the second transconductance stage.

20. The method of claim 19, wherein providing the selectable voltage to the second transconductance stage further comprises selectably controlling a set of switches coupled to a corresponding set of taps in the resistor.

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