CN106156375B - A kind of memory compiler joining method and memory - Google Patents
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Abstract
This application discloses a kind of memory compiler joining methods, comprising: determines signal by the number n of the delay time of wordline driving to distalmost end storage unit and the Fin of the driving MOS of columns n and the wordline driving of storage unitWLDBetween functional relation；N array storage unit is divided into i sections, in nWLDValue range in the delay tn/i of n/i array storage unit is calculated；When the delay tn/i is less than the first preset value, the corresponding n of above-mentioned delay tn/i is obtainedWLD, it is denoted as nmeet；A buffer is inserted between every two sections of storage units, wordline driving is driven to n with each buffermeetA Fin；Assembled domain, it is seen that the number using the Fin of the wordline driving and buffer of storage unit obtained by the above method is optimal value, therefore enhances the area utilization of memory, reduces area loss.
Description
Technical field
This application involves memory technology fields, more specifically to a kind of memory compiler joining method and deposit
Reservoir.
Background technique
Memory in the design process, is usually divided into each functional module (leaf by existing memory compiler
Cell), depending on the circuit size in functional module is according to the worst case of array.Then with program according to configuration parameter, splicing
Multiple functional modules are finally combined into a memory by each functional module.In this process, the large scale in memory
Device is in accordance with to be set under the worst case of array, cannot track the line number of array and the variation of columns, therefore, using existing
Area (Performance, power, the area-abbreviation PPA) waste for the memory for thering is the technical solution in technology to generate, together
When also will increase power consumption of memory.
Summary of the invention
In view of this, the application provides a kind of memory compiler joining method, for solving memory in the prior art
Area loss the problem of.
To achieve the goals above, it is proposed that scheme it is as follows:
A kind of memory compiler joining method, comprising:
Determine signal by wordline driving to the delay time of distalmost end storage unit and the columns n and wordline of storage unit
The number n of the Fin of the driving MOS of drivingWLDBetween functional relation, wherein the nWLDFor a dispersion number；
The n array storage unit is divided into default section, in nWLDValue range in, according to the functional relation calculate
The minimum delay time of every section of storage unit obtains the minimum and prolongs when the minimum delay time is less than the first preset value
When time corresponding nWLD, it is denoted as preferred value, the preferred value is wordline driving and every two sections of storages in the memory
The Fin number of the driving MOS of buffer between unit；
Assembled Fin is the domain of the wordline driving and buffer of preferred value.
Preferably, above-mentioned memory compiler joining method, further includes:
When the minimum delay time is not less than the first preset value, the equal segments of the n array storage unit adds 1, directly
To in nWLDValue range in, the minimum delay time of every section of storage unit is less than the first preset value.
Preferably, in above-mentioned memory compiler joining method, the signal is driven to distalmost end by memory word line and is deposited
The number n of the Fin of the delay time of storage unit and the columns n of storage unit and wordline driving MOSWLDBetween functional relation,
Are as follows:
Wherein, t0 is delay time of the signal by memory word line driving to distalmost end storage unit, RC_WLIt is single for storage
The resistance value of first bit line, CC_WLFor the capacitance of storage unit bit line, a and b are constant.
Preferably, in above-mentioned memory compiler joining method, further includes:
The line number m of the memory compiler is tracked, specifically:
Calculate the resistance R of the pull-up PMOS of memoryC_PUWith the resistance R for writing drivingWRDWith m line storage unit
Resistance RC_BLThe sum of ratio T, wherein it is describedThe nWRDFor write driving NMOS Fin
Number, c is fixed value；
In nWRDValue range in, calculate so that the ratio T be greater than the second preset value the NMOS for writing driving minimum
The number of Fin, is denoted as nWRD1；
Assembled Fin is nWRD1The domain for writing driving.
Preferably, in above-mentioned memory compiler joining method, further includes:
It is tracked using line number m and columns n of the sequential control circuit to the memory compiler, specifically:
Determine the functional module number p and phase inverter of the delay t1 and inverter drive of the sequential control circuit of memory
Fin number nDriverBetween functional relation, wherein the nDriverFor a dispersion number；
It asks in the nDriverValue range in so that the minimum number of the Fin when delay t1 meets timing requirements
Mesh is denoted as nDriver1；
Assembled Fin is nDriverlSequential control circuit domain.
Preferably, in above-mentioned memory compiler joining method, the delay t1 and phase inverter of the sequential control circuit are driven
The number n of the Fin of dynamic functional module number p and phase inverterDriverBetween functional relation be
Wherein, described d, e are fixed value, the CleafcellFor
The capacitor for the functional module that phase inverter is driven, the RleafcellBy the connection resistances for the functional module that phase inverter drives.
A kind of memory, the memory are assembled using above-mentioned any one memory compiler joining method
Memory.
It can be seen from the above technical scheme that in memory compiler joining method disclosed in the present application, by institute
The columns n for stating memory compiler is tracked, so that the number of the Fin of the WL Driver and Buffer of storage unit are
Optimal value so that the size of the WL Driver and Buffer is optimal, therefore enhances the area utilization of memory, reduces
Area loss.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the structure chart of existing 3D transistor；
Fig. 2 is the long line model of the WL Driver in memory compiler disclosed in the embodiment of the present application；
Fig. 3 is the flow chart of the disclosed method tracked to the columns of memory compiler of the embodiment of the present application；
Fig. 4 is the long wire model figure for writing driving Write Driver worst case of memory compiler；
Fig. 5 is the disclosed method flow diagram tracked to the line number m of memory compiler of the embodiment of the present application；
Fig. 6 is that the timing of memory tracks the structure chart of circuit；
Fig. 7 is the long line illustraton of model for the large scale phase inverter that timing is tracked in circuit；
Fig. 8 is the disclosed line number m and column using sequential control circuit to the memory compiler of the embodiment of the present application
The flow chart that number n is tracked.
Specific embodiment
Depending on the circuit size in memory function module in the prior art is directed to according to the worst case of array, from
And the problem of causing the area loss of memory, this application discloses a kind of memory compiler joining method and memories.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Under fin field-effect transistor (Fin Field-Effect Transistor, FinFET) technique, MOS device
Channel length is fixed, width can only quantification value.Therefore user can customize the size of MOS device, can be to MOS device
Carry out computer control.Therefore original memory compiler technology can optimize reform under FinFET technique.
As shown in Figure 1, the FinFET in Fig. 1 is 3D transistor (metal-oxide-semiconductor), referring to the ditch of the 3D transistor in Fig. 1
Road length is fixed value, width can only quantized value, therefore the size of the metal-oxide-semiconductor is determined by the total number of Fin:
FinSum=Fin1Finger* Finger, metal-oxide-semiconductor are sized at a discrete function, thus can be convenient with computer into
Row processing, control domain arrangement, carries out assembled metal-oxide-semiconductor.Wordline in memory compiler drives (WL Driver), writes driving
Large-size device is provided in (Write Driver), timing tracking circuit (Tracking Path), the WL Driver is used
The wordline of storage unit, the Write Driver are used to drive the position of storage unit in storage array in driving storage array
Line, the Tracking Path are used to control the timing of memory, and applicant utilizes FinFET size by research discovery
The characteristic of discretization may make the size of large-size device to be tracked line number and columns, so that reducing memory
Area loss is possibly realized.
Fig. 2 is the long line model of the WL Driver in memory compiler disclosed in the embodiment of the present application.Wherein, Fig. 2
Shown in RWLDThe resistance of MOS, C are driven for WL DriverWLDThe capacitor of MOS, R are driven for WL DriverC_WLFor storage unit
The resistance of bit line, CC_WLFor the capacitor of storage unit bit line, WL Driver drives altogether n array storage unit, and the t0 is signal
By the delay time of the storage unit of WL Driver to distalmost end, the t0=f (nWLD, n), wherein the nWLDFor WL
Driver drives total mesh number of the Fin of MOS, and the nWLDFor a dispersion number.
Based on the signal by WL Driver to distalmost end storage unit delay time t0 and the WL Driver
Drive total mesh number n of the Fin of MOSWLDFunctional relation between the columns n of storage unit, this application discloses a kind of memories
Compiler joining method is tracked by the columns to memory compiler, reaches the mesh of the PPA of optimization memory compiler
's.
Fig. 3 is the disclosed method tracked to the columns of memory compiler of the embodiment of the present application.
Referring to Fig. 1, this method comprises:
The columns n of the memory compiler is tracked, specifically:
Step S301: determine signal by wordline driving to the delay time t0 of distalmost end storage unit and the column of storage unit
The number n of the Fin of number n and the driving MOS of wordline drivingWLDBetween functional relation；
Step S302: the n array storage unit is divided into i sections, i=1；
Step S303: in nWLDValue range in, the minimum delay time tn/i of n/i array storage unit is calculated；
Step S304: judge the minimum delay time tn/i whether less than the first preset value ttarget, if it is executing step
Rapid S306, if not, executing step S305, the first preset value ttargetSize according to depending on user demand:
Step S305: so that i=i+1, continues to execute step S303；
In nWLDValue range in, continue the minimum delay time tn/i that n/i array storage unit is calculated, until sentence
The minimum delay time tn/i that breaks is less than the first preset value ttarget；
Step S306: if the minimum delay time tn/i is less than the first preset value ttarget, obtain so that the minimum
Wordline delay time tn/i corresponding when being minimum value drives the number (n of the Fin of MOSWLD), it is denoted as nmeet；
Step S307: being inserted into a buffer Buffer between every two sections of storage units, wordline driving and each described slow
Fin number for rushing the driving of device Buffer is nmeet；
Step S308: assembled Fin is nmeetWordline driving and buffer domain.
Shown in Fig. 3, n firstWLDIn the number license value range of Fin, the minimum delay of n storage unit is obtained, such as
Fruit is less than target (the first preset value) ttarget, then the smallest Fin value for meeting constraint condition is sought in value range；If
Greater than the first preset value ttarget, then average segmentation is carried out, asks every section of minimum delay, and every section of minimum delay is preset with first
Value ttargetIt is compared, if less than the first preset value ttarget, then the minimum Fin value for meeting constraint condition is sought, is otherwise continued point
Section is gone down, and until meeting targeting constraints, (every section of minimum delay is less than the first preset value ttarget) until.It selects always in this way
To the segments for the condition that meets and the value of Fin, select always it is optimal as a result, therefore every section altogether whole delay then exist
It is also the smallest for meeting under constraint condition.
Wherein, the above method can be referred to as greedy algorithm, can be imitative with simulation to the iteration of greed selection for this
It is really solved, under limited, the discrete value of Fin, operation emulation obtains corresponding delay, by obtained delay and first
Preset value is compared, if terminating emulation less than the first preset value, then carries out operation to delay；It is pre- if more than first
If value, then be segmented the n array storage unit, continue under discrete value, it is corresponding that emulation obtains every section of storage unit
Delay, subsequent iteration and so on, until every section of storage unit it is corresponding delay less than the first preset value when until.Then
It is inserted between every two sections of storage units with buffer Buffer, the value of Fin determines the size of WL Driver and Buffer.No
Same columns (n) obtains corresponding segments and the value n of Finmeet, by computer generate corresponding WL Driver and
The domain of Buffer, such memory compiler can track the variation of columns, so that the WL Driver of each memory
PPA can be optimal.
Referring to disclosed in the above embodiments of the present application, to the method that the columns n of the memory compiler is tracked, deposit
The number of the Fin of the WL Driver and Buffer of storage unit are optimal value, so that the WL Driver and Buffer
Size it is optimal, to enhance the area utilization of memory, reduce area loss.
It is understood that referring to fig. 2, the delay time t0 by memory word line driving to distalmost end storage unit
With the number n of the Fin of columns n and wordline the driving MOS of storage unitWLDBetween functional relation, are as follows:
If whereinDescribed a, b are constant, then:
Wherein RC_WLFor the resistance value of storage unit bit line, CC_WLFor the capacitance of storage unit bit line；
Therefore, the t0 and n and n can be acquiredWLDBetween functional relation are as follows:
Fig. 4 is the long wire model figure for writing driving Write Driver worst case of memory compiler.Wherein, shown
RC_PUFor the resistance of the pull-up PMOS of storage unit, RC_BLFor the resistance of storage unit BL, CC_BLFor storage unit bit line BL (bit
Line capacitor), RWRDFor the resistance for writing driving (Write Driver), m is the line number of storage unit.It is when needing that storage is single
When member writes overturning, the ratio of resistance needs to meet condition:
The wherein λflipFor the second preset value.
Wherein, if the number of the Fin of the NMOS of the Write Driver is nWRD, then, describedIt is described
C is constant, then above-mentioned formula can be deformed into:
Fig. 5 is the disclosed method flow diagram tracked to the line number m of memory compiler of the embodiment of the present application.
It is understood that in order to advanced optimize the PPA of memory, in the above-mentioned columns to the memory compiler
On the basis of n is tracked, can also the line number m to memory compiler track, referring to fig. 4 and Fig. 5, detailed process
Are as follows:
Step S501: the resistance R of the pull-up PMOS of memory is calculatedC_PUWith the resistance R for writing drivingWRDWith m row
The resistance R of storage unitC_BLThe sum of ratio T；
Step S502: in nWRDValue range in, calculate so that the ratio T is greater than the driving of writing of the second preset value
The number of the minimum Fin of NMOS, is denoted as nWRD1；
Step S503: assembled Fin is nWRD1The domain for writing driving.
As it can be seen that analyzing by setting the specific structure for writing driving of the memory editing machine, described deposit is obtained
The resistance R of the pull-up PMOS of reservoirC_PUWith the resistance R for writing drivingWRDWith the resistance R of m line storage unitC_BLIt
The ratio T of sum, meanwhile, analysis obtains the resistance R for writing drivingWRDWith the Fin's of the NMOS of the Write Driver
Number nWRDBetween relationship, thus by bringing into obtain, the number n of the Fin of the NMOS of the Write DriverWRDWith it is described
The minimum n so that when the ratio T meets preset condition can be obtained by analytical calculation for relationship between ratio TWRDTake
Value, to achieve the purpose that be tracked the line number m of reservoir compiler, so that the size of the Write Driver is most
It is excellent, to further enhance the area utilization of memory, reduce area loss.
Fig. 6 is that the timing of memory tracks the structure chart of circuit.Wherein, Cell memory function module in figure, the WL
FMS is the timing triggers of WL signal, and the SA FSM is the timing triggers of SAEN signal.
Referring to Fig. 6, the timing tracks circuit at work, when the shown end CK gets the rising edge of clock signal,
Triggering WLEN is set to ' 1 ', so that shown DWL is also set to ' 1 ' unlatching phase inverter, RBL starts to discharge, and finally WL_END is become
' 1 ' resetting WL FSM, corresponding WLEN, which sets ' 0 ', DWL and set ' 0 ', RBL and revert to ' 1 ', WL_END, sets ' 0 ', terminates the timing of WL
Tracking；When WL_END is set to ' 1 ', open SA timing tracking, SAEN set ' 1 ', SA_END set ' 1 ' resetting SA FSM make
SAEN is ' 0 ', and then SA_END also becomes ' 0 ', terminates the timing tracking of SA.Drive one long company of inverter drive of WLEN
Line, signal delay are influenced by the line number (m) of storage array in memory；One long line of inverter drive of RBL is driven,
Delay is equally influenced by the line number (m) of storage array in memory；The long line of inverter drive of SAEN is driven, delay is deposited
The influence of the columns (n) of storage array in reservoir；The long line of inverter drive of SA_END is driven, is delayed equally by memory
Store the influence of columns (n).And these above-mentioned phase inverters are large-size device, influence the whole timing of memory.It is existing
The timing tracking circuit of memory compiler is only designed the worst case of array, causes array in the case of other in this way
Timing tracking be not it is most suitable so that timing tracking circuit PPA be not it is optimal, increase memory area wave
Take.
Fig. 7 is the long line model for the large scale phase inverter that timing is tracked in circuit.
The PPA for being directed to timing tracking circuit in memory is not optimal problem, and applicant establishes as shown in Figure 7
Long line model, wherein shown RDriverFor the MOS resistance for driving phase inverter, shown CDriverFor the MOS electricity for driving phase inverter
Hold, the RleafcellFor the connection resistances of memory function module, the CleafcellFor the capacitor of memory function module, institute
The number for the memory function module that p is connected for driving phase inverter is stated, the delay t1 is anti-to driving by driving phase inverter
The delay time for the farthest functional module that phase device is connected.
It can be obtained by calculating analysis, the delay:
If driving the number of the Fin of MOS in above-mentioned long line is nDriver, then described
Described d, e are constant.Then above-mentioned formula can be deformed into:
By above-mentioned formula, described in nDriverValue range in, acquire the smallest driving for meeting delay requirement
The size of MOS, and it is assembled into corresponding domain, so that the PPA of above-mentioned long line driving optimizes, this solution
Process can be solved with analog simulation: in discrete nDriverSize value range in, the delay t of simulated measurement correspondingly-sized
Value, compares timing requirements, obtains meeting the n that condition obtains minimum dimensionDriver, and assembled corresponding domain.Therefore tracking timing chases after
The line number of track circuit and the variation of columns, the timing of each memory of generation are tracked circuit from being in harmony, are deposited to reduce
The area loss of reservoir.
Specifically, referring to Fig. 8, using sequential control circuit to the memory compiler in the above embodiments of the present application
The method that line number m and columns n are tracked, concretely:
Step S801: the functional module number p of the delay t1 and inverter drive of the sequential control circuit of memory are determined
And the number n of the Fin of phase inverterDriverBetween functional relation, wherein the nDriverFor a dispersion number；
Step S802: it asks in the nDriverValue range in so that the delay t1 is when meeting preset condition
The minimal amount of Fin, is denoted as nDriver1, i.e., so that the t1 be less than predetermined value when Fin minimal amount；
Step S803: assembled Fin is nDriver1Sequential control circuit domain.
It is understood that corresponding to method disclosed in the above embodiments of the present application, disclosed herein as well is a kind of uses
Memory made of any one of the above method.
A kind of memory, which is characterized in that the memory is to use above-mentioned any one memory compiler splicing side
The assembled memory of method.
It is understood that memory disclosed in the embodiment of the present application can be using the WL Driver in memory to depositing
The columns of reservoir is tracked and/or is tracked and/or uses using line number of the Writer Driver to memory timing control
Circuit processed is all tracked line number and columns, therefore can be tracked customization to the large-size device in memory, thus
So that the whole PPA of each memory is optimal.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (6)
1. a kind of memory compiler joining method characterized by comprising
Determine that signal is driven by the delay time of wordline driving to distalmost end storage unit and the columns n and wordline of storage unit
Driving MOS Fin number nWLDBetween functional relation, the nWLDFor a dispersion number；
The n array storage unit is divided into default section, in nWLDValue range in, calculate every section according to the functional relation
The minimum delay time of storage unit, when the minimum delay time is less than the first preset value, when obtaining the minimum delay
Between corresponding nWLD, it is denoted as preferred value, the preferred value is wordline driving and every two sections of storage units in the memory
Between buffer driving MOS Fin number；
Assembled Fin is the domain of the wordline driving and buffer of preferred value；
The signal is driven by memory word line to the delay time of distalmost end storage unit and the columns n and word of storage unit
Line drives the number n of the Fin of MOSWLDBetween functional relation are as follows:
Wherein, t0 is delay time of the signal by memory word line driving to distalmost end storage unit, RC_WLFor storage unit bit line
Resistance value, CC_WLFor the capacitance of storage unit bit line, a and b are constant.
2. memory compiler joining method according to claim 1, which is characterized in that further include:
When the minimum delay time is not less than the first preset value, the equal segments of the n array storage unit adds 1, until
nWLDValue range in, the minimum delay time of every section of storage unit is less than the first preset value.
3. memory compiler joining method according to claim 1, which is characterized in that further include:
The line number m of the memory compiler is tracked, specifically:
Calculate the resistance R of the pull-up PMOS of memoryC_PUWith the resistance R for writing drivingWRDWith the resistance of m line storage unit
Resistance value RC_BLThe sum of ratio T, wherein it is describedThe nWRDFor write driving NMOS Fin number, c is
Fixed value；
In nWRDValue range in, calculate so that the ratio T be greater than the second preset value the NMOS for writing driving minimum Fin
Number, be denoted as nWRD1；
Assembled Fin is nWRD1The domain for writing driving.
4. memory compiler joining method according to claim 1, which is characterized in that further include:
It is tracked using line number m and columns n of the sequential control circuit to the memory compiler, specifically:
Determine the delay t1 of the sequential control circuit of memory and the functional module number p and phase inverter of inverter drive
The number n of FinDriverBetween functional relation, wherein the nDriverFor a dispersion number；
It asks in the nDriverValue range in so that it is described delay t1 timing requirements when Fin minimal amount, be denoted as
nDriver1；
Assembled Fin is nDriver1Sequential control circuit domain.
5. memory compiler joining method according to claim 4, which is characterized in that the sequential control circuit prolongs
When t1 and inverter drive functional module number p and phase inverter Fin number nDriverBetween functional relation beWherein, described d, e are fixed value, the CleafcellFor reverse phase
The capacitor for the functional module that device is driven, the RleafcellBy the connection resistances for the functional module that phase inverter drives.
6. a kind of memory, which is characterized in that the memory is to be compiled using the claims 1-5 any one memory
The assembled memory of device joining method.
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