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CN105870165A - 一种势垒层组分渐变的InAlN/GaN HEMT器件 - Google Patents

一种势垒层组分渐变的InAlN/GaN HEMT器件 Download PDF

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CN105870165A
CN105870165A CN201610348582.1A CN201610348582A CN105870165A CN 105870165 A CN105870165 A CN 105870165A CN 201610348582 A CN201610348582 A CN 201610348582A CN 105870165 A CN105870165 A CN 105870165A
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任舰
顾晓峰
闫大为
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Jiangnan University
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01ELECTRIC ELEMENTS
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract

本发明公开了一种势垒层组分渐变的InAlN/GaN HEMT器件。该器件包括衬底材料上依次形成的GaN成核层,GaN缓冲层,AlN插入层,In组分渐变InAlN势垒层,GaN帽层,SiN钝化层以及其上形成的栅极、源极和漏极,其特征是底层In0.17Al0.83N势垒与GaN材料形成晶格匹配,通过逐层增加In组分,增加极化效应产生的二维电子气浓度,提高器件的饱和电流和输出功率。本发明在减少异质界面形成线性位错和抑制逆压电效应的同时,有效提高了InAlN/GaN HEMT器件的电学性能。

Description

一种势垒层组分渐变的InAlN/GaN HEMT器件
技术领域
本发明涉及半导体功率器件制造领域,尤其涉及一种势垒层组分渐变的InAlN/GaNHEMT器件。
背景技术
与传统窄禁带半导体相比,以GaN为代表的宽禁带III族氮化物半导体具有高击穿电场、高电子饱和速度与高热稳定性等优越的电学特性。尤其是压电与自发极化效应显著的AlGaN/GaN异质结,能在界面处诱导高浓度的二维电子气(2DEG),是HEMT的核心结构。目前,已报道的AlGaN/GaN HEMT的截止频率超过100GHz,最大输出功率接近10W/mm。但是,由于AlGaN和GaN两种材料之间存在晶格失配,材料生长过程中会引入的大量的线性位错,导致器件漏电流比理论值大很多。很多针对AlGaN/GaN HEMT栅反向漏电流电流的研究指出,异质界面之间的线性位错是其漏电流的主要输运通道。除此之外,因晶格失配引起的逆压电效应也被认为是造成AlGaN/GaN HEMT诸多可靠性问题的主要原因。因此,减少异质界面形成的线性位错和抑制甚至消除势垒层逆压电效应对提高器件性能十分重要。
目前,最有效的一种解决办法是在GaN外延片上直接生长与之晶格匹配的In0.17Al0.83N势垒层。尽管没有压电极化效应,其强自发极化也能够在异质界面诱发大量的2DEG,提供较大的饱和电流和输出功率。但是,研究表明势垒层材料组分改变可以明显影响异质界面诱发的2DEG浓度。而2DEG浓度的高低直接影响形成器件的饱和电流和输出功率的高低。而组分固定的晶格匹配结构将势垒层In组分固定为0.17,该组分获得的2DEG浓度并不是最高。很明显,为了实现晶格匹配,组分固定晶格匹配结构在器件的部分电学性能方面未能达到最佳。
本发明的目的就是针对现有技术上的不足,提供一种势垒层组分渐变的InAlN/GaNHEMT器件。实现底层In0.17Al0.83N势垒与GaN材料晶格匹配、减少异质界面形成线性位错和抑制逆压电效应的同时,通过提高其他层势垒的In组分,增强自发极化效应产生的2DEG浓度,提高器件的饱和电流和输出功率。该器件结构减少异质界面形成的线性位错和抑制逆压电效应的同时,提高了器件的饱和电流和输出功率。不仅考虑了器件的可靠性,同时提升了器件的电学性能。
发明内容
鉴于现有技术存在的不足,本发明的目的旨在提供一种势垒层组分渐变的InAlN/GaNHEMT器件,该器件采用底层In0.17Al0.83N势垒与GaN材料实现晶格匹配,通过逐渐增加势垒层In组分,增加极化效应产生的2DEG浓度,提高器件的饱和电流和输出功率。
本发明通过如下技术方案实现:
为达到上述目的,本发明提供了一种势垒层组分渐变的InAlN/GaN HEMT器件,主要包括衬底材料上依次形成的GaN成核层,GaN缓冲层,AlN插入层,In组分渐变InAlN势垒层,GaN帽层,钝化层以及其上形成的栅极、源极和漏极。该结构中,衬底材料为Si,SiC,蓝宝石或者GaN;GaN成核层厚度为30nm;GaN缓冲层为非故意掺杂,厚度为3μm;AlN插入层厚度为5nm;InAlN势垒分为3-6层,每层厚度为2-5nm。底层势垒In组分为0.17,与GaN实现晶格匹配,其余势垒层In组分逐渐增加,顶层组分不不超过0.32,例如:0.17,0.20,0.23,0.26,0.29,0.32;GaN帽层厚度为2nm;钝化层为SiN,SiO2,或者Si3N4,厚度为150nm;源极和漏极为欧姆接触金属采用Ti/Al/Ti/Au,厚度分别为30nm,120nm,50nm,100nm;栅极金属采用Ni/Au,厚度分别为50nm,300nm;
本发明提供的这种势垒层组分渐变的InAlN/GaN HEMT器件,底层In0.17Al0.83N势垒与GaN材料实现晶格匹配,有效减少材料生长过程中异质界面形成的线性位错,同时抑制了异质界面处的逆压电效应。在保证器件的可靠性前提下,通过逐渐改变势垒层In的组分,进一步提高了器件的饱和电流和输出功率。本发明对于GaN基HEMT器件的制备和提高其电学性能具有重要的意义。
附图说明
图1是本发明势垒层组分渐变的InAlN/GaN HEMT器件的层结构示意图;
图2是势垒层组分固定的的InAlN/GaN HEMT器件的层结构示意图;
图3是势垒层组分渐变和组分固定的两种InAlN/GaN HEMT器件的Id-Vg曲线;
图4是势垒层组分渐变和组分固定的两种InAlN/GaN HEMT器件的Id-Vd曲线。
具体实施方式
下面结合附图和实施例对本发明的技术方案作进一步的说明。
为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明进一步详细说明。
本发明提供的这种势垒层组分渐变的InAlN/GaN HEMT器件,包括衬底材料上依次形成的GaN成核层,GaN缓冲层,AlN插入层,In组分渐变InAlN势垒层,GaN帽层,钝化层以及其上形成的栅极、源极和漏极。
势垒层组分渐变的InAlN/GaN HEMT器件层结构示意图如图1所示。衬底材料为Si,SiC,蓝宝石或者GaN;GaN成核层厚度为30nm;GaN缓冲层为非故意掺杂,厚度为3μm;AlN插入层厚度为5nm;InAlN势垒分为3-6层,每层厚度为2-5nm。底层势垒In组分为0.17,与GaN实现晶格匹配,其余势垒层In组分逐渐增加,顶层组分不不超过0.32,例如:0.17,0.20,0.23,0.26,0.29,0.32;GaN帽层厚度为2nm;钝化层为SiN,SiO2,或者Si3N4,厚度为150nm;源极和漏极为欧姆接触金属采用Ti/Al/Ti/Au,厚度分别为30nm,120nm,50nm,100nm;栅极金属采用Ni/Au,厚度分别为50nm,300nm;势垒层组分固定的InAlN/GaNHEMT器件层结构示意图如图2所示,其势垒层In组分固定,厚度为30nm。制备过程为采用金属有机物化学气相沉积法在衬底材料上逐步生长GaN成核层,GaN缓冲层,AlN插入层,In组分渐变InAlN势垒层,GaN帽层,通过光刻工艺和电子束蒸发工艺定义电极结构,最后生长钝化层来减少表面横向漏电流。值得注意的是,势垒层的In组分和厚度的改变对2DEG的浓度具有一定的影响。随着势垒层In组分和厚度增加,极化效应诱发的2DEG浓度也不断增加。但是,若组分过大,则会引起势垒层应变驰豫,令异质结的材料特性恶化。因此,本发明势垒层的组分和厚度需要分别控制在低于0.32和低于30nm范围内。除此之外,势垒层组分和厚度控制能够获得较高的2DEG迁移率值。这是由于当势垒层组分和厚度增加时会引起2DEG密度增大、分布变窄且更靠近异质界面造成各种散射作用发生变化,反而会降低2DEG浓度。同样条件下,相比于组分固定的InAlN/GaN HEMT器件,本发明提出的势垒层组分渐变InAlN/GaN HEMT具有更大的饱和电流,其输出功率更高(如图3和4所示)。
本发明采用底层In0.17Al0.83N势垒与GaN材料实现晶格匹配,通过逐渐增加势垒层In组分,增强异质界面的自发极化效应诱发的2DEG浓度,来提高了饱和电流和输出功率,实现了对InAlN/GaN HEMT电学性能的提升。由此,该结构有助于GaN基功率器件的制备及其电学性能的提升。对于AlGaN/GaN HEMT器件,晶格失配引起的异质界面线性位错和逆压电效应对严重影响其工作时的可靠性。而实现了晶格匹配的In0.17Al0.83N/GaN HEMT,由于In组分被固定在0.17,其电学性能还有进一步提升的空间。本发明通过采用底层In0.17Al0.83N势垒与GaN材料实现晶格匹配,通过逐渐增加势垒层In组分,实现了对InAlN/GaN HEMT电学性能的进一步提升。同时,控制每层In组分变化较小,减少势垒层之间形成的线性位错和抑制逆压电效应,通过分别控制势垒层In组分和势垒层厚度,获得最佳的电学性能。相比于现有技术,本发明具有如下有益效果:在保证器件的可靠性前提下,通过逐渐改变势垒层In的组分,进一步提高了器件的饱和电流和输出功率。
最后说明的是,以上实施例仅用以说明本发明的技术方案而非限制,尽管参照较佳实施例对本发明进行了详细说明,本领域的普通技术人员应当理解,可以对本发明的技术方案进行修改或者等同替换,而不脱离本发明技术方案的宗旨和范围,其均应涵盖在本发明的权利要求范围当中。

Claims (5)

1.一种势垒层组分渐变的InAlN/GaN HEMT器件,其特征在于:该器件包括衬底材料上依次形成的GaN成核层,GaN缓冲层,AlN插入层,In组分渐变InAlN势垒层,GaN帽层,钝化层以及其上形成的栅极、源极和漏极。
2.根据权利要求1所述的势垒层组分渐变的InAlN/GaN HEMT器件,其特征在于,所述衬底材料为Si,SiC,蓝宝石或者GaN。
3.根据权利要求1所述的势垒层组分渐变的InAlN/GaN HEMT器件,其特征在于,InAlN势垒分为3-6层,每层厚度为2-5nm,总厚度在18nm-30nm范围内。
4.根据权利要求1所述的势垒层组分渐变的InAlN/GaN HEMT器件,其特征在于,底层势垒In组分为0.17,实现与GaN的晶格匹配,其余势垒层In组分逐渐增加,顶层组分不不超过0.32,例如:0.17,0.20,0.23,0.26,0.29,0.32。
5.根据权利要求1所述的势垒层组分渐变的InAlN/GaN HEMT器件,其特征在于,所述钝化层为SiN,SiO2,或者Si3N4
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CN111755510A (zh) * 2019-03-26 2020-10-09 苏州捷芯威半导体有限公司 一种半导体器件及其制备方法
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CN103346068A (zh) * 2013-07-11 2013-10-09 中国科学院半导体研究所 高In组分AlInN薄膜的制备方法
CN205666237U (zh) * 2016-05-24 2016-10-26 江南大学 一种势垒层组分渐变的InAlN/GaN HEMT器件

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CN107123668A (zh) * 2017-04-12 2017-09-01 西安电子科技大学 一种InAs/AlSb HEMT外延结构及其制备方法
CN107123668B (zh) * 2017-04-12 2019-12-13 西安电子科技大学 一种InAs/AlSb HEMT外延结构及其制备方法
CN111755510A (zh) * 2019-03-26 2020-10-09 苏州捷芯威半导体有限公司 一种半导体器件及其制备方法
CN111755510B (zh) * 2019-03-26 2024-04-12 苏州捷芯威半导体有限公司 一种半导体器件及其制备方法
CN113053748A (zh) * 2021-03-12 2021-06-29 浙江大学 GaN器件及制备方法
CN115394842A (zh) * 2022-05-16 2022-11-25 山东大学 一种高功率增益截止频率的InAlN/GaN HEMT及其制备方法

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