CN105336706A

CN105336706A - Preparation method for high voltage LED chip

Info

Publication number: CN105336706A
Application number: CN201410382205.0A
Authority: CN
Inventors: 封�波
Original assignee: Lattice Power Jiangxi Corp
Current assignee: Lattice Power Jiangxi Corp
Priority date: 2014-08-06
Filing date: 2014-08-06
Publication date: 2016-02-17

Abstract

The invention provides a preparation method for a high voltage LED chip. The method mainly comprises the steps of combining with a second substrate by a wafer bonding manner; peeling off a first substrate and a buffer layer to expose an N type GaN layer; forming a plurality of second trenches in a partial region of the N type GaN layer to form GaN micro-crystals arranged at intervals; forming a groove in a partial region of the GaN micro-crystals, wherein the groove is communicated with the second trenches, and the groove reaches a reflective metal layer measured based on the depth of the groove; depositing a second insulating layer on the side wall of the GaN micro-crystals of the second trenches; depositing metals on the N type GaN layer, partial exposed reflective metal layer, the second trenches and the surface of the second insulating layer to form an N electrode, a P electrode and an interlinking metal layer connected with the adjacent LED electrodes to form a plurality of interconnecting LEDs. The preparation method for the chip is simple and the preparation method can be driven by higher voltage; in a control circuit for a lamp, a transformer is not required, so that the production cost is reduced; and in addition, the high voltage chip is free from current crowding, capable of passing high current and good in the heat dissipation performance.

Description

A kind of preparation method of high voltage LED chip

Technical field

The invention belongs to semiconductor applications, particularly relate to a kind of preparation method of high voltage LED chip.

Background technology

Current LED(light-emitting diode) general illumination market uses traditional DCLED(direct-current LED) chip, DCLED chip generally works under big current low-voltage, for booster tension also meets the luminous flux required for illumination, general employing COB(integration packaging) structure, i.e. multiple chips connection in series-parallel.The high-voltage LED (high-voltage LED) occurred subsequently then just achieves the connection in series-parallel of micromeritics in chip-scale, chip-scale connection in series-parallel has following advantage: one is the consistency problem that high-voltage LED avoids COB structure medium wavelength, voltage, brightness span are brought; Two is high-voltage LEDs because self operating voltage is high, easy realization encapsulation finished product operating voltage is close to civil power, improve the conversion efficiency of driving power, because operating current is relatively lower, its line loss in finished product application also will be starkly lower than traditional DCLED chip; Three die bond and the bonding quantity being the reduction of chip, are conducive to the cost reducing encapsulation.Therefore high-voltage LED has wide prospect of the application in illumination market.

But, each LED unit in existing high voltage LED is mostly transversary, transversary LED unit there is electric current congested (CurrentCrowding), big current under light efficiency low, the defects such as thermal resistance is large, complex process, not easily secondary light-distribution, therefore need that a kind of current spread is good, thermal resistance is low, the height of easy secondary light-distribution electricity LED.

Summary of the invention

For the deficiencies in the prior art, the object of this invention is to provide a kind of current spread good, high, good, the simple high voltage LED chip preparation method of technique of dispelling the heat of luminous efficiency under big current.

To achieve these goals, the present invention by the following technical solutions: a kind of preparation method of high voltage LED chip, comprising: grown buffer layer, N-type GaN layer, multiple quantum well layer, P type GaN layer and reflective metal layer successively on the first substrate; The subregion of described reflective metal layer is formed multiple first groove, and the degree of depth of described first groove is to P type GaN layer; Described reflective metal layer deposits one deck first insulating barrier, and described first insulating barrier covers the first groove; Described first insulating barrier deposits one deck bonding metal layer; The mode of wafer bonding is adopted to be combined with the second substrate; Peel off the first substrate and resilient coating makes N-type GaN layer expose; Form multiple second groove in the subregion of described N-type GaN layer, the position of described second groove is corresponding with the first groove, the degree of depth to the first insulating barrier, forms spaced GaN crystallite;

In described GaN crystallite subregion, form a groove, described groove is connected with the second groove, and the degree of depth is to reflective metal layer; In the GaN crystallite deposited on sidewalls first insulating layer of described second groove; Plated metal in described N-type GaN layer, the reflective metal layer partly exposed and the second groove and on the second surface of insulating layer, forms the interconnect metal of N electrode, P electrode and connection adjacent LED electrode, forms multiple LED of interconnection.

Preferably, described method also comprises and carries out surface coarsening process to N-type GaN layer.

Preferably, described first substrate and the second substrate are the one in sapphire, SiC or Si.

Preferably, the high voltage LED chip that described method is also included in formation applies fluorescent powder silica gel.

Preferably, the material of described reflective metal layer be following in one: Ag, Al, Ni, Ni-Ag alloy, Ag-Ni alloy, Ag-Ni-Al alloy.

Preferably, the material of described first insulating barrier and the second insulating barrier be following in one or more: SiO ₂, SiN, Al ₂o ₃.

Preferably, the material of the interconnect metal of described N electrode, P electrode and connection adjacent LED electrode be following in one or more: Cr, Ti, Al, Ni, Pt, Au.

Beneficial effect of the present invention:

The invention provides a kind of preparation method of high voltage LED chip, this chip fabrication technique is simple, directly can adopt higher voltage drives; In the control circuit of light fixture, save transformer, reduce production cost, do not have electric current congested, by big current, excellent heat radiation performance.

Accompanying drawing explanation

Fig. 1 to Fig. 9 is the schematic diagram of the preparation process of one embodiment of the invention.

Identifier declaration in figure:

1 is the first substrate, and 2 is resilient coating, and 3 is N-type GaN layer, 4 is multiple quantum well layer, and 5 is P type GaN layer, and 6 is reflective metal layer, 7 is the first groove, and 8 is the first insulating barrier, and 9 is bonding metal layer, 10 is the second substrate, and 11 is the second groove, and 12 is groove, 13 is the second insulating barrier, 14 is N electrode, and 15 is P electrode, and 16 is interconnect metal.

Embodiment

As shown in Figures 1 to 9, the invention provides a kind of preparation method of high voltage LED chip.

As shown in Figure 1, adopt MOCVD epitaxy growing technology, grown buffer layer 2, N-type GaN layer 3, multiple quantum well layer 4, P type GaN layer 5 successively in Sapphire Substrate 1, then adopt PVD technology precipitation reflective metal layer 6.As shown in Figure 2, use ICP dry etching to P type GaN layer 5 in the subregion of described reflective metal layer 6, form multiple first groove groove 7, in the present embodiment, the number of the first groove 7 is 2.As shown in Figure 3, reflective metal layer 6 deposits one deck first insulating barrier 8, first insulating barrier 8 and covers the first groove 7, the material of described first insulating barrier 8 is silicon dioxide.As shown in Figure 4, the first insulating barrier 8 deposits one deck bonding metal layer 9, then adopt the mode of wafer bonding to be combined with silicon substrate 10.As shown in Figure 5, adopt the method for laser lift-off stripping Sapphire Substrate 1 and resilient coating 2 that N-type GaN layer 3 is exposed.As shown in Figure 6, the position that the subregion of etching N type GaN layer 3 forms multiple second groove 11, second groove 11 is corresponding with the first groove 7, and the degree of depth to the first insulating barrier 8, forms spaced GaN crystallite.As shown in Figure 7 A, while etching second trenches 11, etching forms a groove 12 in GaN crystallite subregion, and groove 12 is connected with the second groove 11, and the degree of depth is to reflective metal layer 6, and its vertical view as shown in Figure 7 B.As shown in Figure 8, in the GaN crystallite deposited on sidewalls first insulating layer 13 of the second groove 11, the material of described second insulating barrier 13 is silicon dioxide.As shown in Figure 9, in N-type GaN layer 3, the reflective metal layer 6 that exposes of part and the second groove 11 and the second insulating barrier 13 deposited on silicon metal, form N electrode 14, P electrode 15 and the interconnect metal 16 being connected adjacent LED electrode, form multiple LED of interconnection.

The above; be only the embodiment in the present invention; but protection scope of the present invention is not limited thereto, any people being familiar with this technology is in the technical scope disclosed by the present invention, and the conversion that can expect easily or replace all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.

Claims

1. a preparation method for high voltage LED chip, comprising:

Grown buffer layer, N-type GaN layer, multiple quantum well layer, P type GaN layer and reflective metal layer successively on the first substrate;

The subregion of described reflective metal layer is formed multiple first groove, and the degree of depth of described first groove is to P type GaN layer;

Described reflective metal layer deposits one deck first insulating barrier, and described first insulating barrier covers the first groove;

Described first insulating barrier deposits one deck bonding metal layer;

The mode of wafer bonding is adopted to be combined with the second substrate;

Peel off the first substrate and resilient coating makes N-type GaN layer expose;

Form multiple second groove in the subregion of described N-type GaN layer, the position of described second groove is corresponding with the first groove, the degree of depth to the first insulating barrier, forms spaced GaN crystallite;

In described GaN crystallite subregion, form a groove, described groove is connected with the second groove, and the degree of depth is to reflective metal layer;

In the GaN crystallite deposited on sidewalls first insulating layer of described second groove;

Plated metal in described N-type GaN layer, the reflective metal layer partly exposed and the second groove and on the second surface of insulating layer, forms the interconnect metal of N electrode, P electrode and connection adjacent LED electrode, forms multiple LED of interconnection.

2. the preparation method of a kind of high voltage LED chip according to claim 1, is characterized in that described method also comprises and carries out surface coarsening process to N-type GaN layer.

3. the preparation method of a kind of high voltage LED chip according to claim 1, is characterized in that the material of described first substrate and the second substrate is the one in sapphire, SiC or Si.

4. the preparation method of a kind of high voltage LED chip according to claim 1, is characterized in that the high voltage LED chip that described method is also included in formation applies fluorescent powder silica gel.

5. the preparation method of a kind of high voltage LED chip according to claim 1, it is characterized in that the material of described reflective metal layer be following in one: Ag, Al, Ni, Ni-Ag alloy, Ag-Ni alloy, Ag-Ni-Al alloy.

6. the preparation method of a kind of high voltage LED chip according to claim 1, it is characterized in that the material of described first insulating barrier and the second insulating barrier be following in one or more: SiO ₂, SiN, Al ₂o ₃.

7. the preparation method of a kind of high voltage LED chip according to claim 1, it is characterized in that the material of the interconnecting metal layer of described N electrode, P electrode and connection adjacent LED electrode be following in one or more: Cr, Ti, Al, Ni, Pt, Au.