CN105185745B - Fin formula field effect transistor and forming method thereof - Google Patents

Abstract

The present invention provides a kind of fin formula field effect transistor and forming method thereof.The forming method of the fin formula field effect transistor includes, there is provided Semiconductor substrate, the Semiconductor substrate include first area and second area；Ion is injected into the first area, the first well region is formed, etches the Semiconductor substrate afterwards and the first fin is formed in the first well region, the second fin is formed in second area；Dielectric layer is formed on a semiconductor substrate, and first fin and the second fin point expose the dielectric layer, etch first fin and the second fin, wherein, it is more than the etch rate of the second fin doped with the etch rate of the first fin of the first ion, so that the second fin after etching is highly more than the height of the first fin, the fin of different height is formed on the same semiconductor substrate, so as to meet the performance requirement of different components.

Description

Fin formula field effect transistor and forming method thereof

Technical field

The present invention relates to semiconductor to form field, more particularly, to a kind of fin formula field effect transistor and forming method thereof.

Background technology

With the rapid development of integrated circuit (abbreviation IC) manufacturing technology, the process node of traditional integrated circuit gradually subtracts Small, the size of IC-components constantly reduces, and prepared by IC-components constantly updates to improve the property of IC-components Energy.

In MOS transistor, obtained by forming the metal with different work functions between high-K dielectric layer and metal gates Preferable threshold voltage is obtained, so as to improve device performance.But with the reduction of semiconductor technology characteristic size, traditional plane formula MOS transistor is can not meet the needs of to device performance, as plane formula MOS transistor becomes to the control ability of channel current It is weak, cause serious leakage current.Therefore, multi-gate device has obtained extensive concern as the replacement of conventional device.

Wherein, fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device.It is conventional with reference to shown in figure 1 Fin FET include：Semiconductor substrate 1；Fin 3 in Semiconductor substrate 1；Oxide layer 2 in Semiconductor substrate 1；According to It is secondary to be located at the surface of oxide layer 2 and across the gate dielectric layer (not shown) and grid 4 of fin 3；The side wall 6 between the fin of the both sides of fin 3；Position Grid curb wall 5 in the both sides of grid 4；Source/drain 31 in 5 liang of lateral fins 3 of grid 4 and grid curb wall.

For Fin FET, the part that the top of fin 3 and the side wall of both sides are in contact with grid all turns into channel region, i.e., With multiple grid, be advantageous to increase driving current, improve device performance.

Obtained in field, Fin FET such as SRAMs (Static Random Access Memory, SRAM) Extensive use.And as integrated circuit develops, generally require to prepare the fin of different height, will to adapt to the performance of different components Ask.

As illustrated with reference to fig. 2, SRAM memory cell includes：Pull up transistor, PMOS transistor P1 and P2；Lower crystal pulling Pipe, nmos pass transistor N1 and N2；And transmission transistor, nmos pass transistor N3 and N4.

For in high performance SRAM memory, relative to pulling up transistor, pull-down transistor usually requires bigger drive Streaming current, to meet the performance requirement of memory.Typically require pull-down transistor N1 and N2, pull up transistor P1 and P2, and Transmission transistor N3 and N4 driving current ratio are 2:1:1, the driving current of transistor is directly proportional to the channel area of transistor, Require that pull-down transistor N1 and N2, the P1 and P2 that pulls up transistor, transmission transistor N3 and N4 channel area ratio are 2:1:1. For fin formula field effect transistor, by adjusting the fin height of each transistor, the ditch of each transistor can be effectively adjusted Road area.

In addition, the channel area by adjusting each transistor, also can adjust the given supply voltage value of each transistor (Vcc), to customize pull-down transistor N1 and N2, pull up transistor P1 and P2, and transmission transistor N3 and N4 unit ratio (Cell ratio), to obtain marginal (Static Noise Margin, the SNM) numerical value of maximum static noise.

Therefore, the fin of different height how is manufactured on same wafer to meet the performance requirement of different components, Yi Jiti The problem of high transistor static noise limit numerical value is those skilled in the art's urgent need to resolve.

The content of the invention

The present invention solves the problems, such as it is to provide a kind of fin formula field effect transistor and forming method thereof, the fin field effect The forming method of transistor is answered to manufacture the fin of different height on same wafer, to meet the performance requirement of different components.

To solve the above problems, the forming method of fin formula field effect transistor provided by the invention, including：

Semiconductor substrate is provided, the Semiconductor substrate includes first area and second area；

The first ion is injected into the Semiconductor substrate first area, forms the first well region；

The first well region of the Semiconductor substrate and the second area are etched, doping is formed in first well region There is the first fin of first ion, the second fin is formed in second area；

Dielectric layer is formed in Semiconductor substrate between first fin and the second fin, makes first fin and the second fin Part protrudes from the dielectric layer surface；

First fin and the second fin are etched, and the speed for etching first fin is more than the speed of the second fin of etching, makes The height of first fin is less than the height of second fin after etching after etching.

Alternatively, the first area is PMOS area, and the second area is NMOS area, and first well region is N Trap.

Alternatively, first ion is phosphonium ion or arsenic ion.

Alternatively, the step of injecting the first ion into the first area includes：Inject the dosage of ion for 1.0 × 10¹³~1.0 × 10¹⁷/cm², energy is 1~20eV.

Alternatively, in the step of etching the first well region of the Semiconductor substrate and the second area, the etching Dry etching.

Alternatively, the dry etching uses the mixed gas of carbon tetrafluoride and oxygen as etching gas.

Alternatively, the technological parameter of the dry etching includes：Air pressure is 10~200mtorr, radio-frequency power is 100~ 1000W, bias power are 0~500W, and the flow of the carbon tetrafluoride is 10~200sccm, the flow of the oxygen for 1~ 100sccm。

Alternatively, the etching gas also include the one or more in difluoromethane, sulfur hexafluoride and Nitrogen trifluoride.

Alternatively, the flow of the difluoromethane is 10~200sccm, and the flow of sulfur hexafluoride is 0~100sccm, three The flow of nitrogen fluoride is 0~100sccm.

Alternatively, the step of etching first fin and the second fin includes：Described first is etched using dry etching method Fin and the second fin.

Alternatively, the step of dry etching for etching first fin and the second fin, includes：With carbon tetrafluoride, Nitrogen trifluoride Mixed gas with oxygen is etching gas.

Alternatively, etching the technological parameter of the dry etching of first fin and the second fin includes：Air pressure be 10~ 200mtorr, radio-frequency power are 100~1000W, and bias power is 0~500W, the flow of the carbon tetrafluoride for 10~ 200sccm, the flow of the oxygen is 1~100sccm, and the flow of Nitrogen trifluoride is 10~100sccm.

Alternatively, the step of dry etching for etching first fin and the second fin, includes：The etching gas also include One or more in hydrogen bromide and chlorine.

Alternatively, the flow of the hydrogen bromide is 10~500sccm, and the flow of chlorine is 10~200sccm.

Alternatively, the step of etching the first well region of the Semiconductor substrate and the second area includes：

Hard mask is formed on a semiconductor substrate, the first trap using the hard mask as Semiconductor substrate described in mask etching Area and the second area；

The step of forming dielectric layer includes：

Layer of dielectric material is formed on the semiconductor substrate, and the layer of dielectric material covers first fin and second Fin；

Using the hard mask as stop-layer, the layer of dielectric material is planarized；

The layer of dielectric material of segment thickness is removed, the upper surface for the dielectric layer to be formed is less than first fin With the upper surface of the second fin；

Remove the hard mask；

Etching first fin and the second fin step also includes：Further remove the dielectric layer of segment thickness.

Alternatively, the Semiconductor substrate is silicon substrate.

Alternatively, first fin and the second fin are etched, make first fin after etching height be less than it is described after etching After the height of second fin, the forming method also includes：The second ion is injected into the second area, forms the second well region.

Present invention also offers a kind of fin formula field effect transistor, including：

Semiconductor substrate, the Semiconductor substrate include first area and second area；

The first area and second area are provided with the first fin and the second fin；

The height of first fin is less than the second fin height, and doped with the first ion in first fin；

Formed with dielectric layer, first fin and in the Semiconductor substrate between first fin and the second fin Two fins protrude from the dielectric layer surface.

Alternatively, the first area is PMOS area, and the second area is NMOS area.

Alternatively, first ion is phosphonium ion or arsenic ion.

Compared with prior art, technical scheme has advantages below：

Semiconductor substrate includes first area and second area, injects ion into the first area, to form first Well region；The Semiconductor substrate is etched afterwards, the first fin is formed in the first well region, and the second fin is formed in second area； Dielectric layer is formed in Semiconductor substrate between first fin and the second device, and first fin and the second fin point expose institute State dielectric layer；First fin and the second fin are etched, wherein, it is more than second doped with the etch rate of the first fin of the first ion The etch rate of fin so that the second fin after etching is highly more than the height of the first fin, so that shape on the same semiconductor substrate Into the fin of different height, so as to meet the performance requirement of different components, and the fin formula field effect transistor being subsequently formed is improved Static noise limit numerical value.

Brief description of the drawings

A kind of structural representation of fin formula field effect transistor of Fig. 1 prior arts；

Fig. 2 is a kind of structural representation of SRAM memory cell of prior art；

Fig. 3 to Figure 13 is the schematic diagram of the forming method for the fin formula field effect transistor that one embodiment of the invention provides.

Embodiment

As described in the background art, in the application of existing fin formula field effect transistor, according to device performance requirements, need Highly different fins is formed on same wafer to improve device performance.In SRAM memory cell, it can be made by reducing The fin height ratio of fin height for the PMOS transistor that pulls up transistor and the nmos pass transistor as pull-down transistor, so that The channel area to pull up transistor with pull-down transistor is adjusted, and then adjusts the driving current to pull up transistor with pull-down transistor Ratio；In addition, by adjusting the channel area to pull up transistor with pull-down transistor, SNM numerical value can be optimized, so as to optimize crystal The performance of pipe.

For the demand, the invention provides a kind of fin formula field effect transistor and forming method thereof, in same wafer The upper fin for forming different height so that the fin of PMOS transistor is less than the fin of nmos pass transistor, to meet that SRAM etc. is partly led The performance requirement of body device, while by changing the height of fin, the channel area of fin formula field effect transistor is can adjust, so as to excellent Change SNM numerical value, optimize the performance of fin formula field effect transistor.

In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention Embodiment be described in detail.

The forming method of the present embodiment fin formula field effect transistor includes：

With reference to shown in figure 3, there is provided Semiconductor substrate 100.

In the present embodiment, the Semiconductor substrate 100 is silicon substrate, but the invention is not limited in this regard, in other realities Apply in example, the Semiconductor substrate 100 can also be germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator substrate, and common partly leads Body substrate can be as the Semiconductor substrate in the present embodiment.

In the present embodiment, the Semiconductor substrate 100 is including first area I described in first area I and second area II PMOS area, for forming PMOS fin formula field effect transistors；Second area II is NMOS area, for forming NMOS fin field Effect transistor.

With reference to shown in figure 4, the first ion is injected into the first area I, the first well region is formed in the I of first area 110。

In the present embodiment, the first ion is N-type ion, and the first well region 110 of formation is N traps.The N-type ion is chosen as Phosphorus (P) ion or arsenic (As) ion.

In the present embodiment, the N-type ion is phosphonium ion.

In the present embodiment, the specific steps of P ion are injected into the first area I to be included：The dosage of ion implanting is 1.0×10¹³~1.0 × 10¹⁷/cm², energy is 1~20eV.Specific dosage and energy values are according to the semiconductor specifically formed The structures shape of device.

Then with reference to the Semiconductor substrate 100 with reference to shown in figure 5 and Fig. 6, is etched, formed in the first area I First fin 310, the second fin 320 is formed in second area II.

In the present embodiment, the method for etching the Semiconductor substrate 100 to form the first fin 310 and the second fin 320 is dry Method etches.Detailed process includes：

As shown in figure 5, hard mask 220 is formed in the Semiconductor substrate 100, then as shown in fig. 6, being covered firmly with described Mould 220 is the first well region 110 and second area II of Semiconductor substrate 100 described in mask etching, so as in the semiconductor The first fin 310 is formed in first well region of substrate 100, the second fin 320 is formed in second area II.

In the present embodiment, the material of the hard mask 220 is silicon nitride (SiN), formed hard mask 220 the step of include： Silicon nitride material is first formed in the Semiconductor substrate 100 using CVD techniques, afterwards the shape in the silicon nitride material Into photoresist hard mask, and using the photoresist mask as silicon nitride material described in mask etching, to form the hard mask 220。

In the present embodiment, first fin 310 is located in first well region 110, and P ion is injected with the first fin 310.

In the present embodiment, the dry etch process specifically includes：

With carbon tetrafluoride (CF₄) and oxygen (O₂) mixed gas be etching gas, adjust the air pressure of etching technics for 10~ 200mtorr, radio-frequency power are 100~1000W, and bias power is 0~500W.Wherein, the flow of the carbon tetrafluoride be 10~ 200sccm, the flow of the oxygen are 1~100sccm.

In alternative, the etching gas also include difluoromethane (CH₂F₂), sulfur hexafluoride (SF₆) and Nitrogen trifluoride (NF₃) in one or more, wherein, the flow of the difluoromethane is 10~200sccm, the flow of sulfur hexafluoride for 0~ 100sccm, the flow of Nitrogen trifluoride is 0~100sccm.

First area I (doped with the silicon of P ion) and second area II of the above-mentioned etching technics for Semiconductor substrate 100 The etch rate of (silicon undoped with P ion) is similar, so as to which the first fin 310 and the height of the second fin 320 that obtain are close.

With reference to shown in figure 7, formed after the fin 320 of the first fin 310 and second, the shape in the Semiconductor substrate 100 Into layer of dielectric material 130, the layer of dielectric material 130 covers the fin 320 of the first fin 310 and second；Covered firmly with described afterwards Mould removes the layer of dielectric material 130 of Partial Height using planarization, until exposing the hard mask as stop-layer 220。

In the present embodiment, the material of layer of dielectric material 130 is silica, and formation process is chosen as chemical vapour deposition technique (CVD)。

In the present embodiment, the planarization is chemical mechanical milling tech (CMP), and the hard mask 220 is grinding Stop-layer.

With reference to shown in figure 8, after exposing the hard mask 220, it is that mask etching removes part to continue with the hard mask 220 The dielectric layer 131 that the layer of dielectric material 130 of height is formed after etching.The dielectric layer 131 is still covered in the semiconductor On substrate 100, but the upper surface of the dielectric layer 213 is less than the upper surface of the fin 320 of the first fin 310 and second so that portion The fin 320 of first fin 310 and second of point height protrudes from the surface of dielectric layer 131.

In the present embodiment, the method for removing the layer of dielectric material 130 of Partial Height is dry etch process, described dry Method etching technics specifically includes：Using containing fluoroform (CHF₃), Nitrogen trifluoride (NF₃) or oxygen (O₂) etc. gas quarter Lose agent and etch the layer of dielectric material 130.But the technique of the etching dielectric layer does not limit protection scope of the present invention, ability The technique of etch media layer is applied to the present invention in domain.

With reference to shown in figure 9, the hard mask 220 is removed.

In the present embodiment, the material of the hard mask 220 is silicon nitride, and the method for removing the hard mask 220 is wet method Etching technics.

Alternatively, the wet-etching technology includes：Using temperature as 100~200 DEG C, volumetric concentration is 10%~90% Hot phosphoric acid (H₃PO₄) it is etchant, 10 seconds (sec)~600 second (sec) are persistently etched, remove the hard mask 220, are exposed described The top of first fin 310 and the second fin 320.

Above-mentioned wet-etching technology is removing hard mask 220 simultaneously, will not be to the layer of dielectric material 130, the first fin 310 There is excessive damage with the second fin 320.

Now, the height of the fin 320 of the first fin 310 and second is close.

With reference to shown in figure 10, continue to etch the fin 320 of the first fin 310 and second, the He of the first fin 311 formed after etching The second fin 321 after etching.

In the present embodiment, the method for etching the fin 320 of the first fin 310 and second is dry etch process.After etching The height of first fin 311 is less than the height of the second fin 321 after etching.

Its principle can be with reference to reference to shown in figure 11, and Figure 11 is in dry etch process, and different microwaves etch power Under (microwave power), the etch rate curve of the silicon of doping different type ion (including N-type ion and p-type ion). Wherein, L1 represents heavily doped N-type ion (N⁺⁺) etch rate curve, the L2 of silicon represent the silicon of lightly doped n type ion (N-) Etch rate curve, L3 represent the etch rate curve for the silicon that p-type ion (P-) is lightly doped, and L4 represents heavily doped P-type ion (P⁺⁺) silicon etch rate curve.Known by Figure 11, in the case where identical microwave etches frequency, the silicon of heavily doped N-type ion, be lightly doped The silicon (and the silicon of p-type ion is lightly doped) of N-type ion, and the etch rate of the silicon of heavily doped P-type ion are sequentially reduced, wherein The silicon of lightly doped n type ion is approximate with the etch rate for the silicon that p-type ion is lightly doped, without the etch rate of the silicon of Doped ions The etch rate of silicon with p-type ion (N-type ion) is lightly doped is close.

In the present embodiment, based in first fin 310 doped with phosphorus (P) ion, and undoped with there is P in the second fin 320 Ion.In etching process, the etch rate of first fin 310 is significantly greater than the etch rate of the second fin 320, and after etching The height of one fin 311 is less than the height of the second fin 321 after etching.

Specifically included in the present embodiment, the step of the first fin 310 described in dry etching and the second fin 320：With carbon tetrafluoride (CF₄), Nitrogen trifluoride (NF₃) and oxygen (O₂) mixed gas be etching gas, control the air pressure of dry etch process for 10~ 200mtorr, radio-frequency power are 100~1000W, and bias power is 0~500W.In etching gas, the flow of the carbon tetrafluoride For 10~200sccm, the flow of oxygen is 1~100sccm, and the flow of Nitrogen trifluoride is 10~100sccm.

In alternative, the etching gas also include hydrogen bromide (HBr) and chlorine (Cl₂) in one or more.Its In, the flow of the hydrogen bromide is 10~500sccm, and the flow of chlorine is 10~200sccm.

Above-mentioned etching technics is for the silicon (the first fin 310) doped with P ion and undoped with silicon (the second fin for having P ion 320) there is larger etching selection ratio, the etch rate of first fin 310 is more than the etch rate of the second fin 320, and then The height of the first fin 311 is less than the height of the second fin of etching technics 321 after etching.

And in the step of etching 310 and second fin 320 of the first fin, while the dielectric layer of segment thickness can be removed 131, the dielectric layer 132 formed after etching.

Referring next to shown in Figure 12, photoresist layer 230 is coated on the first area I of the Semiconductor substrate 100, afterwards The implanting p-type ion into the second area II of the Semiconductor substrate 100, form p-well 120.

In the present embodiment, into the second area II of the Semiconductor substrate 100 during implanting p-type ion, part P Type ion can penetrate the dielectric layer 132 on second area II, into Semiconductor substrate.

With reference to shown in figure 13, the photoresist layer 230 on the second area II is removed.Subsequently, can be described Gate dielectric layer, side wall, and the structure such as grid are formed on one region I and second area II, so as to be formed on the I of first area PMOS gridistors, nmos pass transistor is formed on second area II.Above-mentioned technique is this area maturation process, herein no longer Repeat.

In the present embodiment, first N traps are formed in the PMOS area I doped N-types ion (P) of Semiconductor substrate；Afterwards to cover firmly Mould 220 is mask, and etch semiconductor substrates 100 form height phase on the PMOS area I and NMOS area II of Semiconductor substrate Near the first fin 310 and the second fin 320, and after the hard mask 220 is removed, utilize the silicon of doped N-type ion (such as P ion) With the etch rate difference undoped with N-type ion silicon, the first fin 310 and the second fin 320 are further etched, to form new first The fin 321 of fin 311 and second, so as to form the fin that height differs in same semi-conductive substrate 100, to meet SRAM etc. half The performance requirement of conductor device；Simultaneously by changing the height of fin, to adjust the channel area of fin formula field effect transistor, optimization SNM numerical value, and then optimize the performance of memory.

In addition, in the present embodiment, the first fin and the second fin are being etched so that the height of the first fin after etching, which is less than, carves After the height of the second fin after erosion, then the NMOS area II doped p-type ion (such as boron ion) to the Semiconductor substrate, with shape Into the technical scheme of p-well.Above-mentioned technical proposal avoids first forming p-well in the NMOS area II of Semiconductor substrate, carves again afterwards Semiconductor substrate 100 is lost to be formed in the scheme of NMOS fins, established p-well it is follow-up such as etch semiconductor substrates to form first The defects of being sustained damage in fin and the second fin, and a series of etching subsequent techniques such as the first fin and the second fin；In addition, causing After the height of the first fin after etching is less than the height of the second fin after etching, thickness of dielectric layers is true on a semiconductor substrate for covering It is fixed, no longer perform etching technique, so as to avoid the first implanting p-type ion into dielectric layer, afterwards again etch media layer and reduce quarter The defects of dielectric layer surface flatness after erosion, so as to improve the performance of the Semiconductor substrate ultimately formed.

With continued reference to shown in Figure 13, present invention also offers a kind of fin formula field effect transistor.The fin field effect is brilliant Body pipe can be made by the forming method based on above-mentioned fin formula field effect transistor, can also be adopted and be formed by other methods.

The structure of the fin formula field effect transistor includes：Semiconductor substrate 100, the Semiconductor substrate 100 include the One region I and second area II；

The first fin 311 is provided with the first area I, the second fin 321 is provided with second area II.Wherein, described first The height of fin 311 is less than the height of second fin 321；

Formed with dielectric layer in the Semiconductor substrate 100 in region between the fin 321 of the first fin 311 and second 132, the surface of dielectric layer 132 is protruded in the part of 311 and second fin of the first fin 321.

In the present embodiment, the first area I is PMOS area, formed with N traps in the first area I, for shape Into PMOS transistor, doped with N-type ion in the first fin 310.In the present embodiment, the N-type ion is phosphorus (P) ion or arsenic (As) ion.

Second area II is NMOS area, formed with p-well in the second area II, for forming nmos pass transistor, Doped with p-type ion in the second fin 320.

In the present embodiment, the height of the PMOS fins of fin formula field effect transistor is less than the height of NMOS fins, thus can meet In SRAM memory cell, the fin height of the PMOS transistor to pull up transistor is used as by reducing and as pull-down transistor The fin height ratio of nmos pass transistor, to adjust the channel area to pull up transistor with pull-down transistor, reach the upper crystal pulling of adjustment The purpose of the driving current ratio of body pipe and pull-down transistor；Meanwhile by adjusting the ditch to pull up transistor with pull-down transistor Road area, to reach optimization SNM numerical value, and then optimize the purpose of fin formula field effect transistor performance.

Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute The scope of restriction is defined.

Claims (14)

1. A kind of 1. forming method of fin formula field effect transistor, it is characterised in that including：

   Semiconductor substrate is provided, the Semiconductor substrate includes first area and second area；

   The first ion is injected into the Semiconductor substrate first area, forms the first well region；

   The first well region and the second area of Semiconductor substrate described in dry etching, doping is formed in first well region There is the first fin of first ion, the second fin is formed in second area, the gas of Semiconductor substrate described in the dry etching Body uses the one or more in carbon tetrafluoride and oxygen, and difluoromethane, sulfur hexafluoride and Nitrogen trifluoride；

   Dielectric layer is formed in Semiconductor substrate between first fin and the second fin, makes first fin and the second fin point Protrude from the dielectric layer surface；

   First fin and the second fin are etched, and the speed for etching first fin is more than the speed of the second fin of etching, makes etching The height of first fin is less than the height of second fin after etching afterwards.
2. 2. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the first area is PMOS area, the second area are NMOS area, and first well region is N traps.
3. 3. the forming method of fin formula field effect transistor as claimed in claim 2, it is characterised in that first ion is phosphorus Ion or arsenic ion.
4. 4. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that into the first area The step of injecting the first ion includes：The dosage for injecting ion is 1.0 × 10¹³~1.0 × 10¹⁷/cm², energy is 1~20eV.
5. 5. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that described in the dry etching The technological parameter of Semiconductor substrate includes：Air pressure is 10~200mtorr, and radio-frequency power is 100~1000W, bias power 0 ~500W, the flow of the carbon tetrafluoride is 10~200sccm, and the flow of the oxygen is 1~100sccm.
6. 6. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the stream of the difluoromethane Measure as 10~200sccm, the flow of sulfur hexafluoride is 0~100sccm, and the flow of Nitrogen trifluoride is 0~100sccm.
7. 7. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that etching first fin and The step of second fin, includes：First fin and the second fin are etched using dry etching method.
8. 8. the forming method of fin formula field effect transistor as claimed in claim 7, it is characterised in that etching first fin and The step of dry etching of second fin, includes：Using the mixed gas of carbon tetrafluoride, Nitrogen trifluoride and oxygen as etching gas.
9. 9. the forming method of fin formula field effect transistor as claimed in claim 8, it is characterised in that etching first fin and The technological parameter of the dry etching of second fin includes：Air pressure is 10~200mtorr, and radio-frequency power is 100~1000W, biases work( Rate is 0~500W, and the flow of the carbon tetrafluoride is 10~200sccm, and the flow of the oxygen is 1~100sccm, borontrifluoride The flow of nitrogen is 10~100sccm.
10. 10. the forming method of fin formula field effect transistor as claimed in claim 8, it is characterised in that etching first fin Include with the step of dry etching of the second fin：The etching gas also include the one or more in hydrogen bromide and chlorine.
11. 11. the forming method of fin formula field effect transistor as claimed in claim 10, it is characterised in that the stream of the hydrogen bromide Measure as 10~500sccm, the flow of chlorine is 10~200sccm.
12. 12. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that etch the semiconductor The step of first well region of substrate and the second area, includes：

    Form hard mask on a semiconductor substrate, using the hard mask as Semiconductor substrate described in mask etching the first well region with And the second area；

    The step of forming dielectric layer includes：

    Layer of dielectric material is formed on the semiconductor substrate, and the layer of dielectric material covers first fin and the second fin；

    Using the hard mask as stop-layer, the layer of dielectric material is planarized；

    The layer of dielectric material of segment thickness is removed, makes the upper surface of the dielectric layer to be formed less than first fin and the The upper surface of two fins；

    Remove the hard mask；

    Etching first fin and the second fin step also includes：Further remove the dielectric layer of segment thickness.
13. 13. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the Semiconductor substrate For silicon substrate.
14. 14. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that etching first fin With the second fin, the height of first fin after etching is set to be less than after etching after the height of second fin, the forming method is also Including：The second ion is injected into the second area, forms the second well region.