CA1240741A - Am stereo signal decoder - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A simplified stereo signal decoder is disclosed for use in an AM stereo receiver which receives composite AM stereo broadcast signals comprising a radio frequency carrier wave having amplitude modulation representing stereo sum (L+R) information and phase modulation representing stereo difference (L-R) information. The decoder makes novel use of a common, commercially available integrated circuit (IC) that normally is used as a tone detector or a frequency-modulation (FM) detector.
The decoder provides synchronous detection of the (L-R) information, combined two mode phase-locked loop (PLL) recovery of the carrier component and enabling of the (L-R) signal output, and delayed enabling of the (L-R) signal output for a "stereo bloom" effect. The decoder is particularly useful for decoding independent sideband (ISB) AM stereo broadcast signals.

Description

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WH-6497-1 - 1 - 0595H/005~F

TITLE: AM STEREO SIGNAL DECODER

BACKGROUND OF THE INVENTION
This invention relates to a signal decoder and more particularly to a stereo signal decoder for use in a receiver which is capable of receiving compatible AM
stereo radio frequency (RF) broadcast signals, wherein an RF carrier has amplitude modulation (AM) representing stereo sum (L-~R) information and phase modulation (PM) representing stereo difference (L-R) information.
In my prior U.S. Patent No. 4,018,994, an AM
stereo receiver is disclosed for obtaining L and R
information from an independent sideband (ISB) AM stereo broadcast signal of the above-described type. In such an ISB signal, left (L) stereo information is transmitted primarily in the lower sidebands of the composite modulated RF signal and right (R) stereo information is transmitted primarily in the upper sidebands of the composite RF signal. This results from a 90 phase relationship that is introduced between the L+R and L-R
modulating siynals prior to their being used to amplitude and phase modulate, respectively, the RF carrier at the transmitter. In one type of ISB receiver, a corresponding 90 phase difference is introduced between the demodulated L+R and L-R signals before they are matrixed to produce L and R output signals.
The receiver shown in my prior U.S. Patent No.
4,01~,994 is shown as being constructed from a plurality of separate electronic circuit components and achieves low distortion decoding of a received AM stereo signal by using a distortion cancelling technique in the stereo decoder. In accordance with one aspect of that technique, a received composite intermediate frequency (IF) ISB
signal is inversely amplitude modulated as a function of ~5 the demodulated (L+R) signal. The resulting altered IF
signal is applied to a synchronous quadrature detector, together with an IF reference signal that is developed by a PLL arrangement, where the phase modulation is demodulated to develop a distortion corrected (L-R) signal. The L+R and L-R signals are applied to a pair of 90 phase difference networks and then matrixed to develop left (L) and right (R) stereo audio output signals.
In constructing AM stereo receivers of the aforementioned type it would be desirable to implement the stereo decoder using a single custom-built IC which incorporates all or many of the necessary circuit functions. Although this would substantially reduce space, power, cooling and weight requirements, the capital investment and time required to design and produce such a custom IC is substantial. Alternatively, therefore, it would be desirable to be able to use an existing, low-cost, readily available IC as the basis for AM stereo decoder configurations which would require far fewer discrete circuit components.
It would also be desirable to be able to implement such a simplified decoder using a PLL
arrangement which will not introduce an undesirable tuning characteristic in continuously tunable stereo receivers.
Generally, this requires some form of muting in the L-R
signal path of the decoder during initial tuning of the receiver to a stereo station.
SUMMARY OF THE INVENTION
An improved stereo radio receiver which includes a stereo information decoder, according to the present invention, has an improvement comprising means responsive to a received intermediate frequency stereo signal for developing an output signal representative of the stereo sum signal component thereof and means, having a controllable variable impedance to ground for IF
frequencies, having said received IF stereo signal coupled across said impedance, and having said output signal coupled to control the variation of the impedance, for inversely amplitude modulating the IF signal.

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According to an aspect of the invention, the controllable variable impedance is a field effect transistor having a control terminal and a pair of other terminals, and the output signal is coupled to the control terminal. The IF signal is coupled to one of the pair of other terminals and the remalning other terminal is coupled to ground.
For a better understanding of the present invention, together with other and further objects, reference is made to the following description, taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS
_ Figure 1 is a schematic diagram of an AM stereo decoder embodying the present invention in one form;
Figure 2 is a functional block diagram showing the PLL 20 of Figure 1 in greater detail; and Figure 3 is a schematic of an alternative interface circuit which may be used with the IC of Figure 1 in place of the interface circuit (Q3 and associated components) shown in that Figure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
-Figure 1 is a schematic diagram of a simplified AM stereo decoder 10 in accordance with the present invention. The particular decoder illustrated in Figure 1 is arranged for decoding independent sideband (ISB) AM
stereo signals. It should be recognized, however, that the pTesent invention can be used in constructing decoders suitable for decoding other types of AM stereo signals which contain amplitude modulation representative of L+R
information and angle modulation, e.g. phase or frequency modulation, repIesentative of L-R information.
The heart of the decoder illustrated in Figure 1 is an existing, low-cost IC known as a "567" tone detector, which is available from several manufacturers - ~2~0~

including Signetics (NE/SE 567), National SemiconductoI
(LM 567), and others. The "567" IC is intended for use as a tone and frequency decoder, but the present invention makes novel use of this IC for detecting the phase 5 modulation component of composite intermediate frequency (IF) AM stereo signals.
The "567" IC includes a phase-locked loop (PLL) 2û, a quadrature detector 22, an amplifier 24, and an output transistor 25. For a detailed description of this 10 IC, reference i5 made to the technical literature published by the several manufacturers of this type IC.
The decoder shown in Figure 1 is arranged for use in an AM stereo receiver wherein the received RF signal, with composite amplitude and phase modulation, is 15 frequency converted to a corresponding IF signal. The supplied IF composite signal is coupled to terminal 3 of the "567" IC via components Rl, Cl, C2. Within the IC the IF composite signal is coupled to an input of PLL 20, which generates a reference signal that becomes locked in 2û frequency and phase synchronism to the carrier component of the received composite IF signal. PLL 20 is shown in greater detail in Figure 2. External circuit components R12 and C10 are provided to tune the PLL's oscillator 2ûa so as to have a free-running frequency that corresponds to 25 the IF frequency of the receiver in which the decoder of Figure 1 is used. Typically this IF frequency is of the order to 450 KHz, or 26û KHz in some automotive receivers. Actually, oscillator 20a develops a pair of output signals which are substantially in quadrature with 30 respect to each other.
Phase-locked loop 20 includes a synchronous detector 20b in its control loop. The output signal from detector 20b is also available at terminal 2 of the IC.
When PLL 2û is locked, the AC component of this signal 35 corresponds to the phase deviation between the supplied IF
signal and the reference signal generated by the PLL's oscillator, which is in quadrature with the phase of the 7~.

carrier of the supplied IF signal. Accordingly, the signal available at terminal 2 will have audio frequency amplitude components which correspond to any phase modulation in the supplied IF signal, in addition to low frequency components which correspond to any phase deviation between the PLL's oscillator 2ûa and the carrier frequency in the supplied IF signal. The low frequency components are used in the PLL's control loop to maintain oscillator 2ûa in phase lock with the carrier of the IF
signal that is supplied to IC pin 3. In the case where the IF signal is an ISB AM stereo signal, for example, since synchronous detector 2ûb operates as a quadrature detector with respect to the supplied composite IF signal, the audio frequency components at IC pin 2 will represent the L-R or stereo difference signal information in the received signal.
The second IF reference signal developed by oscillator 2ûa in PLL 20 is supplied to synchronous detector 22. When the PLL is locked, this reference signal is in phase with the carrier of the supplied IF
signal. Therefore, detector 22 provides an output signal representative of the in-phase component of the supplied composite IF signal. This output signal is supplied to threshold amplifier 24 and output transistor 25, which provides at IC pin 8 a binary control signal indicating when the PLL oscillator is locked to the carrier frequency of the supplied IF signal.
Capacitor C7 serves as a low-pass filter for the phase detected signal supplied to amplifier 24, and serves to prevent rapid on and off switching of the output signal at pin 8. Such switching might occur during initial tuning of the receiver to an AM broadcast station because of transient signal outputs from synchronous detector 22.
Capacitor C6, in conjunction with resistors R13, R14, R15, capacitors Cll, C12 and operational amplifier A2 provides low-pass filtering for the signal from the output of the synchronous detector 20b in PLL 20. By controlling ~.2~1Q7~.

FET transistor Q2, the effective impedance presented by these elements at terminal 2 of the IC can be changed, which affects the response characteristics of the PLL, as will be explained later.
Transistor Q3, with its associated resistors R8, R9, R10, and Rll and capacitor C8, provides an inversion and a time delay for the binary control signal which is output from pin 8 of the IC. Transistor Q3 is "on", or conducting, when the binary signal at pin 8 is high, indicating that the PLL is not yet locked. When in the "on" condition, transistor Q3 grounds the gate of transistor Q2, thereby rendering Q2 non-conducting. When the binary signal at terminal 8 goes low, indicating that the PLL is locked, transistor Q3 turns off and capacitor C8 starts to charge through resistors R9, R10 and Rll.
Capacitor C8 and resistors R9, R10 and Rll serve as a delay circuit, so that a voltage sufficient to turn on FET
Q2 will appear at the gate input of Q2 only after a selected time period determined by selection of the values of capacitor C8 and resistors R9, R10, and Rll. In the preferred embodiment these values are chosen such that the time period is on the order of one second, but this time period can be made longer or shorter as desired It should be particularly noted that in the arrangement shown in Figure l, control of FET transistor Q2 provides both audio muting of the stereo difference signal translating channel during initial locking of the PLL and a variable impedance at terminal 2 of the IC.
Because of the manner in which transistor Q2 is 30 ' coupled between pin 2 of the IC, where the demodulated stereo difference (L-R) information is available, and amplifier A2, when Q2 is non-conducting (while PLL 20 is out-of-lock), the result is a muting of this stereo difference signal path during this period. Then, when detector 22 senses lock-in of PLL 20, this is indicated by a change in the state of the binary signal from pin 8.
This change is delayed by the previously mentioned delay circuit and thereafter gates transistor Q2 into a conducting state. This enables the stereo difference signal translation path by allowing the stereo difference signal (L-R) component from pin 2 of the IC to be coupled through to phase shift network 35 by the combination of AC
coupling capacitor C12, which has a large value of capacitance, and OP-AMP A2, where the signal is coupled to the inverting (-) input which presents a virtual ground for the lower frequency PLL control components that are also present at pin 2 of the IC. The amplified L-R signal is phase shifted in network 35 and coupled to sum and difference circuits 45 and 50, respectively, where it is combined with the phase shifted L+R signal to develop stereo L and R audio output signals.
Thus, upon initially tuning the receiver of Figure 1 to an AM stereo station the receiver will operate in a monophonic reception mode until PLL 20 locks to the IF carrier frequency of the received signal. Then after a selected delay, determined by the delay circuit comprising elements C8, R9, R10, Rll, the receiver will change to its stereophonic mode of operation. when the delay is made long enough to be clearly perceptible, this intentional delay of stereo operation is referred to as the "stereo bloom" feature, in that the sound heard becomes "fuller"
when receiver operation switches from mono to stereo. The sharpness of the transition can also be controlled if desired, so as to be either abrupt or a gradual smooth change from mono to stereo.
An additional function performed by transistor Q2 is to change the load impedance seen at terminal 2, which changes the response characteristics of PLL 20 by changing the time constant in the PLL's control loop. Before the PLL is locked to the carrier frequency of the IF signal, the signal at IC pin 2 is oscillatory, and the network consisting of capacitors C6, Cll, C12 with resistors R13, R14, R15 provides a relatively high impedance at IC pin

2. When PLL 20 becomes locked, transistor Q2 is gated into a conducting state, which changes the impedance presented at IC pin 2, providing a longer time constant for the PLL, so that the PLL will have a slower tracking response than it previously had. As a result, PLL 20 operates in two modes. In a first mode, PLL 20 has a wider bandwidth and shorter time constant (when the loop is not yet locked) for better signal acquisition performance, and in the second mode the PLL has a narrower bandwidth and longer time constant (when the loop is lû locked) for less susceptibility to noise during normal operation of the stereo decoder.
Figure 3 shows an alternative circuit for connection between IC pin 8 in Figure 1 and the gate terminal of FET transistor Q2. The circuit of Figure 3 provides a delay in the output of signal from terminal 8 for turning on transistor Q2, but it provides a rapid turn off of transistor Q2 when PLL 20 loses lock.
The output of IC pin 8 is high prior to PLL 20 being locked and this charges capacitor C14 through diode Dl. When lock is achieved, pin 8 goes to a low voltage level, near ground, and capacitor C14 slowly discharges through resistors R21 and R22. When the output of pin 8 is in its high state, the output of differential amplifier A4 is low, so that transistor Q2 is in a non-conducting state. When pin 8 goes to its low state, the output of amplifier A4 rises slowly as capacitor C14 discharges.
When pin 8 goes to its high state again, because phase lock has been lost in the PLL, capacitor C14 is rapidly charged through resistor R20 and diode Dl. Accordingly 9 the circuit as shown in Figure 3 provides a slowly rising voltage level to the gate of transistor Q2 in response to a change in the output of IC pin 8 from a high to a low binary state. The slowly rising gate voltage delays the turn on of FET transistor Q2 and, therefore, delays the enabling of the stereo difference signal channel, thereby providing the "stereo bloom" effect. Then, when the PLL
loses lock, the output from IC pin 8 changes from low to ~2~

high and, because the output of amplifier A4 drops rapidly, transistor Q2 is turned off, or becomes non-conducting, rapidly. This provides fast muting of the stereo difference signal channel when the PLL loses lock.
The specific decoder configuration shown in the circuit diagram of Figure 1 is configured to demodulate an independent sideband, or ISB, AM stereo signal. The circuit includes a FET transistor Ql which is arranged to provide inverse modulation of the composite IF signal in accordance with the teachings of my prior U.S. Patent which was referenced earlier herein. The circuit further includes phase shift networks 35 and 40 arranged to introduce a 90 relative phase difference between the stereo sum and difference signals prior to their being combined in the sum and difference matrix circuits 45 and 5û, where stereo audio output signals L and R are developed. In the circuit of Figure 1, a composite IF
signal is supplied to input terminal 12, and an amplitude demodulated audio frequency (AF) signal containing stereo sum information (L+R) is supplied to input terminal 14.
The latter may have been derived from the composite IF
signal using a conventional envelope detector, for example.
The input stereo sum signal is coupled to amplifier Al, whose output is AC coupled jointly to the gate terminal of FET Ql and to the input of phase shift network 40. The input amplifier Al receives a reference voltage from a voltage divider comprising resistors R3 and R4 connected between the supply voltage Vcc and ground.
Amplifier A1 also has a feedback resistor R5.
FET Q1 has its drain terminal coupled to the IF
input lead between capacitors Cl and C2. Its source terminal is coupled to the supply voltage Vcc through variable resistor R7 bypassed by C5. As a result, Ql presents a variable impedance for the composite IF signal present at its drain terminal. Since this impedance is controlled by the L+R signal applied to the gate of FET
Ql, the result is that the composite IF signal available at the junction between capacitors Cl and C2 will be inversely amplitude modulated by the L+R signal, provided L+R is supplied in the correct phase. This accomplishes distortion cancellation in accordance with the teachings of my prior U.S. Patent No. 4,018,994 referenced earlier herein. The inversely modulated composite IF signal is then coupled through capacitor C2 to the input pin 3 of the IC.
Following is a list of the sample values for various components employed in the specific embodiments of the invention shown in Figures 1 and 3. Those skilled in the art will recognize that other values and other embodiments are possible.
TACLE
Rl = 4.7K Cl = 0.1 uf R2 = 160K C2 = 22 pf R3 = 20K C3 = û.l uf R4 = 20K C4 = 0.1 uf R5 = 330K C5 = 0.047 uf 2û R6 = 160K C6 = O.û5 uf R7 = lOK potentiometer C7 = 6.8 uf R8 = 20K C8 = 100 uf R9 = 30K C9 = 0.1 uf R10 = lOOK C10 = 330 pf Rll = 100 Cll = 2.2 uf R12 = lOK variable C12 = 150 uf R13 = lK C13 = 22 uf R14 = lK Al = LM358M
R15 = 100 A2 = LM324N
R16 = 2K A4 = LM358M
R17 = 2K Dl = IN914 R18 = 39K Ql = FET 2N5248 R20 = 470 Q2 = FET 2N5248 R21 = 20ûK Q3 = 2N3904 R22 = 680K
R23 = 15ûK IC = "567"
R24 = 510K

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The embodiment of Figure 1 is particularly arranged for decoding a received independent sideband (ISB) AM stereo signal Those skilled in the art will recognize, however, that the phase demodulation technique, the phase-locked loop variable bandwidth technique, and the stereo enabling, stereo bloom and muting techniques disclosed herein are applicable generally in decoders for other types of AM stereo signals. Accordingly, these techniques can be used in AM stereo receivers configured for other AM stereo systems.

Claims (2)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. An improved stereo radio receiver which includes a stereo information decoder, wherein the improvement comprises:
means responsive to a received intermediate frequency stereo signal for developing an output signal representative of the stereo sum signal component thereof;
and means, having a controllable variable impedance to ground for IF frequencies, having said received IF stereo signal coupled across said impedance, and having said output signal coupled to control the variation of said impedance, for inversely amplitude modulating said IF signal.

2. A stereo receiver according to claim 1, wherein said controllable variable impedance is a field effect transistor having a control terminal and a pair of other terminals, and wherein said output signal is coupled to said control terminal, said IF signal is coupled to one of said pair of other terminals and the remaining other terminal is coupled to ground.