BE1015721A3 - Werkwijze voor het reduceren van de contactweerstand van de aansluitgebieden van een halfgeleiderinrichting. - Google Patents
Werkwijze voor het reduceren van de contactweerstand van de aansluitgebieden van een halfgeleiderinrichting. Download PDFInfo
- Publication number
- BE1015721A3 BE1015721A3 BE2003/0546A BE200300546A BE1015721A3 BE 1015721 A3 BE1015721 A3 BE 1015721A3 BE 2003/0546 A BE2003/0546 A BE 2003/0546A BE 200300546 A BE200300546 A BE 200300546A BE 1015721 A3 BE1015721 A3 BE 1015721A3
- Authority
- BE
- Belgium
- Prior art keywords
- metal
- semiconductor device
- reducing
- contact resistance
- connection areas
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 3
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 239000002184 metal Substances 0.000 abstract 9
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 229910021332 silicide Inorganic materials 0.000 abstract 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000005475 siliconizing Methods 0.000 abstract 1
Classifications
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
De uitvinding heeft betrekking op een werkwijze ter vervaardiging van een halfgeleiderinrichting met een halfgeleiderstructuur met minstens één aansluitgebied vormend siliciumgebied in en/of op een oppervlak van een substraat. De methode bestaat uit het vormen van een metaalclusterlaag van een eerste , niet-siliciderend metaal, gevolgd door het afzetten van een metaallaag bestaande uit een tweede, siliciderend metaal. Een daaropvolgende warmtebehandeling zorgt voor de vorming van een metaalsilicide van het tweede metaal, waarbij de atomen van het eerste metaal verplaatst worden in een richting nagenoeg loodrecht op het oppervlak van het substraat. Volgens de uitvinding worden de atomen het eerste metaal verplaatst door het Kirkendall effect tot onder het metaalsilicide. Bij vervaardiging van bijvoorbeeld een MOST zijn daaraan zowel ter plaatse van het aanvoer- en afvoergebied als ter plaatse van de poortelektrode voordelen verbonden.
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
BE2003/0546A BE1015721A3 (nl) | 2003-10-17 | 2003-10-17 | Werkwijze voor het reduceren van de contactweerstand van de aansluitgebieden van een halfgeleiderinrichting. |
EP04077815A EP1524686A1 (en) | 2003-10-17 | 2004-10-13 | Method for reducing the contact resistance of the connection regions of a semiconductor device |
TW093131117A TWI248651B (en) | 2003-10-17 | 2004-10-14 | Method for reducing the contact resistance of the connection regions of a semiconductor device |
JP2004301664A JP4722448B2 (ja) | 2003-10-17 | 2004-10-15 | 半導体の接続領域の接触抵抗を低減する方法 |
US10/966,141 US7189648B2 (en) | 2003-10-17 | 2004-10-15 | Method for reducing the contact resistance of the connection regions of a semiconductor device |
CNB2004100981418A CN100437943C (zh) | 2003-10-17 | 2004-10-18 | 一种半导体器件及其制造方法 |
US11/526,116 US7320939B2 (en) | 2003-10-17 | 2006-09-22 | Semiconductor device fabricated by a method of reducing the contact resistance of the connection regions |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
BE2003/0546A BE1015721A3 (nl) | 2003-10-17 | 2003-10-17 | Werkwijze voor het reduceren van de contactweerstand van de aansluitgebieden van een halfgeleiderinrichting. |
Publications (1)
Publication Number | Publication Date |
---|---|
BE1015721A3 true BE1015721A3 (nl) | 2005-07-05 |
Family
ID=34318707
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BE2003/0546A BE1015721A3 (nl) | 2003-10-17 | 2003-10-17 | Werkwijze voor het reduceren van de contactweerstand van de aansluitgebieden van een halfgeleiderinrichting. |
Country Status (6)
Country | Link |
---|---|
US (2) | US7189648B2 (nl) |
EP (1) | EP1524686A1 (nl) |
JP (1) | JP4722448B2 (nl) |
CN (1) | CN100437943C (nl) |
BE (1) | BE1015721A3 (nl) |
TW (1) | TWI248651B (nl) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
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US7405112B2 (en) * | 2000-08-25 | 2008-07-29 | Advanced Micro Devices, Inc. | Low contact resistance CMOS circuits and methods for their fabrication |
JP4011024B2 (ja) | 2004-01-30 | 2007-11-21 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
US7101744B1 (en) * | 2005-03-01 | 2006-09-05 | International Business Machines Corporation | Method for forming self-aligned, dual silicon nitride liner for CMOS devices |
US7939440B2 (en) * | 2005-06-15 | 2011-05-10 | Spansion Llc | Junction leakage suppression in memory devices |
JP4981307B2 (ja) * | 2005-11-18 | 2012-07-18 | シャープ株式会社 | 電子装置、電子回路及び電子機器 |
US20070131985A1 (en) * | 2005-11-29 | 2007-06-14 | Kazunori Fujita | Semiconductor device and method for manufacturing the same |
US7659580B2 (en) * | 2005-12-02 | 2010-02-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
TW200742087A (en) * | 2006-03-14 | 2007-11-01 | Koninkl Philips Electronics Nv | Source and drain formation |
JP4864498B2 (ja) * | 2006-03-15 | 2012-02-01 | 株式会社東芝 | 半導体装置およびその製造方法 |
WO2008007748A1 (fr) | 2006-07-13 | 2008-01-17 | National University Corporation Tohoku University | dispositif semi-conducteur |
JP4247257B2 (ja) | 2006-08-29 | 2009-04-02 | 株式会社東芝 | 半導体装置の製造方法 |
JP2008078403A (ja) * | 2006-09-21 | 2008-04-03 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
EP1928021A1 (en) * | 2006-11-29 | 2008-06-04 | Interuniversitair Microelektronica Centrum (IMEC) | Method of manufacturing a semiconductor device with dual fully silicided gate |
US7812414B2 (en) * | 2007-01-23 | 2010-10-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid process for forming metal gates |
US7754554B2 (en) * | 2007-01-31 | 2010-07-13 | Globalfoundries Inc. | Methods for fabricating low contact resistance CMOS circuits |
US20080191285A1 (en) * | 2007-02-09 | 2008-08-14 | Chih-Hsin Ko | CMOS devices with schottky source and drain regions |
JP4960125B2 (ja) | 2007-03-22 | 2012-06-27 | 株式会社東芝 | 半導体装置およびその製造方法 |
US20090134469A1 (en) * | 2007-11-28 | 2009-05-28 | Interuniversitair Microelektronica Centrum (Imec) Vzw | Method of manufacturing a semiconductor device with dual fully silicided gate |
JP5221112B2 (ja) | 2007-11-29 | 2013-06-26 | 株式会社東芝 | 半導体装置の製造方法および半導体装置 |
KR20090074561A (ko) * | 2008-01-02 | 2009-07-07 | 주식회사 하이닉스반도체 | 반도체소자의 컨택 형성방법 |
US8536660B2 (en) * | 2008-03-12 | 2013-09-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid process for forming metal gates of MOS devices |
WO2009133509A1 (en) * | 2008-04-29 | 2009-11-05 | Nxp B.V. | Integrated circuit manufacturing method and integrated circuit |
US20100052077A1 (en) * | 2008-08-27 | 2010-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-k metal gate structure including buffer layer |
JP5611574B2 (ja) * | 2009-11-30 | 2014-10-22 | 株式会社東芝 | 抵抗変化メモリ及びその製造方法 |
JP5538975B2 (ja) * | 2010-03-29 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
CN102214687A (zh) * | 2010-04-07 | 2011-10-12 | 中国科学院微电子研究所 | 一种栅堆叠结构、半导体器件及二者的制造方法 |
CN103137486B (zh) * | 2011-11-30 | 2016-08-03 | 中国科学院微电子研究所 | 半导体器件制造方法 |
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US20130241007A1 (en) | 2012-03-15 | 2013-09-19 | International Business Machines Corporation | Use of band edge gate metals as source drain contacts |
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CN110931361B (zh) * | 2019-11-28 | 2023-03-14 | 中国科学院微电子研究所 | 一种mos器件、制造方法、集成电路及电子设备 |
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TW200518234A (en) | 2005-06-01 |
US20070020930A1 (en) | 2007-01-25 |
JP4722448B2 (ja) | 2011-07-13 |
TWI248651B (en) | 2006-02-01 |
CN1667808A (zh) | 2005-09-14 |
US20050112875A1 (en) | 2005-05-26 |
EP1524686A1 (en) | 2005-04-20 |
CN100437943C (zh) | 2008-11-26 |
US7320939B2 (en) | 2008-01-22 |
JP2005123626A (ja) | 2005-05-12 |
US7189648B2 (en) | 2007-03-13 |
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