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Abdurohman et al., 2010 - Google Patents

The new embedded system design methodology for improving design process performance

Abdurohman et al., 2010

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Document ID
2265412673686732742
Author
Abdurohman M
Sutikno S
Sasongko A
et al.
Publication year
Publication venue
arXiv preprint arXiv:1005.0931

External Links

Snippet

Time-to-market pressure and productivity gap force vendors and researchers to improve embedded system design methodology. Current used design method, Register Transfer Level (RTL), is no longer be adequate to comply with embedded system design necessity. It …
Continue reading at arxiv.org (PDF) (other versions)

Classifications

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    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G06F17/5031—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
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    • G06F17/5009—Computer-aided design using simulation
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    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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