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Mehta et al., 2006 - Google Patents

A low-energy reconfigurable fabric for the supercisc architecture

Mehta et al., 2006

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Document ID
12582692331441928005
Author
Mehta G
Stander J
Lucas J
Hoare R
Hunsaker B
Jones A
Publication year
Publication venue
Journal of Low Power Electronics

External Links

Snippet

Hardware acceleration using Field Programmable Gate Arrays (FPGAs) has become increasingly popular for computationally intensive Digital Signal Processing (DSP) applications. Unfortunately, while FPGAs have a reasonably tractable Computer Aided …
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Classifications

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    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
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    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
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    • G—PHYSICS
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