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Higgins et al., 2000 - Google Patents

BSM2: Next generation boundary-scan master

Higgins et al., 2000

Document ID
746343518872644579
Author
Higgins F
Srinivasan R
Publication year
Publication venue
Proceedings 18th IEEE VLSI Test Symposium

External Links

Snippet

Boundary-scan (BS) strategies require successful coordination of BS activities for the devices integrated on boards and systems. The original Boundary-Scan Master (BSM) chip was developed to achieve this coordination. We have recently designed the next generation …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
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    • G01R31/318572—Input/Output interfaces
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    • G01R31/318558—Addressing or selecting of subparts of the device under test
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    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
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    • G01R31/318583—Design for test
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    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
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    • G—PHYSICS
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    • G—PHYSICS
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    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation

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