Nothing Special   »   [go: up one dir, main page]

Modarressi et al., 2009 - Google Patents

A hybrid packet-circuit switched on-chip network based on SDM

Modarressi et al., 2009

View PDF
Document ID
7466798437898140830
Author
Modarressi M
Sarbazi-Azad H
Arjomand M
Publication year
Publication venue
2009 Design, Automation & Test in Europe Conference & Exhibition

External Links

Snippet

In this paper, we propose a novel on-chip communication scheme by dividing the resources of a traditional packet-switched network-on-chip between a packet-switched and a circuit- switched sub-network. The former directs packets according to the traditional packet …
Continue reading at www.date-conference.com (PDF) (other versions)

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/25Routing or path finding through a switch fabric
    • H04L49/253Connections establishment or release between ports
    • H04L49/254Centralized controller, i.e. arbitration or scheduling
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Switching fabric construction
    • H04L49/109Switching fabric construction integrated on microchip, e.g. switch-on-chip
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/06Deflection routing, e.g. hot-potato routing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/30Peripheral units, e.g. input or output ports
    • H04L49/3009Header conversion, routing tables or routing tags
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
    • H04L12/46Interconnection of networks
    • H04L12/4604LAN interconnection over a backbone network, e.g. Internet, Frame Relay
    • H04L12/462LAN interconnection over a bridge based backbone
    • H04L12/4625Single bridge functionality, e.g. connection of two networks over a single bridge
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/60Router architecture
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems
    • H04L12/56Packet switching systems
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/40Wormhole routing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/12Shortest path evaluation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/16Multipoint routing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/15Interconnection of switching modules
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/50Overload detection; Overload protection
    • H04L49/505Corrective Measures, e.g. backpressure
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic regulation in packet switching networks
    • H04L47/10Flow control or congestion control

Similar Documents

Publication Publication Date Title
Modarressi et al. A hybrid packet-circuit switched on-chip network based on SDM
US9634866B2 (en) Architecture and method for hybrid circuit-switched and packet-switched router
Effiong et al. Distributed and dynamic shared-buffer router for high-performance interconnect
Teimouri et al. Power and performance efficient partial circuits in packet-switched networks-on-chip
Gharan et al. A novel virtual channel implementation technique for multi-core on-chip communication
Sun et al. Architecting a congestion pre-avoidance and load-balanced wireless network-on-chip
Requena et al. Exploiting wiring resources on interconnection network: increasing path diversity
Lusala et al. A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications
Kumar et al. A survey for silicon on chip communication
Lusala et al. A SDM-TDM based circuit-switched router for on-chip networks
Salaheldin et al. Review of NoC-based FPGAs architectures
KR101028806B1 (en) Communication apparatus of soc network applicable to various communication methods
Parane et al. LBNoC: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA
Anjali et al. Design and evaluation of virtual channel router for mesh-of-grid based NoC
Zhou et al. A router architecture with dual input and dual output channels for Networks-on-Chip
Chen et al. Physical vs. virtual express topologies with low-swing links for future many-core nocs
Jain et al. Asynchronous bypass channels: Improving performance for multi-synchronous nocs
Nambinina et al. Extension of the lisnoc (network-on-chip) with an axi-based network interface
Langar et al. Virtual channel router architecture for network on chip with adaptive inter-port buffers sharing
Kwa et al. Small virtual channel routers on FPGAs through block RAM sharing
Sethi et al. Bio-inspired NoC fault tolerant techniques using guaranteed throughput and best effort services
Lee et al. Design of a feasible on-chip interconnection network for a chip multiprocessor (cmp)
FallahRad et al. Cirket: A performance efficient hybrid switching mechanism for noc architectures
Raparti et al. Memory-aware circuit overlay NoCs for latency optimized GPGPU architectures
Zulkefli et al. A efficacy of different buffer size on latency of network on chip (NoC)