Nothing Special   »   [go: up one dir, main page]

Phyu et al., 2004 - Google Patents

An ultra low-power output feedback flip-flop

Phyu et al., 2004

Document ID
6546787380847189910
Author
Phyu M
Goh W
Yeo K
Publication year
Publication venue
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.

External Links

Snippet

We proposed a new low-power output feedback single edge-triggered flip-flop (FBFF) that eliminates unnecessary internal transitions at the precharge node. As a result, the proposed FBFF is able to achieve substantial power reduction with no impact on its latency. The …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234—Action, measure or step performed to reduce power consumption
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—INDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B60/00—Information and communication technologies [ICT] aiming at the reduction of own energy use
    • Y02B60/10—Energy efficient computing
    • Y02B60/12—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
    • Y02B60/1207—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply acting upon the main processing unit
    • Y02B60/1217—Frequency modification
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass

Similar Documents

Publication Publication Date Title
Kong et al. Conditional-capture flip-flop for statistical power reduction
US8341578B2 (en) Clock gater with test features and low setup time
Chung et al. A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops
Wang et al. A low-power double edge-triggered flip-flop with transmission gates and clock gating
US20180167058A1 (en) Clock gating cell for low setup time for high frequency designs
Lin et al. Fine-grained power gating for leakage and short-circuit power reduction by using asynchronous-logic
Huang et al. Anti-interference low-power double-edge triggered flip-flop based on C-elements
Stojanovic et al. A unified approach in the analysis of latches and flip-flops for low-power systems
Mahmoodi-Meimand et al. Self-precharging flip-flop (SPFF): A new level converting flip-flop
Xiang et al. Design of a low-power pulse-triggered flip-flop with conditional clock technique
Stojanovic et al. Comparative analysis of latches and flip-flops for high-performance systems
Kuamar et al. Low Power High Speed 15-Transistor Static True Single Phase Flip Flop
Wu et al. Low-power design of sequential circuits using a quasi-synchronous derived clock
Phyu et al. An ultra low-power output feedback flip-flop
Venkatraman et al. A robust, fast pulsed flip-flop design
Sivagnaname et al. Wide limited switch dynamic logic circuit implementations
Tiwari et al. Power gating technique for reducing leakage power in digital asynchronous GasP circuits
Maheshwari A Comparative Analysis for Low-voltage, Low-power, and Low-energy Flip-flops
Wang et al. Low Power Explicit-Pulsed Single-Phase-Clocking Dual-edge-triggering Pulsed Latch Using Transmission Gate
Huang et al. Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements
Mukherjee et al. Design and implementation of low power dual edge triggered flip-flop using GDI and TG for high speed FIR filter
Wang et al. Low power and high performance Zipper domino circuits with charge recycle path
Rao et al. Design of low power pulsed flip-flop using sleep transistor scheme
Pallavi et al. Design of 4-Bit Synchronous Counter Using TSPC-SVL T Flip-Flop for Power Reduction
Rajshekar et al. Power efficient multiplexer using DLDFF synchronous counter