Nothing Special   »   [go: up one dir, main page]

Pasricha et al., 2010 - Google Patents

On-chip communication architectures: system on chip interconnect

Pasricha et al., 2010

Document ID
5050031618354987599
Author
Pasricha S
Dutt N
Publication year

External Links

Snippet

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so …
Continue reading at books.google.com (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/16—Constructional details or arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234—Action, measure or step performed to reduce power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

Similar Documents

Publication Publication Date Title
Pasricha et al. On-chip communication architectures: system on chip interconnect
Jerraya et al. Multiprocessor systems-on-chips
US6587905B1 (en) Dynamic data bus allocation
Yoo et al. Low-power noc for high-performance soc design
Soni VLSI Implementation of a Wormhole Runtime Reconfigurable Processor
Greaves System on Chip Design and Modelling
Kim et al. Design of low-power coarse-grained reconfigurable architectures
Bahn et al. On design and application mapping of a Network-on-Chip (NoC) architecture
Wingard Socket-based design using decoupled interconnects
Sarekokku et al. Design and Implementation of APB Bridge based on AMBA AXI 4.0
Chang et al. Design of on-chip bus with OCP interface
Reehal Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs
Nagaraju et al. Design of Multiple Master/Slave Memory Controllers with AMBA Bus Architecture
Sombatsiri et al. An AMBA hierarchical shared bus architecture design space exploration method considering pipeline, burst and split transaction
Patterson et al. Slotless module-based reconfiguration of embedded FPGAs
Barkalov et al. Design of Embedded Systems
Donlin Applications, design tools and low power issues in FPGA reconfiguration
Koh A reconfigurable multiprocessor system for DSP behavioral simulation
Koti Physical design of USB1. 1
Pasricha COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip
Fujiwara et al. A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting fpga designs
Gebhardt Energy-efficient design of an asynchronous network-on-chip
Cesário et al. HW/SW interfaces design of a VDSL modem using automatic refinement of a virtual architecture specification into a multiprocessor SoC: a case study
Gudla Design and implementation of clocked Open Core Protocol interfaces for Intellectual Property cores and on-chip network fabric
Balasingam Modular, Configurable Bus Architecture Targeted for Ease of IP Reuse on System on Chip and ASIC Devices