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Link Testing: a Survey of Current Trends in Network on Chip

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Abstract

As an excellent interconnection model, Network on chip (NoC) addresses different on-chip communication problems and can meet different requirements of performance, cost and reliability. Currently, with the growth of technology practice, wire-based interconnections are more and more unreliable. Consequently, growing sources of unreliability directly impact upon both signals and wires leading to some kinds of while misbehaviors in wires called faults. The literature offers various mechanisms designed for detection and diagnosis of such faults. However, this current paper aims to comprehensively survey these various state of art mechanisms of designed for detection and diagnosis of such faults and discusses them in detail in a way that is quite novel, not found in the previous publications. This is the pioneering survey paper which is concerned with classifying link testing approaches in two Online and Offline categories and extracts some conceptualizations to assist the research community. Besides making comparison among various link testing mechanisms on different parameters in the typical comparative table, detailed explanations are also presented about these parameters in NoC architecture.

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References

  1. Abad P, Prieto P, Menezo LG, Puente V, Gregorio J-Á (2012) Topaz: An open-source interconnection network simulator for chip multiprocessors and supercomputers. In: Proceeding IEEE/ACM International Symposium on Networks on Chip (NoCS), pp 99–106

  2. Abdel-Khalek R, Bertacco V (2012) Functional post-silicon diagnosis and debug for networks-on-chip. In: Proceeding IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp 557–563

  3. Achballah AB, Saoud SB (2013) A survey of network-on-chip tools. arXiv preprint arXiv:13122976

  4. Acken JM, Millman SD (1991) Accurate modeling and simulation of bridging faults. In: Proceedings IEEE Custom Integrated Circuits Conference, pp 17.14/11–17.14/14

  5. Agarwal A, Iskander C, Shankar R (2009) Survey of network on chip (NOC) architectures & contributions. Journal of Engineering, Computing and Architecture 3(1):21–27

    Google Scholar 

  6. Aitken RC (1999) Nanometer technology effects on fault models for IC testing. Computer 11:46–51

    Article  Google Scholar 

  7. Alliance V (2001) Virtual component interface standard. Online: http://www.vsiorg/library/specs/summary.html

  8. Alliance O (2003) Open Core Protocol Specification. Release,

  9. ARM A (2004) AXI Protocol Specification, version 10 www arm com, ARM March.

  10. Association SI (2009) ITRS: International Technology Roadmap for Semiconductors.

  11. Association SI (2012) ITRS: International Technology Roadmap for Semiconductors.

  12. Attarha A, Nourani M (2001) Testing interconnects for noise and skew in gigahertz SoCs. In: IEEE, p 305

  13. Attia B, Chouchene W, Zitouni A, Tourki R (2011) Network interface sharing for SoCs based NoC. In: Proceeding IEEE Conference on Communications, Computing and Control Applications (CCCA), pp 1–6

  14. Babaei S, Mansouri M, Aghaei B, Khadem-Zadeh A (2011) Online-structural testing of routers in network on Chip. World Applied Sciences Journal 14(9):1374–1383

    Google Scholar 

  15. Barger A, Goren D, Kolodny A (2004) Design and modelling of network on chip interconnects using transmission lines. In: Proceeding IEEE Conference on Electronics, Circuits and Systems, pp 403–406

  16. Barsky R, Wagner IA (2004) Reliability and yield: a joint defect-oriented approach. In: Proceedings of 19th International symposium on defect and fault tolerance in VLSI Systems (DFT’04). Cannes, France, pp 2–10

  17. Bengtsson T, Jutman A, Kumar S, Ubar R, Peng Z (2006) Off-line testing of delay faults in NoC interconnects. In: Proceeding 9th IEEE EUROMICRO Conference on Digital System Design: DSD Architectures, Methods and Tools, pp 677–680

  18. Benini L, De Micheli G (2002) Networks on chips: a new SoC paradigm. Computer 35(1):70–78

    Article  Google Scholar 

  19. Ben-Itzhak Y, Zahavi E, Cidon I, Kolodny A (2012) HNOCS: modular open-source simulator for heterogeneous NoCs. In: Proceeding IEEE Conference on Embedded Computer Systems (SAMOS), pp 51–57

  20. Bhojwani P, Mahapatra R (2003) Interfacing cores with on-chip packet-switched networks. In: Proceeding IEEE International Conference on VLSI Design, pp 382–387

  21. Bhowmik B, Biswas S, Deka JK (2015) A packet address driven test strategy for stuck-at faults in networks-on-chip interconnects. In: Proceeding 23th IEEE Mediterranean Conference on Control and Automation (MED), pp 176–183

  22. Binkert N, Beckmann B, Black G, Reinhardt SK, Saidi A, Basu A, Hestness J, Hower DR, Krishna T, Sardashti S (2011) The gem5 simulator. ACM SIGARCH Computer Architecture News 39(2):1–7

    Article  Google Scholar 

  23. Bjerregaard T, Mahadevan S (2006) A survey of research and practices of network-on-chip. ACM Computing Surveys (CSUR) 38(1):1

    Article  Google Scholar 

  24. Bondavalli A, Chiaradonna S, Di Giandomenico F, Grandoni F (2000) Threshold-based mechanisms to discriminate transient from intermittent faults. Computers, Transactions on IEEE 49(3):230–245

    Article  Google Scholar 

  25. Bryant R, Schuster M (1983) Fault simulation of MOS digital circuits. VLSI Design 4(6):24–30

    Google Scholar 

  26. Chai S, Wu C, Li Y, Yang Z (2008) A NoC simulation and verification platform based on systemC. In: Proceeding IEEE International Conference on Computer Science and Software Engineering, pp 423–426

  27. Chen W, Gupta SK, Breuer MA (1997) Analytic models for crosstalk delay and pulse analysis under non-ideal inputs. In: Proceedings of International test conference, pp 809–818

  28. Cheng AC (2002) Comprehensive study on designing memory BIST: algorithms, implementations and trade-offs. EECS 579, advanced computer architecture lab, Department of electrical engineering and computer science, The University of Michigan Ann Arbor, Michigan

  29. Chouchene W, Attia B, Zitouni A, Abid N, Tourki R A (2011) low power network interface for network on chip. In: Proceeding IEEE International Multi-Conference on Systems, Signals and Devices (SSD), pp 1–6

  30. ITRS: International technology roadmap for semiconductors. www.itrs2.net. Accessed June 2016

  31. Concatto C, Almeida P, Kastensmidt F, Cota É, Lubaszewski M, Herve M (2009) Improving yield of torus NoCs through fault-diagnosis-and-repair of interconnect faults. In: Proceeding 15th IEEE International On-Line Testing Symposium, pp 61–66

  32. Coppola M, Curaba S, Grammatikakis MD, Maruccia G, Papariello F (2004) OCCN: a network-on-chip modeling and simulation framework. In: Proceeding IEEE conference on Design, automation and test in Europe, Volume 3, p 30174

  33. Cota EF, Kastensmidt FGdL, Santos MCd, Hervé MB, Almeida PRVd, Meirelles PRM, Amory AdM, Lubaszewski MS (2008) A high-fault-coverage approach for the test of data, control, and handshake interconnects in mesh networks-on-chip. IEEE transactions on computers New York Vol 57, no 9 (Sept 2008), p 1202–1215

  34. Cota É, Kreutz M, Zeferino CA, Carro L, Lubaszewski M, Susin A (2003) The impact of NoC reuse on the testing of core-based systems. In: Proceedings IEEE VLSI Test Symposium, pp 128–133

  35. Cuviello M, Dey S, Bai X, Zhao Y (1999) Fault modeling and simulation for crosstalk in system-on-chip interconnects. In: Proceeding IEEE/ACM international conference on Computer-aided design, pp 297–303

  36. Dalirsani A (2015) Self-diagnosis in network-on-chips. Doctoral Dissertation, University of Stuttgart

  37. De Micheli G, Benini L (2002) Networks on chip: a new paradigm for systems on chip design. In: Proceedings Design, Automation & Test in Europe Conference & Exhibition, pp 0418–0418

  38. De Micheli G, Seiculescu C, Murali S, Benini L, Angiolini F, Pullini A (2010) Networks on chips: from research to products. In: Proceeding ACM/IEEE Design Automation Conference (DAC), pp 300–305

  39. Duato J, Yalamanchili S, Ni LM (2003) Interconnection networks: an engineering approach. Morgan Kaufmann

  40. Ebrahimi M, Daneshtalab M, Neishaburi MH, Mohammadi S, Afzali-Kusha A, Plosila J, Tenhunen H (2009) An efficent dynamic multicast routing protocol for distributing traffic in NOCs. In: Proceedings EDAA Conference on Design, Automation and Test in Europe, pp 1064–1069

  41. Ebrahimi M, Daneshtalab M, Liljeberg P, Plosila J, Tenhunen H (2010) A high-performance network interface architecture for NoCs using reorder buffer sharing. In: Proceeding IEEE Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pp 546–550

  42. Fiorin L, Sami M (2014) Fault-tolerant network interfaces for networks-on-Chip. IEEE Transactions on Dependable and Secure Computing 11(1):16–29

    Article  Google Scholar 

  43. Fiorin L, Micconi L, Sami M (2011) Design of fault tolerant network interfaces for nocs. In: Proceeding IEEE Euromicro Conference on Digital System Design (DSD), pp 393–400

  44. Fu B, Ampadu P (2009) On hamming product codes with type-II hybrid ARQ for on-chip interconnects. Circuits and Systems I: Regular Papers, IEEE Transactions on 56(9):2042–2054

    Article  MathSciNet  Google Scholar 

  45. Gebali F, Elmiligi H, El-Kharashi MW (2011) Networks-on-chips: theory and practice. CRC Press

  46. Genko N, Atienza D, De Micheli G, Mendias JM, Hermida R, Catthoor F (2005) A complete network-on-chip emulation framework. In: Proceeding IEEE Design, Automation and Test in Europe, pp 246–251

  47. Genko N, Atienza D, De Micheli G, Benini L (2007) Feature-NoC emulation: a tool and design flow for MPSoC. IEEE Circuits and Systems Magazine 7(4):42–51

    Article  Google Scholar 

  48. Ghofrani A, Parikh R, Shamshiri S, DeOrio A, Cheng K-T, Bertacco V (2012) Comprehensive online defect diagnosis in on-chip networks. In: Proceedings 30th IEEE VLSI Test Symposium, pp 44–49

  49. Grecu C, Pande P, Ivanov A, Saleh R (2006a) BIST for network-on-chip interconnect infrastructures. In: Proceeding 24th IEEE VLSI Test Symposium, pp. 1–6

  50. Grecu C, Ivanov A, Saleh R, Sogomonyan ES, Pande PP (2006b) On-line fault detection and location for NoC interconnects. In: Proceeding 12th IEEE International On-Line Testing Symposium (IOLTS'06), pp. 145–150

  51. Grecu C, Ivanov A, Saleh R, Pande PP (2007) Testing network-on-chip communication fabrics. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(12):2201–2214

    Article  Google Scholar 

  52. Gupta A, Maheshwari V, Sharma S, Kar R (2015) Crosstalk noise and delay analysis for high speed on-chip global RLC VLSI interconnects with mutual inductance using 90 nm process technology. In: Proceedings IEEE Conference on Computing, Communication & Automation (ICCCA), pp 1215–1219

  53. Hahanov V, Yegorov O, Mostova K (2015) NoCs Design for Verification. Elektronika ir Elektrotechnika 75(3):45–48

    Google Scholar 

  54. Hassan AS, Agarwal VK, Nadeau-Dostie B, Rajski J (1992) BIST of PCB interconnects using boundary-scan architecture. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11(10):1278–1288

    Article  Google Scholar 

  55. Heat EW (2015) Context and motivations. University of L’Aquila

  56. Heck G, Guazzelli R, Moraes F, Calazans N, Soares R (2012) HardNoC: A platform to validate networks on chip through FPGA prototyping. In: Proceeding IEEE VIII Southern Conference on Programmable Logic (SPL), pp 1–6

  57. Hegde R, Shanbhag NR (2000) Toward achieving energy efficiency in presence of deep submicron noise. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8(4):379–391

    Article  Google Scholar 

  58. Hemani A, Jantsch A, Kumar S, Postula A, Oberg J, Millberg M, Lindqvist D (2000) Network on chip: an architecture for billion transistor era. In: Proceeding IEEE NorChip Conference.

  59. Henkel J, Wolf W, Chakradhar S (2004) On-chip networks: a scalable, communication-centric embedded system design paradigm. In: Proceedings IEEE International Conference on VLSI Design, pp. 845–851

    Google Scholar 

  60. Hervé M, Almeida P, Kastensmidt FL, Cota E, Lubaszewski M (2010) Concurrent test of network-on-chip interconnects and routers. In: Proceeding 11th Latin American Test Workshop.

  61. Ho R, Mai KW, Horowitz MA (2001) The future of wires. Proceedings IEEE 89(4):490–504

    Article  Google Scholar 

  62. Huang J, Wu H, Li T, Yang H, Sun Z (2015) VeriNP: A FPGA-based verification platform for general-purpose many-core network processors. In: International Conference on Computer Science and Intelligent Communication (CSIC), pp. 361–364

  63. Hussein MA, He J (2005) Materials' impact on interconnect process technology and reliability. IEEE Trans Semicond Manuf 18(1):69–85

    Article  Google Scholar 

  64. Jain L, Al-Hashimi B, Gaur M, Laxmi V, Narayanan A (2007) NIRGAM: a simulator for NoC interconnect routing and application modeling. In: Proceeding Europe Conference on Design, Automation and Test, pp 16–20

  65. Jantsch A, Tenhunen H (2003) Networks on chip. Springer 396

  66. Jerger NE, Peh L-S, Lipasti M (2008) Virtual circuit tree multicasting: a case for on-chip hardware multicast support. In: Proceeding IEEE Symposium on Computer Architecture, pp 229–240

  67. Jutman A, Ubar R, New RJ (2005) Built-in self-test scheme for soc interconnect. In: Proceedings WMSCI. Orlando, Florida, pp 19–24

    Google Scholar 

  68. Kakoee MR, Bertacco V, Benini L (2014) At-speed distributed functional testing to detect logic and delay faults in NoCs. IEEE Trans Comput 63(3):703–717

    Article  MathSciNet  Google Scholar 

  69. Karkar A, Mak T, Tong K-F, Yakovlev A (2016) A survey of emerging interconnects for on-Chip efficient multicast and broadcast in many-cores. IEEE Circuits and Systems Magazine 16(1):58–72

    Article  Google Scholar 

  70. Khasanvis S, Rahman M, Li M, Shi J, Moritz CA (2015) Architecting connectivity for fine-grained 3-D vertically integrated circuits. In: Proceedings IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp 175–180

  71. Kim J-S, Hwang M-S, Roh S, Lee J-Y, Lee K, Lee S-J, Yoo H-J (2004) On-chip network based embedded core testing. Proceedings IEEE International SOC Conference, In, pp 223–226

    Google Scholar 

  72. Kim M, Kim D, Sobelman GE (2006) Network-on-chip link analysis under power and performance constraints. In: Proceeding IEEE International Symposium on Circuits and Systems, pp. 4163–4166

  73. Kogel T, Doerper M, Wieferink A, Leupers R, Ascheid G, Meyr H, Goossens S (2003) A modular simulation framework for architectural exploration of on-chip interconnection networks. In: Proceeding IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp 7–12

  74. Krasteva YE, Criado F, de la Torre E, Riesgo T (2008) A fast emulation-based NoC prototyping framework. In: IEEE International Conference on Reconfigurable Computing and FPGAs, pp 211–216

  75. Krstic A, Cheng K-T (1998) Delay fault testing for VLSI circuits. Springer

  76. Kumar S, Jantsch A, Soininen J-P, Forsell M, Millberg M, Oberg J, Tiensyrja K, Hemani A (2000) A network on chip architecture and design methodology. In: Proceedings IEEE Computer Society Annual Symposium on VLSI, pp 105–112

  77. Kundu S, Zachariah ST, Chang Y-S, Tirumurti C (2005) On modeling crosstalk faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(12):1909–1915

    Article  Google Scholar 

  78. Lavo DB, Larrabee T, Chess B (1996) Beyond the byzantine generals: unexpected behavior and bridging fault diagnosis. In: Proceedings IEEE Test Conference, pp 611–619

  79. Lee K, Lee S-J, Yoo H-J (2004) SILENT: serialized low energy transmission coding for on-chip interconnection networks. In: Proceedings IEEE/ACM International conference on Computer-aided design, pp 448–451

  80. Lehtonen T, Liljeberg P, Plosila J (2007) Online reconfigurable self-timed links for fault tolerant NoC. VLSI design, doi:10.1155/2007/9467

  81. Lien J-C, Breuer MA (1991) Maximal diagnosis for wiring networks. In: Proceedings International Test Conference, pp 96–105

  82. Lin X, McKinley PK, Ni LM (1994) Deadlock-free multicast wormhole routing in 2-D mesh multicomputers. IEEE transactions on Parallel and Distributed Systems 5(8):793–804

    Article  Google Scholar 

  83. Lin S-Y, Shen W-C, Hsu C-C, Chao C-H, Wu A-Y (2009) Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2D–mesh based chip multiprocessor systems. In: Proceeding IEEE int symp VLSI design, automation, and test, pp 72–75

  84. Liu C, Cota E, Sharif H, Pradhan DK (2004) Test scheduling for network-on-chip with BIST and precedence constraints. In: Proceeding IEEE International Test Conference, pp 1369–1378

  85. Liu C, Link Z, Pradhan DK (2006) Reuse-based test access and integrated test scheduling for network-on-chip. In: Proceedings EBAA conference on Design, automation and test in Europe, pp 303–308

  86. Liu J, Harkin J, Li Y, Maguire L (2014) Online fault detection for Networks-on-Chip interconnect. In: Proceeding IEEE Conference on Adaptive Hardware and Systems (AHS), pp 31–38

  87. Lu Z, Thid R, Millberg M, Nilsson E, Jantsch A (2005) NNSE: nostrum network-on-chip simulation environment. Proceedings Swedish System-on-Chip Conference (SSoCC), pp. 1–4

  88. Mack CA (2011) Fifty years of Moore's law. IEEE Trans Semicond Manuf 24(2):202–207

    Article  Google Scholar 

  89. Marković D, Ljuština D, Cvijetić R, Ivošević D, Rohtek O, Rotim M (2001) The role of post-layout verification in microprocessor design. In: MIPRO International Convention.

  90. Maxwell PC, Aitken (1993) RC biased voting: a method for simulating CMOS bridging faults in the presence of variable gate logic thresholds. In: Proceedings International Test Conference, pp. 63–72

  91. Maxwell P, Hartanto I, Bentz L (2000) Comparing functional and structural tests. In: Proceeding International Test Conference, pp. 400–407

  92. Morgenshtein A, Cidon I, Kolodny A, Ginosar R (2004) Comparative analysis of serial vs parallel links in NoC. In: Proceeding IEEE International Symposium on System-on-Chip, pp 185–188

  93. Nazarian G (2008) On-line testing of routers in networks-on-chip. TU Delft, Delft University of Technology

  94. Nourani M, Attarha A (2001) Built-in self-test for signal integrity. In: ACM Proceeding annual Design Automation Conference, pp 792–797

  95. Nourani M, Attarha A, Chakrabarty K (2002) Signal integrity: fault modeling and testing in high-speed SoCs. In: SOC (System-on-a-Chip) Testing for Plug and Play Test Automation. Springer, pp 175–190

  96. Nourmandi-Pour R, Mousavian N (2013) A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC. Microelectron J 44(3):248–257

    Article  Google Scholar 

  97. Nourmandi-Pour R, Khadem-Zadeh A, Rahmani AM (2010) An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip. Microelectron J 41(7):417–429

    Article  Google Scholar 

  98. Ost L, Mello A, Palma J, Moraes F, Calazans N (2005) MAIA: a framework for networks on chip generation and verification. In: Proceeding ACM Asia and South Pacific Design Automation Conference, pp 49–52

  99. Pai V (2011) HW/SW codesign and design, evaluation of software framework for AcENoCs: An FPGA-Accelerated NoC Emulation Platform

  100. Palesi M, Kumar S, Patti D (2010) Noxim: Network-on-chip simulator

  101. Pande PP, Grecu C, Saleh R, De Micheli G (2005) Design, synthesis, and test of networks on chips. IEEE Design & Test of Computers 5:404–413

    Article  Google Scholar 

  102. Park ES, Mercer M, Williams T (1988) Statistical delay fault coverage and defect level for delay faults. In: Proceedings IEEE Test Conference on New Frontiers in Testing, pp 492–499

  103. Petersén K, Öberg J (2007) Toward a scalable test methodology for 2D–mesh network-on-chips. In: Proceeding conference on Design, automation and test in Europe, pp 367–372

  104. Puente V, Gregorio JA, Beivide R (2002) SICOSYS: an integrated framework for studying interconnection network performance in multiprocessor systems. In: Proceedin IEEE Euromicro Workshop on Parallel, Distributed and Network-based, pp 15–22

  105. Radetzki M, Feng C, Zhao X, Jantsch A (2013) Methods for fault tolerance in networks-on-chip. ACM Computing Surveys (CSUR) 46(1):8

    Article  Google Scholar 

  106. Raik J, Ubar R, Govind V (2007) Test configurations for diagnosing faulty links in NoC switches. In: Proceedings IEEE European Test Symposium (ETS), pp. 29–34

  107. Rodrigo S, Flich J, Duato J, Hummel M (2008) Efficient unicast and multicast support for CMPs. In: Proceeding IEEE/ACM International Symposium on Microarchitecture, pp 364–375

  108. Salminen E, Kulmala A, Hamalainen TD (2007) On network-on-chip comparison. In: Proceeding IEEE Euromicro Conference on Digital System Design Architectures, Methods and Tools, pp 503–510

  109. Salminen E, Kulmala A, Hamalainen TD (2008) Survey of network-on-chip proposals. white paper, OCP-IP:1–13

  110. Saltarelli P, Niazmand B, Raik J, Govind V, Hollstein T, Jervan G, Hariharan R (2015) A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers. In: Proceeding ACM 9th International Symposium on Networks-on-Chip, p 6

  111. Saponara S, Bacchillone T, Petri E, Fanucci L, Locatelli R, Coppola M (2014) Design of an NOC interface macrocell with hardware support of advanced networking functionalities. IEEE Trans Comput 63(3):609–621

    Article  MathSciNet  Google Scholar 

  112. Schaller RR (1997) Moore's law: past, present and future. IEEE Spectr 34(6):52–59

    Article  Google Scholar 

  113. Schelle G, Grunwald D (2006) Onchip interconnect exploration for multicore processors utilizing FPGAs. In: Proceeding 2nd Workshop on Architecture Research using FPGA Platforms, pp 1–4

  114. Segura J, Hawkins CF (2004) CMOS electronics: how it works, how it fails. John Wiley & Sons,

  115. Sgroi M, Sheets M, Mihal A, Keutzer K, Malik S, Rabaey J, Sangiovanni-Vencentelli (2001) A addressing the system-on-a-chip interconnect woes through communication-based design. In: Proceedings ACM annual Design Automation Conference, pp 667–672

  116. Shamshiri S, Cheng K-T (2010) Error-locality-aware linear coding to correct multi-bit upsets in SRAMs. In: Proceeding IEEE International Test Conference (ITC), pp 1–10

  117. Souri SJ, Banerjee K, Mehrotra A, Saraswat KC (2000) Multiple Si layer ICs: motivation, performance analysis, and design implications. In: Proceedings ACM Annual Design Automation Conference, pp 213–220

  118. Spear C (2006) SystemVerilog for verification, Synopsys. Inc,

  119. Spear C (2008) SystemVerilog for verification: a guide to learning the testbench language features. Springer Science & Business Media

  120. Strano A, Gómez C, Ludovici D, Favalli M, Gómez ME, Bertozzi D (2011) Exploiting network-on-chip structural redundancy for a cooperative and scalable built-in self-test architecture. In: Proceeding IEEE Europe Conference on Design, Automation & Test & Exhibition (DATE), pp 1–6

  121. Swaminathan K, Lakshminarayanan G, Lang F, Fahmi M, Ko S-B (2013) Design of a low power network interface for network on Chip. In: Proceedings IEEE Canadian Conference on Electrical and Computer Engineering, pp 1–4

  122. Tan J, Fresse V, Rousseau F (2016) Rapid prototyping of networks-on-Chip on multi-FPGA platforms. In: Proceeding MATEC Web of Conferences, EDP Sciences

  123. Tatas K, Siozios K, Soudris D, Jantsch A (2014a) Designing 2D and 3D network-on-chip architectures. Springer,

  124. Tatas K, Siozios K, Soudris D, Jantsch A (2014b) NoC Verification and Testing. In: Designing 2D and 3D Network-on-Chip Architectures. Springer, pp 147–159

  125. Theis TN (2000) The future of interconnection technology. IBM J Res Dev 44(3):379–390

    Article  MathSciNet  Google Scholar 

  126. Tran AT, Baas B (2012) NoCTweak: a highly parameterizable simulator for early exploration of performance and energy of networks on-chip. Technical Report ECE-VCL-2012-2, VLSI Computation Lab, ECE Department, University of California, Davis,

  127. Tsiligiannis G, Pierre L A (2012) mixed verification strategy tailored for networks on chip. In: Proceeding IEEE/ACM International Symposium on Networks on Chip (NoCS), pp 161–168

  128. Tuomi I (2002) The lives and death of Moore’s law. First Monday Peer-Reviewed Journal on the Internet 7(11). doi:10.5210/fm.v7i11.1000

  129. Ferrante A, Medardoni S, Bertozzi D (2008) Network interface sharing techniques for area optimized NoC architectures. In: Proceeding IEEE EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, pp 10–17

  130. Ubar R, Raik J (2003) Testing strategies for networks on chip. In: Networks on chip. Springer, pp 131–152

  131. Yu Q (2011) Transient and permanent error co-management for nanoscale networks-on-chip. PhD Dissertation, University of Rochester

  132. Yu Q, Ampadu P (2011) Transient and permanent error control for networks-on-chip. Springer Science & Business Media,

  133. Patel JH (1998) Stuck-at fault: a fault model for the next millennium. In: Proceedings International Test Conference, p. 1166

  134. Delmas-Bendhia S, Caignet F, Sicard E (2000) On Chip crosstalk characterization on deep submicron buses. In: Proceedings IEEE International Caracas Conference on Devices, Circuits and Systems, pp 1–5

  135. West BG (1999) At-speed structural test. In Proceedings International Tesr Conference, pp. 795-800

  136. Wang L, Jin Y, Kim H, Kim EJ (2009) Recursive partitioning multicast: a bandwidth-efficient routing for networks-on-Chip. In: Proceeding ACM/IEEE International Symposium on Networks-on-Chip, pp 64–73

  137. Weste NH, Eshraghian K (1985) Principles of CMOS VLSI design. Addison-Wesley New York, vol 188

  138. Vincentelli AS, Cohn J (2001) Platform-based design. IEEE Design & Test of Computers 18(6):23–33

  139. Wang D, Lo C, Vasiljevic J, Jerger NE, Steffan JG (2014) DART: a programmable architecture for NoC simulation on FPGAs. IEEE Trans Comput 63(3):664–678

    Article  MathSciNet  Google Scholar 

  140. Zhang Y, Wu N, Ge F, Chen X (2015) Collaborative verification and testing platform for NoC-based SoC. In: Proceeding World Congress on Engineering and Computer Science, San Francisco, California, USA

  141. Vitullo F, Saponara S, Petri E, Casula M, Fanucci L, Maruccia G, Locatelli R, Coppola M (2009) A reusable coverage-driven verification environment for Network-on-Chip communication in embedded system platforms. In: Proceeding IEEE Seventh Workshop on Intelligent solutions in Embedded Systems, pp 71–77

  142. Xiang D, Chakrabarty K, Fujiwara H (2016) Multicast-based testing and thermal-aware test scheduling for 3D ICs with a stacked network-on-chip. IEEE Trans Comput 65(9):2767–2779

    Article  MathSciNet  Google Scholar 

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Authors and Affiliations

  1. Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

    Babak Aghaei & Midia Reshadi

  2. Iran Telecommunication Research Center, ITRC, Tehran, Iran

    Ahmad Khademzadeh & Kambiz Badie

Authors
  1. Babak Aghaei
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  2. Ahmad Khademzadeh
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  3. Midia Reshadi
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  4. Kambiz Badie
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Corresponding author

Correspondence to Kambiz Badie.

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Responsible Editor: S. T. Chakradhar

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Aghaei, B., Khademzadeh, A., Reshadi, M. et al. Link Testing: a Survey of Current Trends in Network on Chip. J Electron Test 33, 209–225 (2017). https://doi.org/10.1007/s10836-017-5646-0

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  • DOI: https://doi.org/10.1007/s10836-017-5646-0

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