Abstract
Languages such as SystemC or SpecC offer modeling of hardware and whole system designs at a high level of abstraction. However, formal verification techniques are widely applied in the hardware design industry only for low level designs, such as a netlist or RTL. The higher abstraction levels offered by these new languages are not yet amenable to rigorous, formal verification. This paper describes how to apply predicate abstraction to SpecC system descriptions. The technique supports the concurrency constructs offered by SpecC. It models the bit-vector semantics of the language accurately, and can be used both for property checking and for checking refinement together with a traditional low-level design given in Verilog.
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Notes
We are grateful to Masahiro Fujita for clarifying this issue.
Thus, we implement a form of busy-waiting—this is wasteful if execution is the goal, but simplifies the model if the goal is model checking.
http://www.inf.ethz.ch/personal/daniekro/satabs/
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Acknowledgments
We thank Masahiro Fujita for numerous clarifications of the semantics of SpecC, and the anonymous referees for helpful suggestions.
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This paper is an extended version of [29].
This research was sponsored by the Gigascale Systems Research Center (GSRC) under contract no. 9278-1-1010315, the National Science Foundation (NSF) under grant no. CCR-9803774, the Office of Naval Research (ONR), the Naval Research Laboratory (NRL) under contract no. N00014-01-1-0796, the Army Research Office (ARO) under contract no. DAAD19-01-1-0485, and the General Motors Collaborative Research Lab at CMU. The views and conclusions contained in this document are those of the author and should not be interpreted as representing the official policies, either expressed or implied, of GSRC, NSF, ONR, NRL, ARO, GM, or the U.S. government.
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Clarke, E., Jain, H. & Kroening, D. Verification of SpecC using predicate abstraction. Form Method Syst Des 30, 5–28 (2007). https://doi.org/10.1007/s10703-006-0020-3
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DOI: https://doi.org/10.1007/s10703-006-0020-3