Abstract
High-performance computing systems consist of many modules of high complexity with billion transistors on a small silicon die. To design these mega functional systems, the common bus architecture poses a serious problem in terms of latency and throughput. To overcome the disadvantages of the common bus architecture, a new paradigm in ASIC design called the Network-on-Chip (NoC) was proposed. Several topologies like 2D mesh, torus, etc., were used to interconnect the different modules of the design using this novel idea. These topologies underperformed when scaled. This paper proposes a new architecture RiCoBiT: Ring Connected Binary Tree. It is a new scalable, structured architecture for Network-on-Chip based systems. An optimal routing algorithm for it has been designed. The paper discusses the different properties and performance parameters like maximum hop count, average hop count, number of wire segments, and wire length used to interconnect the nodes of RiCoBiT. These parameters are compared with that of 2D mesh and torus. The paper also discusses and bounds real-time parameters like latency and throughput.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
William J. Dally, Brian Towles, Route Packets Not Wires: on chip interconnection network, DAC 2001 June 2001.
Ahmed Hemani, Axel Jantsch, Shashi Kumar, Adam Postula, Johnny berg, Mikael Millberg, Dan Lindqvist, Network on a Chip: An architecture for billion transistor era, DAC 2001.
J. Nurmi: Network on Chip: A New Paradigm for System on Chip Design. Proceedings 2005 International Symposium on System on Chip, 15 17 November 2005.
Ville Rantala, Teijo Lehtonen, Juha Plosila, Network On Chip Routing Algorithms, TUCS Technical Report No 779, August 2006.
Tobias Bjerregaard And Shankar Mahadevan, A Survey of Research and Practices of Network on Chip, ACM Computing Survey March 2006.
Radu Marculescu, IEEE, Natalie Enright Jerger, Yatin Hoskote, Umit Y. Ogras and Li Shiuan Peh, Outstanding Research Problems in NoC Design: System, Micro architecture, and Circuit Perspectives, IEEE Transactions on computer aided design of integrated circuits and systems, vol. 28, no. 1, January 2009.
L. Benini, G. De Micheli. Networks on chips: A new SoC paradigm. IEEE Computer. 35(1), 2002.
S. Kumar, A. Jantsch, J. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani, A Network on Chip Architecture and Design Methodology, Proceedings International Symposium VLSI (ISVLSI), pp. 117–124, 2002.
Dan Marconett, A Survey of Architectural Design and Implementation Tradeoffs in Network on Chip Systems, University of California, Davis.
Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha, “A Power and Performance Model for Network-on-Chip Architectures”, Proceedings of the Design, Automation, and Test in Europe Conference and Exhibition (DATE), p. 21250, 2004. Transactions on Computers, vol. 54, no. 8, pp. 1025–1040, August, 2005.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer Science+Business Media Singapore
About this paper
Cite this paper
Sanju, V., Niranjan Chiplunkar (2017). RiCoBiT—Ring Connected Binary Tree: A Structured and Scalable Architecture for Network-on-Chip Based Systems: an Exclusive Summary. In: Satapathy, S., Bhateja, V., Joshi, A. (eds) Proceedings of the International Conference on Data Engineering and Communication Technology. Advances in Intelligent Systems and Computing, vol 469. Springer, Singapore. https://doi.org/10.1007/978-981-10-1678-3_4
Download citation
DOI: https://doi.org/10.1007/978-981-10-1678-3_4
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-1677-6
Online ISBN: 978-981-10-1678-3
eBook Packages: EngineeringEngineering (R0)