Abstract
The High Efficiency Video Coding (HEVC) standard has nearly doubled the compression efficiency of prior standards. Nonetheless, this increase in coding efficiency involves a notably higher computing complexity that should be overcome in order to achieve real-time encoding. For this reason, this paper focuses on applying parallel processing techniques to the HEVC encoder with the aim of reducing significantly its computational cost without affecting the compression performance. Firstly, we propose a coarse-grained slice-based parallelization technique that is executed in a multi-core CPU, and then, with finer level of parallelism, a GPU-based motion estimation algorithm. Both techniques define a heterogeneous parallel coding architecture for HEVC. Results show that speed-ups of up to 4.06\(\times \) can be obtained on a quad-core platform with low impact in coding performance.
This work was jointly supported by the Spanish Ministry of Economy and Competitiveness (MINECO) and the European Commission (FEDER funds) under projects TIN2015-66972-C5-2-R and TIN2015-66972-C5-4-R, and by the Spanish Ministry of Education, Culture and Sports under the grant FPU13/04601.
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Cebrián-Márquez, G., Migallón, H., Martínez, J.L., López-Granado, O., Piñol, P., Cuenca, P. (2016). GPU-Based Heterogeneous Coding Architecture for HEVC. In: Carretero, J., Garcia-Blas, J., Ko, R., Mueller, P., Nakano, K. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2016. Lecture Notes in Computer Science(), vol 10048. Springer, Cham. https://doi.org/10.1007/978-3-319-49583-5_41
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DOI: https://doi.org/10.1007/978-3-319-49583-5_41
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