Abstract
This chapter consists of two sections that cover algorithms and hardware architectures for modular addition and multiplication: (x + y) mod m and xy mod m. Subtraction and division are also included—as the addition of an inverse and as multiplication by an inverse. The underlying algorithms and hardware structures are those of Chap. 1, modified for modular arithmetic. For both operations we shall consider generic algorithms and hardware structures for arbitrary moduli and also those for special moduli.
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Notes
- 1.
Strictly, the first addition may be in n bits.
- 2.
Recall that such a compressor can be built to have a delay that is slightly larger than that through a 3:2 compressor.
- 3.
In ordinary multiplication the 2i factor is taken care of by shifting the partial product instead of the multiplicand multiple. That is possible because the lower order i bits of the ith partial product are not included in the corresponding addition. On the other hand, with modular multiplication—specifically the required reductions—all bits of a partial product must be included in the arithmetic; therefore, 2ixy i is taken in its entirety.
References
R. Zimmerman. 1999. Efficient VLSI implementation of modulo (2n ± 1) addition and multiplication. Proceedings, International Symposium on Computer Arithmetic, pp. 158–167.
H. T. Vergos and C. Efstathiou. 2008. A unifying approach for weighted and diminished-one modulo 2n + 1 addition. IEEE Transactions on Circuits and Systems II, 55:1041–1045.
L. Sousa and R. Chaves. 2005. A universal architecture for designing efficient modulo 2n + a multipliers. IEEE Transactions on Circuits and Systems I, 52(6):1166–1178.
R. Muralidharan and C.-H. Chang. 2012. Area-power efficient modulo 2n − 1 and modulo 2n + 1 multipliers for {2n − 1, 2n, 2n + 1} based RNS. IEEE Transactions on Circuits and Systems I, 59(10):2263–2274.
J. W. Chen, R. H. Yao, and W. J. Wu. 2011. Efficient modulo 2n + 1 multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(12):2149–2157.
M. Knezevic, F. Vercauteren, and I. Verbauwhede. 2010. Faster interleaved modular multiplication based on Barrett and Montgomery reduction methods. IEEE Transactions on Computers, 59(12):1715–17121.
H. Orup. 1995. Simplifying quotient determination in high-radix modular multiplication. In: Proceedings, 12th Symposium on Computer Arithmetic, pp. 193–199.
P. Kornerup. 1993. High-radix modular multiplication for cryptosystems. In: Proceedings, 12th Symposium on Computer Arithmetic, pp. 277–283.
A. V. Curiger, H. Bonennenberg, and H. Kaeslin. 1991. Regular VLSI architectures for multiplication modulo 2n + 1. IEEE Journal of Solid-State Circuits, 26(7):990–994.
M.-D. Shieh, J.-H. Chen, W.-C. Lin, and H.-H. Wu. 2009. A new algorithm for high-speed modular multiplication design. IEEE Transactions on Circuits and Systems I, 56(9): 2009–2019.
S.-R. Kuang, J. -P. Wang, K.-C. Chang, and H.-W. Hsu. 2013. Energy-efficient high-throughput Montgomery modular multipliers for RSA cryptosystems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(11):1999–2009.
A. Reza and P. Keshavarzi. 2015. High-throughput modular multiplication and exponentiation algorithms using multibit-scan—multibit-shift technique. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(9): 1710–1719.
S.-R. Kung, K.-Y. Wu, and R.-Y. Lu. 2016. Low-cost high-performance VLSI architecture for Montgomery modular multiplication. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(2):434–443.
J.-C. Bajard, L.-S. Didier, and P. Kornerup. 1998. An RNS Montgomery modular multiplication algorithm. IEEE Transactions on Computers , 47(7):766–776.
H. K. Garg and H. Xiao. 2016. New residue based Barrett algorithms: modular integer computations. IEEE Access, 4:4882–4890.
C. K. Koc. 1995. RSA Hardware Implementation. Report, RSA Laboratories. Redwood City, California, USA.
H. Orup and P. Kornerup. 1991. A high-radix hardware algorithm for calculating the exponential M E modulo N. Proceedings, 10th IEEE Symposium on Computer Arithmetic, pp. 51–56.
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R. Omondi, A. (2020). Modular Addition and Multiplication. In: Cryptography Arithmetic. Advances in Information Security, vol 77. Springer, Cham. https://doi.org/10.1007/978-3-030-34142-8_5
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